Semiconductor device using a dicing groove of a wafer to mount a capacitor and packaging method thereof

Abstract

The disclosed semiconductor device with a dicing groove mounted capacitor and packaging method thereof using a wafer relates to the technical field of semiconductors, and is convenient for optimizing the structural layout of the semiconductor device and improving packaging efficiency. The semiconductor device comprises a substrate layer, a power supply network and at least two dies arranged on the substrate layer, wherein the at least two dies comprise a first die and a second die arranged transversely and connected, and the first die and the second die each have a power supply pin; a dicing groove is arranged between the first die and the second die to form a block therebetween; and a capacitor is arranged in the dicing groove and connected to the power supply network. The semiconductor device is applicable to chip packaging, testing and high-density interconnection scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its packaging method that utilizes the dicing grooves of a wafer to mount capacitors. Background Technology

[0002] In the semiconductor manufacturing industry, a scribe lane is a block on a wafer that divides individual dies (sometimes also called bare dies). During the wafer slicing process, individual dies are cut off along the scribe lane.

[0003] With the development of high-speed chip interconnect technology, two or more dies may exist in a single semiconductor package device. Furthermore, with the rapid development of 3D stacking technology, the design and manufacturing process of semiconductor packaging is constantly evolving, providing possibilities for the reuse of dicing slots. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device and a packaging method thereof that utilizes the dicing grooves of a wafer to mount capacitors, which facilitates optimization of the structural layout of the semiconductor device and improves packaging efficiency.

[0005] To achieve the above-mentioned objectives, the following technical solution is adopted: According to a first aspect of the present invention, a semiconductor device is provided, comprising: A base layer, on which a power network and at least two dies are disposed, including a first die and a second die arranged laterally connected, the first die and the second die respectively having power pins; A dicing groove is provided between the first bare wafer and the second bare wafer, forming a block between the first bare wafer and the second bare wafer; A capacitor is provided in the dicing groove, and the capacitor is connected to the power network.

[0006] According to a specific implementation of an embodiment of this application, conductive traces are laid at the bottom of the dicing groove, and the conductive traces are led out and connected to the power network; The capacitor includes a first metal electrode plate and a second metal electrode plate, which are longitudinally distributed on different horizontal layers, and an insulating dielectric layer is disposed between the first metal electrode plate and the second metal electrode plate. The first metal electrode plate is connected to the conductive trace.

[0007] According to a specific implementation of an embodiment of this application, a grounding network is provided at the bottom of the substrate layer, the power network includes a power rail, the first metal electrode plate is connected to the power rail through the conductive trace, and the second metal electrode plate is connected to the grounding network.

[0008] According to one specific implementation of the embodiments of this application, one or more of the capacitors are provided in each block formed by the squaring slots.

[0009] According to a specific implementation of this application, the capacitor is located in the dicing slot at the position shortest from the power supply pin of the first die and the power supply pin of the second die, and is connected to the power supply pin.

[0010] According to a specific implementation of an embodiment of this application, the capacitor includes at least three metal electrode plates arranged in a vertical layer, with an insulating dielectric layer disposed between two adjacent metal electrode plates, forming a vertically stacked capacitor structure.

[0011] According to a specific implementation of an embodiment of this application, the capacitor includes: a pair of intercalation electrodes disposed opposite to each other, each intercalation electrode including a plurality of conductive tips arranged alternately above and below, wherein the conductive tips of one intercalation electrode are disposed in the space formed by two adjacent conductive tips above and below the other intercalation electrode, and an insulating dielectric layer is provided between the two adjacent conductive tips above and below, forming a longitudinally stacked capacitor structure.

[0012] According to one specific implementation of the present application, two or more capacitors are provided in each block formed by the squaring slot, and at least two capacitors have different sizes, shapes and capacitance values.

[0013] Secondly, embodiments of this application provide a method for packaging a semiconductor device, the method comprising: A substrate is provided, and a power network and a first and second die, laterally connected, are formed on its surface; wherein the first and second dies are connected by an uncut scribe groove. A capacitor placement area is formed in the dicing groove; Conductive traces are laid at the bottom of the dicing groove and led out to connect to the power network; A capacitor is formed in the capacitor placement area, and the capacitor is connected to the power network through the conductive trace.

[0014] According to a specific implementation of an embodiment of this application, forming a capacitor in the capacitor placement area includes: A first layer of metal electrode is deposited in the capacitor placement area of ​​the dicing groove; A thin insulating material is deposited on the first metal electrode to form an insulating dielectric layer; A second metal electrode layer is deposited on the insulating dielectric layer; Photolithography and etching are performed on the first and second metal electrodes, respectively, to form a first metal electrode plate and a second metal electrode plate.

[0015] According to a specific implementation of an embodiment of this application, the power network includes a power rail, and the method further includes: pre-arranging a grounding network at the bottom of the substrate layer, connecting a second metal electrode plate to the grounding network; and connecting the first metal electrode plate to the power rail through conductive traces laid at the bottom of the dicing groove.

[0016] The semiconductor device and its packaging method that utilize the dicing grooves of a wafer to mount capacitors, as provided in the embodiments of this application, achieve the reuse of the dicing grooves by retaining at least two dicing grooves between the two dies in the wafer dicing (slicing) process, mounting capacitors in the dicing grooves in the semiconductor packaging structure, and connecting them to the power network, thereby facilitating the optimization of the structural layout of the semiconductor device.

[0017] Furthermore, compared to the slicing process in traditional semiconductor packaging, which cuts off individual dies, this application retains a dicing groove between at least two dies during slicing, meaning the minimum cutting unit is two connected dies. This facilitates improved slicing efficiency during the packaging process, thereby increasing packaging efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of another embodiment of a semiconductor device; Figure 3 This is a schematic diagram of another embodiment of the semiconductor device of the present invention; Figure 4 This is a schematic flowchart of an embodiment of the semiconductor packaging device formation process of the present invention; Figure 5 This is a schematic diagram of an embodiment of the capacitor forming process in a dicing groove according to the present invention. Detailed Implementation

[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] Example 1 Figure 1 This is a schematic diagram of an embodiment of the semiconductor device of the present invention; please refer to it. Figure 1 As shown, the semiconductor device provided in this embodiment of the invention can be applied to semiconductor device packaging, testing, and high-density interconnection scenarios of chips. The semiconductor device is, for example, a chip, including: a substrate 100; a power network (not shown in the figure) and at least two dies are disposed on the substrate 100, wherein the at least two dies include a first die 110 and a second die 120 arranged laterally connected, and the first die 110 and the second die 120 respectively have power pins for connecting to the power network to supply power.

[0023] A dicing groove 130 is disposed between the first die 110 and the second die 120, forming a block between them. This dicing groove 130 is retained during the wafer dicing process. By reusing the original dicing groove and filling it with a capacitor 140, the robustness of the power network against noise can be enhanced. Specifically, the capacitor 140 is a decoupling capacitor, connected to a node of the power network and positioned close to the load device. It effectively filters high-frequency noise and provides additional current for transient loads, thereby enhancing the stability of the power network for semiconductor devices.

[0024] Capacitor 140 can be customized to meet specific application requirements, such as different sizes, shapes, materials and structures, to meet the decoupling requirements of the chip at different operating frequencies and ensure that the power network remains stable under dynamic load changes.

[0025] The semiconductor device utilizing dicing grooves on a wafer, provided in this embodiment of the invention, achieves the reuse of dicing grooves by retaining at least two dies between them during the wafer dicing (slicing) process. In the semiconductor packaging structure, capacitors are mounted on these dicing grooves and connected to a power network, facilitating the optimization of the semiconductor device's structural layout. Furthermore, by reusing the dicing grooves to incorporate capacitors and connecting them to the power network, the robustness of the power network against noise is enhanced.

[0026] Furthermore, compared to the slicing process in traditional semiconductor packaging, which cuts off individual dies, this application retains a dicing groove between at least two dies during slicing, meaning the minimum cutting unit is two connected dies. This facilitates improved slicing efficiency during the packaging process, thereby increasing packaging efficiency.

[0027] See Figure 2 As shown, according to the technical concept of the present invention, this solution can also be extended to a solution with four, six or more interconnect chips. In the slicing process, the smallest slicing unit can be four, six, etc., retaining more dicing slots to be applied to scenarios that require four or six interconnected chips. This can not only improve wafer slicing efficiency, but also improve chip packaging efficiency.

[0028] Furthermore, by retaining the dicing grooves, the two connected chips are integrated into a single unit, resulting in a multi-chip interconnect structure with better mechanical strength.

[0029] In some embodiments, conductive traces (not shown) are laid at the bottom of the dicing groove 130, and the conductive traces are led out and connected to the power network (not shown). By providing conductive traces at the bottom of the dicing groove 130, power signals can be effectively transmitted to the capacitor 140 filled in the dicing groove, thereby achieving a more efficient decoupling effect.

[0030] See Figure 3 As shown in the figure, MT represents the metal layer. The capacitor 140 includes a first metal electrode plate 141 and a second metal electrode plate 142. The first metal electrode plate 141 and the second metal electrode plate 142 are longitudinally distributed on different horizontal layers, and an insulating dielectric layer 143 is disposed between the first metal electrode plate 141 and the second metal electrode plate 142.

[0031] In this embodiment, the first metal electrode plate 141 is connected to the conductive trace to facilitate the direct introduction of power signals into the capacitor 140. This allows the capacitor 140 to quickly respond to dynamic load changes in the power network, improving the system's ability to suppress transient noise.

[0032] In the design of high-performance semiconductor devices, especially chips, the layout of power and ground networks is crucial to system stability and interference immunity. Traditional power and ground designs often face problems such as power supply noise and ground interference, which can lead to decreased signal integrity and system instability. Therefore, how to effectively combine power and ground networks to improve overall performance is a technical problem that urgently needs to be solved.

[0033] Therefore, in some embodiments, a grounding network (not shown) is provided at the bottom of the substrate 100. The power network includes a power rail, the first metal electrode plate 141 is connected to the power rail via the conductive trace, and the second metal electrode plate 142 is connected to the grounding network.

[0034] In this embodiment, by setting a grounding network at the bottom of the substrate layer 100, the common-mode noise in the semiconductor package device can be effectively reduced, and a stable reference potential can be provided for the capacitor 140. By connecting the first metal electrode plate 141 to the power rail and the second metal electrode plate 142 to the grounding network, a good decoupling path can be formed between the capacitor 140 and the power network, thereby improving the response capability to transient load changes and improving the working performance and reliability of the entire semiconductor device.

[0035] See Figure 1 and Figure 2 As shown, in some embodiments, one or more of the capacitors are provided in each block formed by the slicing slots.

[0036] In the design of high-performance electronic devices, it is particularly important to rationally configure the number, size, shape, and capacitance value of capacitors to meet decoupling requirements under different frequencies and load conditions. Traditional designs often use only a single type of capacitor, which cannot meet diverse power supply noise suppression requirements.

[0037] Specifically, each block formed by the slicing slot 130 has two or more capacitors 140. At least two capacitors have different sizes, shapes and capacitance values ​​to accommodate decoupling requirements at different frequencies.

[0038] Continue reading Figure 1 In this embodiment, multiple capacitors 140 can be disposed within the dicing slot 130, wherein the first capacitor and the second capacitor have different sizes, shapes, and capacitance values. For example, the first capacitor 1 can be designed with a smaller size and a lower capacitance value to provide a fast response under high-frequency signals; while the second capacitor can be designed with a larger size and a higher capacitance value to provide better decoupling under low-frequency signals.

[0039] Furthermore, to further enhance decoupling performance, a third capacitor 146 can be placed within the same block. This third capacitor, with a different shape and material than the first two, can achieve a wider frequency response. This diverse configuration allows the capacitors in each diced slot to work collaboratively, effectively suppressing noise across different frequency ranges, thereby improving the stability and reliability of the entire semiconductor device.

[0040] Understandably, capacitor performance affects the stability and interference immunity of the power network. Optimizing the thickness of the metal plates and the dielectric constant of the insulating dielectric layer is crucial to capacitor performance. In some embodiments, the thickness of the first metal electrode plate 141 and the second metal electrode plate 142 is ≤1 micrometer, and the dielectric constant of the insulating dielectric layer 143 is between 3.5 and 10, and can be selected from materials such as polyester, polytetrafluoroethylene (PTFE), or other high dielectric constant materials.

[0041] In this embodiment, through simulation testing and verification during the chip design process, the above-mentioned parameters of the first metal electrode plate 141 and the second metal electrode plate 142 can not only effectively reduce the capacitor volume, but also improve the response capability of the capacitor in the semiconductor package device to transient signals because the thinner metal electrode plate helps to reduce parasitic inductance.

[0042] In the design of chip power networks, the layout and position of capacitors are crucial to their decoupling effect. In some embodiments, the capacitor 140 is disposed in the dicing slot 130 at the position where it is shortest from the power supply pins of the first die 110 and the second die 120, and is connected to the power supply pins.

[0043] In this embodiment, capacitor 140 is placed within the dicing slot 130 to minimize the distance between it and the power supply pins of the first die 110 and the second die 120. When the supply voltage of the power network fluctuates due to changes in load current, the capacitor can temporarily store charge, mitigating voltage fluctuations and making the power supply voltage received by the chip more stable. Furthermore, placing the capacitor close to the power supply pins of the first and second dies reduces power supply ripple, improves the reliability of digital signals, and enhances the overall performance and stability of the semiconductor packaged device.

[0044] In some technical solutions, the capacitor may include any one or a combination of two or more of the following three types of capacitors: MOM capacitor, MIM capacitor, and Device capacitor.

[0045] Among them, MOM low capacitance utilizes the C between the edges of the same layer of metal, and in order to save area, multiple metal layers can be stacked.

[0046] MIM (Metal Injection Molding) utilizes the capacitance between two metal layers, i.e., plate capacitance. The lower plate is Mn, and the upper plate is Mn+1. Because ordinary Mn and Mn+1 are relatively far apart in three-dimensional space due to the oxide layer, the capacitance value is not large. In this embodiment, a photomask, such as MCT (Metal Contact Thread), is introduced into the MIM capacitor. This layer is made on top of Mn and below Mn+1. A metal wire is inserted between the two metal layers. These metal wires are connected to the upper or lower metal layer through vias, which reduces the distance between the plates, increases the capacitance, and forms a more compact capacitor structure.

[0047] Generally, the three types of capacitors mentioned above can be used in combination. For example, high-voltage capacitive load removal can be achieved by using device capacitors plus analog product capacitors (MOM capacitors) on the SMIC 40nm process (smic40 process), which is commonly referred to in the industry as HV Decap. During evaluation, a 50μm × 50μm capacitor unit is used for testing, and the measured capacitance value is approximately 20 pF.

[0048] In some embodiments, the capacitor 140 includes at least three metal electrode plates arranged in a longitudinal layer, with an insulating dielectric layer 144 disposed between two adjacent metal electrode plates, forming a longitudinally stacked capacitor structure.

[0049] In this embodiment, by forming a vertically stacked capacitor structure, a larger effective capacitance value can be provided within the limited space of the dicing slot, thereby improving the space utilization of the semiconductor packaging device.

[0050] The design structure of a capacitor has a significant impact on its electrical performance and space utilization. In some embodiments, capacitor 140 includes a pair of intercalation electrodes disposed opposite each other, each intercalation electrode including a plurality of conductive tips arranged alternately vertically. Specifically, the conductive tips of one intercalation electrode are disposed within the space formed by two adjacent conductive tips of the other intercalation electrode 142, and an insulating dielectric layer 144 is provided between the two adjacent conductive tips, thereby forming a vertically stacked capacitor structure.

[0051] In this embodiment, by arranging the conductive tips of a pair of opposing interposed electrodes in an alternating manner, multiple vertically stacked capacitors can be formed. This not only improves the energy storage capacity of the capacitors but also significantly reduces parasitic inductance and resistance, enhances the system's response speed to transient load changes, and makes reasonable use of the limited space of the dicing slot.

[0052] The conductive fingertip of each interdigital electrode can be made of a highly conductive material, such as copper or aluminum. Each pair of interdigital electrodes has at least three conductive fingertips.

[0053] In summary, the semiconductor packaging device provided by the embodiments of the present invention, which utilizes the dicing groove of a wafer to connect a power network and mount a capacitor, effectively utilizes the space that may be wasted on the wafer structure. By setting a capacitor in the dicing groove, the noise immunity of the power network can be enhanced, and the overall performance of the integrated circuit can be improved.

[0054] This invention also provides a semiconductor packaging method, which can be used in the packaging process of the semiconductor packaging device provided in the foregoing embodiments. Referring to the figure, method S200 includes the following steps: S210. A substrate layer is provided, and a power network and a first die and a second die that are laterally connected are formed on its surface; wherein the first die and the second die are connected by an uncut dicing groove.

[0055] In this embodiment, specifically, step S210 includes: selecting silicon, gallium arsenide, or other semiconductor materials as the substrate material, and cleaning and surface treating them to remove surface impurities and oxides, ensuring good adhesion for subsequent processes. A power network is formed on the substrate surface using photolithography and etching techniques. Exemplarily, photoresist is coated onto the substrate and exposed; unexposed areas are removed by development; and unwanted materials on the substrate are removed using dry or wet etching, leaving power rails. An adhesive material (such as epoxy resin or other thermally conductive adhesive) is used to bond the first and second dies to the surface of the substrate, ensuring a strong connection between the dies and the substrate.

[0056] S220, A capacitor placement area is formed in the dicing groove.

[0057] Within the dicing groove, a capacitor placement area is etched out for subsequent capacitor formation in the capacitor placement area. The size and shape of this area should be adapted to the pre-defined capacitor type.

[0058] S230. Lay a conductive trace at the bottom of the dicing groove and lead it out to connect to the power network.

[0059] Conductive traces are laid at the bottom of the dicing groove using thin-film deposition or printing techniques. These traces are connected to the power network to ensure that the capacitor can effectively receive electrical signals from the power network. The conductive traces should be laid out as straight as possible, with each trace having a width of 5μm to 50μm, a spacing of 5μm to 50μm between adjacent traces, and a thickness of 0.5μm to 2μm. This is done to minimize parasitic inductance and resistance to improve signal transmission efficiency.

[0060] S240. A capacitor is formed in the capacitor placement area, and the capacitor is connected to the power network through the conductive trace.

[0061] In this embodiment of the invention, when achieving high-density chip interconnection, by retaining at least two dicing slots between dies during the wafer dicing (slicing) process, and using these dicing slots to mount capacitors and connect them to the power network during semiconductor packaging, the dicing slots are reused. This facilitates optimization of the semiconductor device's structural layout. Furthermore, since it is not necessary to cut off each die individually during packaging preparation, such as the wafer dicing process, and the minimum cutting unit is two connected dies, the dicing efficiency during the packaging process can be improved, thereby increasing packaging efficiency.

[0062] In some embodiments, forming a capacitor in the capacitor placement area (S220) includes: S221. Deposit a first layer of metal electrode in the capacitor placement area of ​​the dicing groove; The first metal electrode layer can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques. The deposition thickness is controlled between 0.5 μm and 2 μm to ensure good electrical conductivity and mechanical strength.

[0063] S222. A thin insulating material is deposited on the first metal electrode to form an insulating dielectric layer; Among them, the insulating material includes silicon dioxide ( ), silicon nitride ( Materials used include polyimide (PI) or other materials. The thickness of the insulating dielectric layer is typically controlled between 0.1 μm and 1 μm to ensure good dielectric properties while maintaining a small footprint.

[0064] S223. Deposit a second metal electrode layer on the insulating dielectric layer; A second metal electrode layer is deposited on the insulating dielectric layer using PVD or CVD technology. This second metal electrode layer should have the same material parameters as the first metal electrode layer.

[0065] S224. Photolithography and etching are performed on the first metal electrode layer and the second metal electrode layer respectively to form the first metal electrode plate and the second metal electrode plate.

[0066] After the deposition of the aforementioned metal electrodes is completed, photolithography is used to pattern the first and second metal electrode layers. Specifically, photoresist is coated and exposed, followed by development to remove unexposed areas. Subsequently, dry or wet etching techniques are used to remove unwanted metal material, forming the first and second metal electrode plates. The photoresist is then removed, thereby forming the desired capacitor structure.

[0067] In other embodiments, the power network includes power rails, and the method further includes: A grounding network is pre-arranged at the bottom of the base layer, and the second metal electrode plate is connected to the grounding network. In addition, the first metal electrode plate is connected to the power rail through conductive traces laid at the bottom of the dicing groove.

[0068] The semiconductor device and its packaging method that utilize the dicing grooves of a wafer to mount capacitors, provided by the embodiments of the present invention, achieve the reuse of the dicing grooves by retaining at least two dicing grooves between the two dies in the wafer dicing (slicing) process, mounting capacitors in the dicing grooves in the semiconductor packaging structure, and connecting them to the power network, thereby facilitating the optimization of the structural layout of the semiconductor device.

[0069] Furthermore, compared to the slicing process in traditional semiconductor packaging, which cuts off individual dies, this application retains a dicing groove between at least two dies during slicing, meaning the minimum cutting unit is two connected dies. This facilitates improved slicing efficiency during the packaging process, thereby increasing packaging efficiency.

[0070] Meanwhile, by reusing the dicing slots and adding capacitors, which are then connected to the power network, the robustness of the power network against noise is enhanced, thereby improving the performance of the semiconductor packaged devices.

[0071] One or more embodiments in this embodiment are described by reference or cross-reference and can be seen in each other.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A base layer, wherein a power network and at least two dies are disposed on the base layer, wherein the at least two dies include a first die and a second die arranged laterally connected, and the first die and the second die respectively have power pins; A dicing groove is provided between the first bare wafer and the second bare wafer, forming a block between the first bare wafer and the second bare wafer; A capacitor is provided in the dicing groove, and the capacitor is connected to the power network.

2. The semiconductor device according to claim 1, characterized in that, Conductive traces are laid at the bottom of the dicing groove, and the conductive traces are led out and connected to the power network; The capacitor includes a first metal electrode plate and a second metal electrode plate, which are longitudinally distributed on different horizontal layers, and an insulating dielectric layer is disposed between the first metal electrode plate and the second metal electrode plate. The first metal electrode plate is connected to the conductive trace.

3. The semiconductor device according to claim 2, characterized in that, A grounding network is provided at the bottom of the substrate layer. The power network includes a power rail. The first metal electrode plate is connected to the power rail through the conductive trace, and the second metal electrode plate is connected to the grounding network.

4. The semiconductor device according to claim 1, characterized in that, Each block formed by the squaring slots is equipped with one or more of the aforementioned capacitors.

5. The semiconductor device according to claim 1, characterized in that, The capacitor is positioned in the dicing groove at the shortest distance from the power supply pins of the first die and the second die, and is connected to the power supply pins.

6. The semiconductor device according to claim 1, characterized in that, The capacitor includes at least three metal electrode plates arranged in a vertical layer, with an insulating dielectric layer between two adjacent metal electrode plates, forming a vertically stacked capacitor structure.

7. The semiconductor device according to claim 1, characterized in that, The capacitor includes: a pair of intercalation electrodes disposed opposite to each other, each intercalation electrode including a plurality of conductive tips arranged alternately above and below, wherein the conductive tips of one intercalation electrode are disposed in the space formed by two adjacent conductive tips above and below the other intercalation electrode, and an insulating dielectric layer is provided between the two adjacent conductive tips above and below, forming a longitudinally stacked capacitor structure.

8. The semiconductor device according to claim 1, characterized in that, Each slab formed by the slab is equipped with two or more capacitors, at least two of which have different sizes, shapes and capacitance values.

9. A method for packaging a semiconductor device, characterized in that, The method includes: A substrate is provided, and a power network and a first and second die, laterally connected, are formed on its surface; wherein the first and second dies are connected by an uncut scribe groove. A capacitor placement area is formed in the dicing groove; Conductive traces are laid at the bottom of the dicing groove and led out to connect to the power network; A capacitor is formed in the capacitor placement area, and the capacitor is connected to the power network through the conductive trace.

10. The semiconductor device packaging method according to claim 9, characterized in that, The formation of a capacitor in the capacitor placement area includes: A first layer of metal electrode is deposited in the capacitor placement area of ​​the dicing groove; A thin insulating material is deposited on the first metal electrode to form an insulating dielectric layer; A second metal electrode layer is deposited on the insulating dielectric layer; Photolithography and etching are performed on the first and second metal electrodes, respectively, to form a first metal electrode plate and a second metal electrode plate.

11. The semiconductor device packaging method according to claim 10, characterized in that, The power network includes power rails, and the method further includes: A grounding network is pre-arranged at the bottom of the base layer, and the second metal electrode plate is connected to the grounding network. In addition, the first metal electrode plate is connected to the power rail through conductive traces laid at the bottom of the dicing groove.

Images