一种碳化硅MOSFET器件及其制造方法
By employing a double-layer sidewall self-alignment process in silicon carbide MOSFET devices, the problems of high source region contact resistance and gate oxide reliability are solved, achieving a reduction in contact resistance and an improvement in device performance, while also supporting device miniaturization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HESTIA POWER INC
- Filing Date
- 2026-04-24
- Publication Date
- 2026-07-17
AI Technical Summary
Existing silicon carbide MOSFET devices suffer from high contact resistance, severe lattice damage, and gate oxide layer reliability issues during source region doping, especially with significant impacts from photolithography alignment deviations during miniaturization.
A dual-sidewall self-alignment process is adopted. By forming a source region structure in the p-type well region, the lateral offset of the first and second n-type regions and the buffer gap are used to reduce the contact resistance and protect the gate oxide layer, avoiding phosphorus implantation damage.
It effectively reduces the contact resistance of the source region, improves the device's conduction performance, and eliminates the influence of photolithographic alignment deviation through self-alignment technology, supporting device miniaturization.
Smart Images
Figure CN122121228B_ABST