An LED and IC combined encapsulation packaging structure

Abstract

The application relates to the technical field of semiconductor packaging, and discloses a packaging structure for combining and packaging an LED and an IC, which comprises an IC chip and a Micro LED chip vertically combined above the front surface of the IC chip; the IC chip is internally integrated with a driving circuit and has metal welding spots distributed on the top surface and matched with the electrodes of the Micro LED chip; the IC chip and the Micro LED chip form a three-dimensional stacked integrated structure through a metal bonding layer; the physical projection of the Micro LED chip is located in the projection range of the IC chip; the IC chip is provided with a conductive mechanism for leading out signals, and the conductive mechanism comprises surface bumps distributed on the edges of the front surface, vertical conductive columns penetrating the interior, back welding balls on the back surface, back cut positions in the form of slopes on the edges, and a metal coating layer covering the back cut positions and connecting the front circuit and the back welding balls. The application realizes miniaturization of the packaging size and improves display transmittance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a packaging structure that encapsulates an LED and an IC. Background Technology

[0002] Currently, transparent display technology is at a critical stage of transitioning towards high pixel density, and the miniaturization of pixel pitch has become the mainstream trend in the industry. In transparent screen designs with P2.5 and finer pixel pitches, the physical space occupied by the package unit directly determines the transparency of the display panel. Due to the limitations of package size, how to balance pixel resolution and light transmittance within a limited display area has become a core issue that urgently needs to be addressed in the current semiconductor display field.

[0003] Regarding the aforementioned aspects, traditional packaging methods generally employ horizontal layout logic. The driver IC and the red, green, and blue LED chips are placed at the same plane height and fixed to an external support, ceramic substrate, or printed circuit board surface using upright wire bonding or flip-chip bonding processes. In this structure, electrical signals are transmitted horizontally on the substrate surface. The necessary mechanical support and electrical interconnection paths are provided by external carriers, and the driver IC and LED chips complete functional assembly through a lateral parallel arrangement.

[0004] The existing packaging logic has shortcomings in practical applications. First, the device's external dimensions are limited. Horizontal arrangement means the projected area of ​​the package unit is always greater than the sum of the areas of the driver IC and each color LED chip. This cumulative effect of physical dimensions makes it difficult to achieve deep miniaturization of the package, hindering the development of ultra-small pitch displays. Second, structural redundancy leads to poor light transmittance. The system must rely on an additional carrier substrate. Since the substrate itself has a non-negligible thickness and is opaque, this not only increases the overall structural thickness but also results in an excessively high proportion of non-light-emitting components per unit area, directly reducing the overall light transmittance of the transparent screen. Finally, the optoelectronic layout affects the light emission quality. With the driver IC and LED chips at the same horizontal plane, the physical contour of the driver components creates lateral obstruction. This not only leads to a decrease in light extraction rate but also causes uneven distribution of viewing angle brightness, making it difficult to meet the visual requirements of high-quality displays.

[0005] Therefore, the present invention provides a package structure for co-encapsulating LEDs and ICs to overcome the shortcomings of the prior art. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a package structure that combines LED and IC, solving the problems of size redundancy, obstructed light emission path, and reliance on external substrates that limit the transparency of transparent displays caused by the horizontal arrangement of driver chips and light-emitting chips in existing packaging structures.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] An LED and IC co-packaged structure includes an IC chip, wherein a Micro LED chip is mounted on the top side of the IC chip;

[0009] The IC chip integrates a driving circuit for controlling the light-emitting unit. Metal solder joints adapted to the electrodes of the Micro LED chip are distributed on the top side of the IC chip. The IC chip and the Micro LED chip form a three-dimensional stacked integrated structure through a metal bonding layer. The physical projection area of ​​the Micro LED chip is located within the physical projection range of the IC chip. A conductive mechanism for extracting electrical signals is provided on the IC chip. The conductive mechanism includes surface bumps distributed around the Micro LED chip and located on the front edge of the IC chip. A vertical conductive pillar penetrates the interior of the IC chip. A back solder ball is provided on the back side of the IC chip. A sloping back-cut position is formed at the edge of the IC chip extending towards the top surface. The back-cut position connects the front circuit of the IC chip to the outer surface of the back solder ball, which is covered by a metal cladding layer.

[0010] Preferably, the Micro LED chip comprises a chip array consisting of red Micro LED chips, green Micro LED chips, and blue Micro LED chips arranged at a preset pixel spacing;

[0011] The chip array is fixed to the top side of the IC chip using an integral wafer bonding process or a step-by-step sequential bonding process.

[0012] Preferably, the top surface of the IC chip is divided into a central core functional area and an edge lead-out area located around the core functional area;

[0013] The Micro LED chip is fixed to the core functional area, and the surface bumps are disposed in the edge lead-out area.

[0014] Preferably, the vertical height of the surface bumps is lower than or equal to the top surface height of the Micro LED chip, in order to prevent the surface bumps from physically blocking the light-emitting path of the Micro LED chip;

[0015] The surface bumps include metal tin balls formed by a solder balling process, conductive bumps formed by solder paste printing, or copper pillars with solder caps formed by an electroplating process.

[0016] Preferably, the vertical conductive pillars are arranged in an array inside the IC chip, and the positions of the vertical conductive pillars avoid each other with the driving circuit logic units inside the IC chip.

[0017] Preferably, the vertical conductive pillar is a copper pillar that penetrates the silicon substrate of the IC chip;

[0018] A metal seed layer, a diffusion barrier layer, and an insulating layer are sequentially disposed between the sidewall of the vertical conductive post and the silicon substrate from the inside out, thereby electrically isolating the vertical conductive post from the silicon substrate.

[0019] Preferably, the back solder balls are disposed on the back metal pads on the back side of the IC chip;

[0020] The centerline of the back solder ball coincides with the axis of the vertical conductive post in the vertical direction.

[0021] Preferably, the back-cutting position is a thinning groove provided on the edge of the IC chip, and the angle between the inclined surface of the back-cutting position and the horizontal plane of the IC chip is 30 degrees to 60 degrees, which is used to provide a physical support surface for the metal cladding layer.

[0022] Preferably, the metal cladding layer is applied to the beveled surface of the back-cut position by physical vapor deposition or electroplating, and an insulating dielectric layer is disposed between the metal cladding layer and the silicon substrate of the IC chip.

[0023] Preferably, the sidewall of the IC chip is a single-piece cut surface; the single-piece cut surface is located outside the surface protrusion, or the single-piece cut surface is located at the center line of the back cut and exposes the metal cladding layer.

[0024] This invention provides a package structure for co-encapsulating LEDs and ICs. It offers the following advantages:

[0025] 1. This invention vertically stacks Micro LED chips on top of the front of an IC chip, limiting the horizontal projected area of ​​the entire packaging unit to within the size range of the IC chip, thus eliminating the gaps between chips in traditional horizontal arrangement schemes. This highly integrated three-dimensional structure reduces the non-light-emitting area of ​​display pixels. When applied to high-pixel-density transparent display scenarios, it can leave more light-transmitting space while maintaining resolution, thereby improving the overall light transmittance performance of the display screen.

[0026] 2. This invention, by having the IC chip simultaneously perform both driving circuitry and physical support functions, directly replaces the brackets, ceramic substrates, or printed circuit boards required in traditional packaging processes. This design reduces the number of material layers inside the package and lowers the overall structural thickness, which not only helps to achieve thinner and lighter display devices but also reduces the accumulation of thermal resistance and mechanical stress caused by the stacking of heterogeneous materials, thus enhancing the physical stability of the packaging structure.

[0027] 3. The vertical encapsulation structure of this invention creates the shortest electrical connection path between the driving unit on the IC chip surface and the Micro LED chip. This interconnection method effectively reduces parasitic resistance and inductance caused by long-distance wiring, improves signal response speed, and reduces power consumption. Combined with various conductive path designs such as surface bumps, vertical conductive pillars, or side metal cladding layers, this invention can flexibly adapt to the mounting requirements of various substrates, ensuring stable optoelectronic performance even under high-frequency driving. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a surface-mounted ball packaging structure according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a TSV vertical through-package structure according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the back-cutting process according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of a finished product of a back-cut side wiring packaging structure according to an embodiment of the present invention.

[0032] Among them, 1. IC chip; 2. Micro LED chip; 3. Surface bumps; 4. Vertical conductive pillars; 5. Back solder balls; 6. Back cut position; 7. Metal cladding layer. Detailed Implementation

[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] See attached document Figure 1 The present invention provides a package structure for encapsulating LED and IC, which mainly consists of IC chip 1 and Micro LED chip 2 vertically bonded to the surface of IC chip 1.

[0035] IC chip 1 is constructed as a composite component that simultaneously possesses circuit driving and physical support functions. IC chip 1 integrates a complementary metal-oxide-semiconductor driving circuit for controlling the light-emitting unit, and its top surface has metal solder joints precisely matched to the electrode positions and dimensions of Micro LED chip 2. IC chip 1 not only provides the necessary driving current and logic control signals to Micro LED chip 2, but also serves as the mechanical support substrate for the entire packaging structure, directly replacing the bracket, ceramic substrate, or printed circuit board substrate that must be used in traditional packaging technologies.

[0036] Micro LED chip 2 and IC chip 1 form a three-dimensional stacked structure in the vertical direction. In this vertically stacked layout, the physical projection area of ​​Micro LED chip 2 falls entirely within the physical projection area of ​​IC chip 1. Through this high degree of vertical spatial integration, the package's dimensions in the horizontal plane are limited to the side length of IC chip 1, thereby eliminating the extra spacing caused by the side-by-side placement of IC chip 1 and Micro LED chip 2 in traditional horizontal arrangement schemes, and achieving miniaturization of the package size.

[0037] In this packaging structure, IC chip 1 is located at the bottom layer, and Micro LED chip 2 is located at the top layer. The two are electrically connected and mechanically fixed together by a metal bonding layer. The light-emitting surface of Micro LED chip 2 faces away from IC chip 1, ensuring that the light is not blocked by the driving circuit or external carrier during outward radiation. Because IC chip 1 and Micro LED chip 2 are at different physical height levels, no component of IC chip 1 will enter the light-emitting path of Micro LED chip 2. This ensures the uniformity of light emission distribution in the physical structure and eliminates the problem of reduced light extraction efficiency caused by horizontal shading in traditional structures.

[0038] This three-dimensional packaging logic creates the shortest electrical transmission path between the driving unit on the surface of IC chip 1 and the Micro LED chip 2 above it. This shortest path connection effectively reduces parasitic resistance and inductance caused by long-distance traces, improving signal transmission quality and response speed. When applied to high-pixel-density scenarios such as transparent displays, this vertical encapsulation structure minimizes the space occupied by non-light-emitting components per unit area while ensuring the integrity of pixel unit functionality, thus providing a physical basis for improving the overall light transmittance of the structure.

[0039] In the monolithic construction of this package structure, the edge region of IC chip 1 is endowed with different structural features depending on the different pin lead-out schemes. For example, in some embodiments, the edge region of IC chip 1 is used to fabricate surface pins, while in other embodiments, the interior or sides of IC chip 1 are processed to form conductive paths that lead signals to the back side. Regardless of the pin lead-out method used, the core structure always maintains the structural relationship of IC chip 1 as a carrier substrate and Micro LED chip 2 being vertically stacked.

[0040] This invention provides a packaging structure for co-packaging LEDs and ICs. Before carrying out the specific packaging and assembly process, wafer-level pre-preparation is required.

[0041] In the wafer-level pre-processing stage, metallization is first performed on the wafer surface of IC chip 1 to fabricate metal solder joints that match the electrode dimensions and spacing of Micro LED chip 2. These metal solder joints are distributed in the opening area of ​​the top layer circuit of IC chip 1, and their physical arrangement strictly follows the spacing design of display pixels to ensure that each Micro LED chip 2 can form a one-to-one electrical path with the driving circuit inside IC chip 1 when vertically stacked.

[0042] A solder layer is pre-fabricated on the metal solder joints on the surface of IC chip 1. The material choices for this solder layer include gold-tin alloy, gold-indium alloy, pure tin, or tin-based alloy. The solder layer is prepared using vacuum evaporation or sputtering processes in physical vapor deposition, or electroplating to uniformly deposit the metal solder onto specific solder joint areas on the surface of IC chip 1. The thickness and composition ratio of the solder layer are precisely controlled to ensure that, during subsequent bonding processes, the solder layer can form a stable eutectic alloy or diffusion bonding layer under preset pressure and temperature conditions, thereby achieving mechanical fixation and electrical signal transmission between IC chip 1 and Micro LED chip 2.

[0043] The fabrication process of Micro LED chip 2 includes epitaxial growth of red, green, or blue light-emitting epitaxial layers on growth substrates such as sapphire, gallium arsenide, or silicon, followed by dicing the epitaxial layers into micrometer-scale independent chip units using semiconductor micro / nano fabrication processes. Laser lift-off technology is then used to separate the Micro LED chips 2 from the original growth substrate and transfer them to a temporary carrier substrate. During this transfer, the Micro LED chips 2 of different colors are rearranged at preset intervals according to the pixel arrangement requirements of the target display product, forming a chip array structure with a specific arrangement step.

[0044] During the formation of the aforementioned chip array structure, the red, green, and blue Micro LED chips 2 are precisely placed on the carrier medium with their electrode surfaces exposed to the outside, so as to interface with the solder layer on the surface of the IC chip 1. This preparation process ensures that the Micro LED chips 2 on the entire wafer are spatially aligned with the driving units on the IC chip 1 wafer, providing a structural basis for subsequent large-scale wafer-level bonding.

[0045] Wafer-level preparation also involves optimizing the surface flatness of IC chip 1. Chemical mechanical polishing (CMP) is used to reduce the surface roughness of the solder layer, ensuring it meets the flatness requirements for diffusion bonding. Simultaneously, the electrode surfaces of Micro LED chip 2 require cleaning and oxide removal to reduce contact resistance and improve post-bonding connection reliability.

[0046] Through the above-mentioned wafer-level preparations, the chip array structure of IC chip 1 wafer and Micro LED chip 2 has met the requirements of the encapsulation process in terms of physical size, electrode arrangement and surface condition, supporting the realization of the subsequent three-dimensional stacked structure.

[0047] This invention provides a packaging structure for co-packaging LED and IC. After completing wafer-level pre-preparation, the physical connection and electrical interconnection between IC chip 1 and Micro LED chip 2 are achieved through wafer-level bonding process.

[0048] During the bonding process, the pre-arranged array of Micro LED chips 2 is precisely aligned with the IC chip 1 wafer. The alignment process utilizes an infrared alignment device or a binocular vision alignment system to ensure that the center lines of the electrodes of the Micro LED chips 2 coincide with the center lines of the metal solder joints on the surface of the IC chip 1. After alignment, the substrate containing the Micro LED chips 2 is pressed together with the IC chip 1 wafer and placed in a vacuum bonding furnace for thermo-press bonding.

[0049] During the thermocompression bonding process, the bonding equipment applies a preset vertical pressure to IC chip 1 and Micro LED chip 2, while simultaneously raising the ambient temperature above the melting point or eutectic point of the solder layer. Under the action of thermocompression, the solder layer undergoes a change in physical properties, undergoing atomic diffusion or forming a eutectic alloy phase with the electrode material on the surface of Micro LED chip 2 and the metal solder joints on the surface of IC chip 1, thereby forming a dense metal bonding interface between IC chip 1 and Micro LED chip 2. This interface provides mechanical support strength while establishing a low-resistivity conductive path.

[0050] The bonding process offers several sequential options depending on the integration requirements of the Micro LED chip 2. In one embodiment, an integral wafer bonding scheme is employed, where an array of Micro LED chips 2 containing red, green, and blue colors is bonded to the IC chip 1 wafer in a single step. In this method, the Micro LED chips 2 of different colors are pre-arranged on the same substrate according to pixel pitch, and the vertical bonding of the full-color pixel units is achieved through a single cyclic heating and pressurizing process.

[0051] In another implementation, a step-by-step sequential bonding scheme is employed. The specific process is as follows: First, the Micro LED chip 2 of the first color is bonded to the corresponding position on the IC chip 1 wafer. Then, the bonding operations of the Micro LED chips 2 of the second and third colors are performed sequentially. Step-by-step bonding includes either bonding one color of Micro LED chip 2 first, then simultaneously bonding the next two colors, or bonding two colors of Micro LED chip 2 simultaneously first, and finally bonding the remaining color. This step-by-step bonding logic allows for setting differentiated bonding temperature and pressure parameters for Micro LED chips 2 with different material systems to optimize the connection quality of chips with different wavelengths.

[0052] This process is not limited to a combination of red, green, and blue chips. Depending on display performance requirements, the number of Micro LED chips 2 vertically bonded to the surface of IC chip 1 can be increased or decreased. When applied to monochrome displays, only a single color Micro LED chip 2 is bonded; when enhanced color gamut or brightness is required, four or more Micro LED chips 2 can be vertically stacked above the driving units on the surface of IC chip 1.

[0053] After thermosetting bonding, a cooling and hardening process is performed to stabilize the metallic phase at the bonding interface. Subsequently, the temporary support substrate on the back of the Micro LED chip 2 is removed using laser lift-off, chemical etching, or mechanical lift-off processes. Since the Micro LED chip 2 is firmly fixed to the surface of the IC chip 1 through the bonding interface, the removal of the support substrate does not compromise the stability of the vertically stacked structure. At this point, the light-emitting surface of the Micro LED chip 2 is completely exposed, and the IC chip 1 has substantially assumed the substrate support function for all subsequent process steps.

[0054] This bonding process ensures that the shear strength of the connection interface between IC chip 1 and Micro LED chip 2 meets semiconductor packaging standards, while also ensuring that the on-resistance in the vertical direction remains within a preset low range, providing structural support for subsequent pin bump fabrication or back-cutting.

[0055] See attached document Figure 1 The present invention provides a package structure for encapsulating LED and IC, the package structure including IC chip 1, Micro LED chip 2 vertically bonded to the surface of IC chip 1, and surface bumps 3 disposed on the front side of IC chip 1.

[0056] In the physical structure of this embodiment, the top surface of IC chip 1 is divided into a central core functional area and an edge lead-out area surrounding the core functional area. The core functional area is used to support and drive the Micro LED chip 2, and its surface is distributed with micron-sized bonding pads for electrical interconnection with the Micro LED chip 2. The edge lead-out area is located at the periphery of IC chip 1 and is used to prepare external connection terminals for leading out electrical signals. The Micro LED chip 2 is fixed to the core functional area of ​​IC chip 1 by a metal bonding process, and its physical projection falls entirely within the area of ​​IC chip 1.

[0057] Surface bumps 3 are located on the edge lead-out area of ​​the top layer of IC chip 1 and surround the Micro LED chip 2. The height of surface bumps 3 is designed to ensure that the position of their tops in the vertical direction does not physically obstruct the light emission angle of Micro LED chip 2. The driving circuit integrated inside IC chip 1 transmits electrical signals to the metal pads of the edge lead-out area through its top redistribution layer. Surface bumps 3 are directly grown or fixed on these metal pads, thereby leading the driving signal, power signal, or ground signal to the front side of the package.

[0058] Regarding the specific fabrication process of surface bump 3, depending on the specific requirements of the package for pin spacing and height, a solder balling process, a solder paste printing process, or an electroplating process for copper pillar fabrication is employed. In the solder balling process, high-precision solder balling equipment is used to place metal solder balls of a preset diameter onto the surface of the pads in the edge lead-out area. Reflow soldering then ensures a reliable metallurgical bond between the solder balls and the pads. In the solder paste printing process, a stencil with a specific array of openings is used to deposit solder paste containing metal particles onto the pads. After reflow soldering, conductive bumps with an arc-shaped surface are formed. In the electroplating process for copper pillar fabrication, a metal seed layer is first deposited on the surface of IC chip 1 and covered with photoresist. Openings are formed in the edge area through exposure and development. Electrochemical deposition is then used to grow copper pillars of a preset height within the openings, and a tin-lead or lead-free solder cap is fabricated on top of the copper pillar.

[0059] In this structural layout, the electrical connectors of the external system are directly connected to the surface bumps 3 located on the front side of the IC chip 1. Since the Micro LED chip 2 and the surface bumps 3 are both located on the same side surface of the IC chip 1, and both are directly supported by the IC chip 1, this packaging structure eliminates the need for an external ceramic or plastic substrate, which is essential in traditional packaging technologies. This integration method shortens the electrical path between the Micro LED chip 2 and the driving unit, reducing line impedance.

[0060] During the monomerization process of this packaging structure, the cutting path is located outside the surface bumps 3. Since the IC chip 1 simultaneously serves as both the circuit driver and the physical support, the final projected area of ​​the package is determined by the size of the IC chip 1. By vertically stacking the Micro LED chips 2 at the center of the IC chip 1 and compactly arranging the surface bumps 3 along the edge of the IC chip 1, complete display pixel unit packaging within a very small projected area is achieved, providing a physical basis for the fabrication of high-resolution and high-transmittance displays.

[0061] See attached document Figure 2 The present invention provides a package structure for encapsulating LED and IC. The package structure mainly consists of an IC chip 1, a Micro LED chip 2 vertically bonded to the surface of the IC chip 1, a vertical conductive post 4 penetrating the interior of the IC chip 1, and a back solder ball 5 disposed on the back side of the IC chip 1.

[0062] In this embodiment, the IC chip 1 integrates a through-silicon via (TSV) structure, namely vertical conductive pillars 4. The vertical conductive pillars 4 are arranged in an array within the IC chip 1, their spatial arrangement avoiding the drive circuit logic units of the core functional area of ​​the IC chip 1, and are physically connected to the top metal trace layer of the IC chip 1. The axis of the vertical conductive pillars 4 is perpendicular to the main plane of the IC chip 1, extending from the front to the back of the IC chip 1 and penetrating the entire silicon substrate.

[0063] Regarding the manufacturing mechanism of the vertical conductive pillar 4, this structure is fabricated using a through-silicon via (TSV) process. First, a TSV with a high aspect ratio is drilled from the front or back of the silicon substrate of the IC chip 1 using deep reactive ion etching (DRIE). The diameter and depth of the TSV are controlled according to the total thickness of the package and current carrying requirements, ensuring that the TSV completely penetrates the silicon substrate in the vertical direction. An insulating layer is deposited on the inner wall of the TSV to achieve electrical isolation between the conductive material and the silicon substrate. Subsequently, a diffusion barrier layer and a metal seed layer are prepared by physical vapor deposition (PVD). Finally, copper is filled into the TSV using electroplating to form a solid vertical conductive pillar 4.

[0064] In terms of electrical connection logic, the electrodes of Micro LED chip 2 are connected to the driving circuit inside IC chip 1 through the solder layer on the surface of IC chip 1. The driving signal, as well as the externally supplied power and ground signal, are gathered at the top of the vertical conductive post 4 through the redistribution layer on the top layer of IC chip 1. The vertical conductive post 4 acts as a vertically downward conductive path, transmitting electrical signals from the front side of IC chip 1 to the back side of IC chip 1.

[0065] On the back of the IC chip 1, there are back metal pads corresponding to the bottom ends of the vertical conductive pillars 4. Back solder balls 5 are fixed to these back metal pads using a ball-mounting process or electroplating. The center point of the back solder balls 5 coincides with the axis of the vertical conductive pillars 4 in the vertical projection direction or is electrically interconnected through a back wiring layer. With this configuration, the drive signals required by the Micro LED chip 2 on the front of the package are pinned through the vertical conductive pillars 4 inside the IC chip 1 and ultimately converge to the back solder balls 5 on the back of the package.

[0066] This TSV vertical through-package structure enables vertical signal transmission within the package. Because the pins, i.e., the back solder balls 5, are located on the back of the IC chip 1, the projected area of ​​the package in the horizontal direction can be compressed to only slightly larger than or equal to the physical size of the IC chip 1. Simultaneously, the vertical conductive pillars 4 provide extremely short vertical interconnect paths, reducing parasitic capacitance and inductance effects during signal transmission. In high-density pixel integration, this back-pin design allows the package to be directly mounted on the display driver substrate using surface mounting, without occupying any light-emitting space on the front of the IC chip 1.

[0067] See attached document Figure 3 and Figure 4 The present invention provides a packaging structure for LED and IC co-encapsulation. In this embodiment, by thinning and edge forming the IC chip 1, an electrical signal transmission path is established on the sidewall of the IC chip 1 using a metal cladding layer 7.

[0068] In the manufacturing process of this embodiment, the IC chip 1 wafer with the bonded Micro LED chip 2 is first thinned by back-side grinding. Excess silicon substrate material on the back side of the IC chip 1 is removed using mechanical grinding equipment, reducing the thickness of the IC chip 1 to a preset process dimension. Subsequently, a back-cutting process is performed in the dicing path area on the back side of the IC chip 1 to form a back-cutting position 6. The back-cutting position 6 is presented as a slot with a specific ramp angle, which extends from the side of the IC chip 1 to the metal pad area on the top layer of the IC chip 1. The ramp angle of the back-cutting position 6 relative to the horizontal plane of the IC chip 1 is controlled between 30 degrees and 60 degrees.

[0069] The slope design of the back cut 6 is intended to provide a continuous physical support surface for the subsequent metallization layer. If the back cut 6 is a 90-degree vertical section, there is a risk of breakage due to insufficient step coverage during the subsequent thin film deposition process. By setting the slope angle within the above range, it is possible to ensure that the metal cladding layer 7 maintains uniformity and continuity in thickness at the front mating point, side wall slope, and back mating point of the IC chip 1.

[0070] After forming the back cut position 6, a metal cladding layer 7 is deposited on the back side and sidewall bevels of the IC chip 1 using a physical vapor deposition process. The deposition process employs magnetron sputtering or electroplating, and the selected metal materials include titanium, copper, nickel, gold, or combinations thereof. The metal cladding layer 7 covers the entire bevel of the back cut position 6 and achieves physical contact with the leads of the top-layer circuitry of the IC chip 1. To improve the insulation reliability between the metal cladding layer 7 and the silicon substrate, a silicon dioxide or silicon nitride insulating dielectric layer needs to be pre-grown on the surface of the back cut position 6 before depositing the metal.

[0071] In terms of electrical logic, the drive signals and power signals on the front side of IC chip 1 are guided to the edge area of ​​IC chip 1 through the top layer wiring and connected to the top of the metal cladding layer 7. The metal cladding layer 7 runs along the bevel of the back cut 6 to the back side of IC chip 1 and forms pin pads of a specific shape on the back side of IC chip 1. This bypass wiring method realizes the through-hole-free transmission of signals from the front to the back side of IC chip 1.

[0072] Finally, back solder balls 5 are fabricated at the ends of the metal cladding layer 7 on the back side of the IC chip 1. The back solder balls 5 serve as the final electrical connection interface between the package and the external system. In this structure, the electrical connection signals of the package are transferred from the front light-emitting area to the back mounting area through the side metal cladding layer 7. By eliminating the high aspect ratio aperture etching and filling steps in the TSV process, this embodiment reduces the process difficulty. At the same time, since the metal cladding layer 7 is distributed on the side edge of the IC chip 1, the wiring density in the central area of ​​the IC chip 1 is further increased.

[0073] Since the forming of the back cut position 6 and the deposition of the metal cladding layer 7 are both completed at the wafer-level scale, the metallization layer on the side of the package structure constitutes the lateral pins of the package after the monolithic dicing. This construction method enables the package to maintain a vertically stacked miniaturized size while possessing good heat dissipation path and stable signal transmission performance.

[0074] See attached document Figures 1 to 4 This invention provides a packaging structure for LED and IC co-encapsulation. After completing the vertical bonding of IC chip 1 and Micro LED chip 2 and the preparation of related pin bumps or conductive structures, the entire wafer needs to be divided into multiple independent packaging units through a single-unit dicing process.

[0075] The wafer dicing process is performed on a fully automated precision dicing machine, with the dicing path following dicing tracks pre-defined in the wafer map. The dicing tracks are distributed in a crisscrossing grid pattern on the wafer surface, with the geometric center lines of the tracks precisely located at the physical boundary between two adjacent packaging units. Before the dicing operation, the wafer containing IC chip 1 is attached to an adhesive dicing film, and a frame is used to fix the film in place to ensure that the relative positions of IC chip 1 and Micro LED chip 2 remain fixed during the dicing process.

[0076] For a package structure with surface bumps 3, the cutting path is arranged outside the edge lead-out area on the surface of the IC chip 1. A preset clearance distance is maintained between the physical movement trajectory of the cutting tool and the surface bumps 3 to ensure that mechanical vibrations and shearing forces generated during the cutting process do not act on the surface bumps 3. This clearance distance takes into account the tool wobble tolerance and the edge chipping tolerance of the IC chip 1, thereby ensuring that the surface bumps 3 maintain their complete physical shape and electrical connection performance at the edge of the cut package unit.

[0077] For packaging structures involving vertical conductive pillars 4 and back solder balls 5, the dicing process directly acts on the silicon substrate material of the IC chip 1. The high-speed rotating blade of the dicing tool moves along the center of the dicing path, dividing the IC chip 1 into rectangular bodies of a preset size. During this process, the dicing path must maintain an electrical isolation distance from the vertical conductive pillars 4 inside the IC chip 1 to prevent dicing damage to the insulating coating layer of the vertical conductive pillars 4.

[0078] For a package structure including a back-cut section 6 and a metal cladding layer 7, the monomer cutting is performed along the centerline of the valley of the back-cut section 6. Since the back-cut section 6 has already formed a V-shaped or U-shaped thinning groove through machining or chemical treatment in previous processes, the final monomer cutting only needs to penetrate the remaining extremely thin silicon substrate. When the cutting tool passes through the back-cut section 6, it cuts the metal cladding layer 7 as well, exposing the cross-section of the metal cladding layer 7 on the sidewall of the package monomer, forming laterally arranged conductive terminals.

[0079] During the dicing process, the spray system continuously sprays deionized cooling water onto the processing areas of IC chip 1 and Micro LED chip 2. The deionized water serves several purposes: cooling the dicing tool to extend its lifespan, reducing the width of the heat-affected zone in the processing area, and continuously flushing away silicon chips and metal residue generated during dicing. After rinsing, the wafers undergo high-speed airflow drying to prevent residual moisture from causing oxidation of the metal structure.

[0080] After cutting, the individual packaged units remain on the cutting film. An expansion process is used to increase the spacing between the packaged units, facilitating subsequent visual inspection of the Micro LED chip 2's luminous uniformity and the IC chip 1's cutting quality. Qualified packaged units are removed from the cutting film using a suction nozzle and transferred to the testing or packaging process.

[0081] See attached document Figures 1 to 4 The present invention provides a package structure for LED and IC co-encapsulation. Before or after the individual chip cutting is completed, the package consisting of IC chip 1 and Micro LED chip 2 needs to be tested for electrical performance and optical performance to verify the driving capability of IC chip 1 to Micro LED chip 2 and the overall optical quality.

[0082] The electrical performance testing process is performed using an automated testing system. The test head establishes electrical contact with the pin terminals on the IC chip 1. In Embodiment 1, the test head contacts the surface bumps 3 located on the edge of the front side of the IC chip 1. In Embodiments 2 and 3, the test head contacts the back solder balls 5 located on the back side of the IC chip 1. The automated testing system inputs specific logic control signals to the IC chip 1 and determines the integrity of its internal driving circuit by monitoring the electrical signals fed back by the IC chip 1. Simultaneously, the testing system detects the voltage drop during the transmission of the driving current to the Micro LED chip 2, thereby evaluating the contact resistance of the bonding interface between the IC chip 1 and the Micro LED chip 2.

[0083] Optical performance testing was conducted with the encapsulated structure in an active state. The testing system sent a lighting command to IC chip 1 via pin terminals, causing Micro LED chip 2 to emit visible light of a preset wavelength. A high-precision photoelectric sensor acquired the emission parameters of Micro LED chip 2, including center wavelength, luminous intensity, and spectral half-width. Since Micro LED chip 2 is vertically stacked above IC chip 1 and the light emission path is unobstructed by support walls or leads, the testing system recorded its light extraction efficiency data.

[0084] During testing, a uniformity evaluation formula was used to quantitatively assess the brightness consistency of multiple packaged cells on the wafer. Brightness uniformity. The calculation method is as follows:

[0085] ;

[0086] In the above formula, Represents brightness uniformity. This represents the highest measured brightness value output by Micro LED chip 2 in this batch of test samples. This represents the lowest measured brightness value output by Micro LED chip 2 in this batch of test samples. The value is calculated using this formula. The value serves as a core indicator for sorting and packaging individual unit grades.

[0087] The test results are compared in real time with a pre-set performance database. The testing system sorts each sealing unit based on the deviation range of electrical and optical parameters. The sorting criteria cover the wavelength consistency deviation range and the brightness level. Areas with values ​​below a preset threshold are automatically marked as unqualified units by the system. For qualified packaged units, after thinning and cutting, they are precisely picked up using vacuum nozzles and classified and taped according to brightness and wavelength levels.

[0088] After sorting, the packaged units are placed in anti-static packaging material for packaging. This comprehensive testing and sorting process for the vertically packaged IC chip 1 and Micro LED chip 2 ensures that each packaged unit has consistent photoelectric response characteristics under the same driving signal in subsequent applications, providing data support for achieving color uniformity in high-resolution transparent displays.

[0089] Working principle: IC chip 1 receives logic control signals and power energy from the external system through its internally integrated complementary metal-oxide-semiconductor (CMOS) driving circuit and converts them into precise pixel driving current. Since Micro LED chip 2 is vertically stacked on top of the front side of IC chip 1 via a metal bonding layer, the driving current is directly injected into the electrodes of Micro LED chip 2 through the metal solder joints on the top layer of IC chip 1. This vertical interconnection mode establishes the shortest electrical transmission path, effectively reducing parasitic resistance and inductance during signal transmission and improving the response speed of the display unit.

[0090] In terms of physical layout and light path extraction, the packaging structure utilizes high vertical integration to achieve size miniaturization. The physical projection of the Micro LED chip 2 is confined to the projection range of the IC chip 1, so that the area occupied by the package unit on the horizontal plane depends only on the size of the IC chip 1. When the Micro LED chip 2 is excited by current to emit light, the light radiates outwards away from the IC chip 1. Since the IC chip 1 and the conductive mechanism are located on the light-emitting side or below the Micro LED chip 2, and there is no support sidewall as in traditional packaging, the light is not physically blocked in the propagation path, thus achieving a high light extraction rate and a uniform viewing angle distribution.

[0091] During signal extraction and external interconnection, the package structure adapts to different application scenarios through various conductive mechanisms. Electrical signals from external systems enter the IC chip 1 through surface bumps 3, vertical conductive pillars 4, or the metal cladding layer 7. In back-side lead-out mode, the vertical conductive pillars 4 or the metal cladding layer 7 guide the signal from the front of the IC chip 1 to the back solder balls 5, achieving vertical signal transmission across layers. This mechanism ensures that the IC chip 1, while handling drive logic processing, can also act as an interposer, converting complex micron-level pixel electrodes into standardized package pins, ultimately completing the full energy and signal transmission from the system end to the display end.

Claims

1. A packaging structure for co-encapsulating LED and IC, characterized in that, Includes an IC chip (1), on the top side of which a Micro LED chip (2) is mounted. The IC chip (1) has an integrated driving circuit for controlling the light-emitting unit. The top side of the IC chip (1) has metal solder joints that are compatible with the electrodes of the Micro LED chip (2). The IC chip (1) and the Micro LED chip (2) form a three-dimensional stacked integrated structure through a metal bonding layer. The physical projection area of ​​the Micro LED chip (2) is located within the physical projection range of the IC chip (1); The IC chip (1) is provided with a conductive mechanism for leading out electrical signals. The conductive mechanism includes a back solder ball (5) disposed on the back side of the IC chip (1), a slope-shaped back cut (6) formed on the edge of the IC chip (1) and extending from the back side to the top side, and a metal cladding layer (7) covering the outer surface of the back cut (6). The metal cladding layer (7) connects the front circuit of the IC chip (1) to the back solder ball (5) to form an electrical signal lead-out path from the front of the IC chip (1) through the side of the back cut position (6) to the back of the IC chip (1).

2. The LED and IC co-encapsulation packaging structure according to claim 1, characterized in that, The Micro LED chip (2) includes a chip array consisting of red Micro LED chips, green Micro LED chips and blue Micro LED chips arranged at a preset pixel pitch. The chip array is fixed to the top side of the IC chip (1) by an integral wafer bonding process or a step-by-step sequential bonding process.

3. The LED and IC co-encapsulation packaging structure according to claim 1, characterized in that, The top surface of the IC chip (1) is divided into a core functional area at the center and an edge lead-out area located around the core functional area; The Micro LED chip (2) is fixed to the core functional area, and the edge lead-out area is provided with an edge lead-out end that is electrically connected to the front circuit of the IC chip (1). One end of the metal cladding layer (7) is electrically connected to the edge lead-out end.

4. The LED and IC co-encapsulation packaging structure according to claim 1, characterized in that, The back solder ball (5) is disposed on the back metal pad on the back of the IC chip (1), and the back metal pad is electrically connected to the metal cladding layer (7).

5. The LED and IC co-encapsulation packaging structure according to claim 1, characterized in that, The back cut (6) is a thinning groove provided on the edge of the IC chip (1). The angle between the inclined surface of the back cut (6) and the horizontal plane of the IC chip (1) is 30 degrees to 60 degrees, which is used to provide a physical support surface for the metal cladding layer (7).

6. The LED and IC co-encapsulation packaging structure according to claim 5, characterized in that, The metal cladding layer (7) is applied to the beveled surface of the back cut position (6) by physical vapor deposition or electroplating. An insulating dielectric layer is provided between the metal cladding layer (7) and the silicon substrate of the IC chip (1).

7. The LED and IC co-encapsulation packaging structure according to claim 1, characterized in that, The sidewall of the IC chip (1) is a single-piece cut surface; the single-piece cut surface is located at the center line of the back cut position (6) and exposes the cross-section of the metal cladding layer (7).

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