Semiconductor device and method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUBEI 3D SEMICON INTEGRATED INNOVATION CENT CO LTD
- Filing Date
- 2024-11-28
- Publication Date
- 2026-05-29
Smart Images
Figure CN122121550A_ABST
Abstract
Description
Technical Field
[0001] This application relates generally to the field of semiconductors, and more specifically to a semiconductor device and a method for forming the same. Background Technology
[0002] In hybrid chip-to-wafer (C2W) bonding, the metal layers (typically copper) of the chip and the carrier wafer are precisely aligned and directly pressed together to form direct electrical contacts. This method allows for solderless bonding, thereby reducing the thickness of the bonding layer, shortening the electrical path, and reducing parasitic effects. Furthermore, hybrid bonding technology can select chips of different sizes and types, as well as wafer-level chips, for bonding, showing great potential in 3D stacked memory and high-end logic applications, and is one of the most important ways to achieve heterogeneous integration such as silicon photonics.
[0003] A single chip can be formed by cutting a wafer, and how to reduce the deformation of the wafer is currently an extremely important technical problem. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor device and a method for forming the same, which aims to reduce the deformation of a first wafer.
[0005] To address the aforementioned problems, embodiments of this application provide a method for forming a semiconductor device, comprising:
[0006] A first wafer is formed, the first wafer including opposing first and second surfaces;
[0007] A first carrier wafer is provided, the first carrier wafer including opposing third and fourth surfaces;
[0008] A deformation-resistant layer and a first bonding layer located on the surface of the deformation-resistant layer are formed on the third surface;
[0009] The first surface of the first wafer is bonded to the first bonding layer.
[0010] In some embodiments, the method further includes: forming a second bonding layer on a first surface of the first wafer;
[0011] The step of bonding the first surface of the first wafer to the first bonding layer includes: bonding the first bonding layer and the second bonding layer using a melt bonding process.
[0012] In some embodiments, the method further includes: dicing the first wafer and the first carrier wafer after bonding, forming a plurality of target chips from the first wafer; forming a second wafer; bonding the second surfaces of the plurality of target chips to the second wafer respectively; and removing the first carrier wafer, the anti-deformation layer and the first bonding layer after bonding.
[0013] In some embodiments, the step of forming the first wafer includes: providing a first initial wafer, the first initial wafer including opposing first initial surfaces and second initial surfaces; thinning the first initial wafer on the first initial surfaces to form the first wafer including the first surface and the second surface.
[0014] In some embodiments, before thinning the first initial wafer, the step of forming the first wafer further includes: forming a third bonding layer on the second initial surface; providing a second carrier wafer, the second carrier wafer including opposing fifth and sixth surfaces; forming a fourth bonding layer on the fifth surface; bonding the third bonding layer to the fourth bonding layer; and thinning the first initial wafer on the first initial surface after bonding to form the first wafer including the first surface and the second surface.
[0015] In some embodiments, the step of bonding the third bonding layer to the fourth bonding layer includes: bonding the third bonding layer and the fourth bonding layer using a melt bonding process.
[0016] In some embodiments, the stiffness of the anti-deformation layer is greater than the stiffness of the first bonding layer.
[0017] In some embodiments, the thickness of the anti-deformation layer is greater than the thickness of the first bonding layer.
[0018] In some embodiments, the first carrier wafer includes a SiC substrate or <111> Silicon wafers with crystal orientation.
[0019] In some embodiments, after the step of bonding the first surface of the first wafer to the first bonding layer, the forming method further includes: removing the second carrier wafer and the fourth bonding layer; and forming a first bonding structure on the second surface of the first wafer.
[0020] In some embodiments, after forming the first bonding structure, the forming method further includes: forming a sacrificial layer on one side of the first bonding structure; providing a third carrier wafer; temporarily bonding the third carrier wafer to the sacrificial layer; after the temporary bonding, thinning the first carrier wafer on the fourth surface; and after thinning the first carrier wafer, debonding the third carrier wafer.
[0021] Accordingly, this application also provides a semiconductor device, including: a first wafer, including opposing first and second surfaces; a first carrier wafer bonded to the first wafer, including opposing third and fourth surfaces; a deformation-resistant layer located on the third surface; and a first bonding layer located on the surface of the deformation-resistant layer, wherein the first surface of the first wafer is bonded to the first bonding layer.
[0022] In some embodiments, the stiffness of the anti-deformation layer is greater than the stiffness of the first bonding layer.
[0023] In some embodiments, the thickness of the anti-deformation layer is greater than the thickness of the first bonding layer.
[0024] In the semiconductor device formation method provided in this application embodiment, bonding the first carrier wafer to the first wafer can reduce the deformation of the first wafer. Furthermore, before bonding the first wafer to the first carrier wafer via the first bonding layer, an anti-deformation layer is first formed on the first carrier wafer. After bonding, the anti-deformation layer can maintain the deformation of the first wafer, thereby improving the deformation resistance of the first wafer. Attached Figure Description
[0025] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0026] Figure 1 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application;
[0027] Figures 2-9 These are schematic diagrams illustrating the structure of a semiconductor device during its fabrication process, provided in some embodiments of this application.
[0028] Figure 10 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application;
[0029] Figures 11-18 This is a schematic diagram of the semiconductor device fabrication process provided in some embodiments of this application. Detailed Implementation
[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0031] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.
[0032] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.
[0033] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more second conductive layers and contact layers, as well as one or more dielectric layers.
[0034] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0035] In C2W hybrid bonding technology, target chips and wafer-level chips of different sizes and types can generally be selected for bonding. These target chips can be obtained by dicing target wafers. Before dicing, the target wafers need to undergo processes such as thinning and forming metal bonding structures. During the thinning or metal bonding structure formation process, the target wafers often need to be bonded to other carrier wafers first.
[0036] However, because the target wafer expands or shrinks after undergoing multi-layer wiring, this phenomenon becomes increasingly severe after the target wafer is thinned and diced into individual target chips. These deformations significantly reduce the C2W bonding accuracy and may even lead to abnormal electrical connections between the target chip and the wafer-level chip.
[0037] Based on the above, this application provides a method for forming a semiconductor device to reduce the deformation of a first wafer (i.e., the target wafer).
[0038] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for forming a semiconductor device according to some embodiments of this application. The method includes the following steps S1 to S4.
[0039] Step S1: Form a first wafer, the first wafer including opposing first and second surfaces.
[0040] Step S2: Provide a first carrier wafer, the first carrier wafer including opposing third and fourth surfaces.
[0041] Step S3: Form a deformation-resistant layer and a first bonding layer on the surface of the deformation-resistant layer on the third surface.
[0042] Step S4: Bond the first surface of the first wafer to the first bonding layer.
[0043] In the semiconductor device formation method provided in this application embodiment, bonding the first carrier wafer to the first wafer can reduce the deformation of the first wafer. Furthermore, before bonding the first wafer to the first carrier wafer via the first bonding layer, an anti-deformation layer is first formed on the first carrier wafer. After bonding, the anti-deformation layer can maintain the deformation of the first wafer, thereby improving the deformation resistance of the first wafer.
[0044] The method for forming this semiconductor device will be described in detail below with reference to the accompanying drawings.
[0045] Please refer to the following: Figures 2-9 , Figures 2-9 This is a schematic diagram of the semiconductor device provided in some embodiments of this application during its formation process. The method for forming this semiconductor device includes the following steps S1 to S4.
[0046] Step S1: Form a first wafer 10, the first wafer 10 including a first surface 101 and a second surface 102 opposite to each other.
[0047] In some embodiments, the specific process of step S1 can be found in [reference needed]. Figure 2 .
[0048] Please refer to Figure 2 A first substrate 11 is provided; a first device layer 12 is formed on the surface of the first substrate 11 and a first interconnect layer 13 is formed on the surface of the first device layer 12.
[0049] The lower surface of the first substrate 11 can be the first surface 101 of the first wafer 10, and the upper surface of the first interconnect layer 13 can be the second surface 102 of the first wafer 10.
[0050] The first substrate 11 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI).
[0051] The first device layer 12 may include a memory device, which can be of various types, such as phase-change memory devices, 3D NAND memory devices, etc. This application embodiment does not limit this.
[0052] The first interconnect layer 13 may include multiple wiring layers, specifically including an insulating layer and metal traces located in the insulating layer.
[0053] Please refer to Figure 3 The method for forming the semiconductor device further includes forming a second bonding layer 14 on the first surface 101 of the first wafer 10.
[0054] The second bonding layer 14 may include dielectric layers such as silicon oxide and silicon nitride, and the second bonding layer 14 can be formed by various deposition processes.
[0055] In other embodiments, please refer to the specific process of step S1. Figures 4-7 .
[0056] See Figure 4 A first initial wafer 10a is provided, the first initial wafer 10a including opposing first initial surface 101a and second initial surface 102a.
[0057] The first initial wafer 10a may include a first substrate 11, a first device layer 12, and a first interconnect layer 13 stacked together. The first interconnect layer 13 may include an insulating layer and multilayer wiring located within the insulating layer. The first device layer 12 may be various types of memory devices. Therefore, the bottom surface of the first substrate 11 is the first initial surface 101a of the first initial wafer 10a, which becomes the first surface 101 after thinning, while the top surface of the first interconnect layer 13 is the second initial surface 102a of the first initial wafer 10a, which is referred to as the second surface 102 after thinning.
[0058] See Figure 5 A third bonding layer 14a is formed on the second initial surface 102a.
[0059] The process for forming the third bonding layer 14a includes: 1) forming a first dielectric layer (not shown) on the first initial wafer 10a; 2) performing a chemical mechanical polishing process on the first dielectric layer; 3) after the chemical mechanical polishing process, forming a second dielectric layer (not shown) on the first dielectric layer, wherein the density of the second dielectric layer is greater than that of the first dielectric layer.
[0060] It should be noted that in some embodiments, the third bonding layer 14a may not include the second dielectric layer.
[0061] Specifically, the first dielectric layer can be formed by depositing an oxide (e.g., silicon oxide), and the second dielectric layer can also be formed by depositing an oxide (e.g., silicon oxide). However, the deposition rate of the second dielectric layer is lower than that of the first dielectric layer. Therefore, the density of the second dielectric layer is greater than that of the first dielectric layer. Consequently, the third bonding layer 14a can provide certain mechanical properties during the bonding process, increasing the bonding strength. Here, "density" refers to the volume percentage occupied by the atoms themselves in the unit cell. The higher the density, the more tightly the atoms are arranged. Therefore, the second dielectric layer can provide higher mechanical properties and wear resistance. The density of the first dielectric layer is lower than that of the second dielectric layer, which is beneficial for the chemical mechanical polishing process.
[0062] See Figure 6 A second carrier wafer 30 is provided, the second carrier wafer 30 including a fifth surface 301 and a sixth surface 302 opposite to each other; a fourth bonding layer 31 is formed on the fifth surface 301; and the third bonding layer 14a is bonded to the fourth bonding layer 31.
[0063] The second carrier wafer 30 can be a silicon wafer, and the fourth bonding layer 31 can be formed by a thermal oxidation process. Specifically, the third bonding layer 14a and the fourth bonding layer 31 can be bonded together using a fusion bonding process. It can be understood that the function of the second carrier wafer 30 is to support the first initial wafer 10a, with the first initial surface 101a facing upwards, thereby facilitating the thinning of the first initial surface 101a of the first wafer 10.
[0064] In one embodiment, the second carrier wafer 30 can also be temporarily bonded to the first initial wafer 10a using bonding adhesive.
[0065] Compared to the process of temporarily bonding the second carrier wafer 30 with bonding adhesive, the bonding process using the third bonding layer 14a and the fourth bonding layer 31 allows for adjustment of the bonding machine's process parameters (e.g., adjusting the deformation of the carrier disk when placing the first initial wafer 10a on the bonding cavity's carrier disk (e.g., an electrostatic chuck or electronic chuck)). This adjustment controls the deformation of the first initial wafer 10a. For example, if the first initial wafer 10a expands overall, the bonding machine's process parameters can be adjusted to shrink it; conversely, if the first initial wafer 10a shrinks overall, the bonding machine's process parameters can be adjusted to expand it. Therefore, this embodiment utilizes the bonding process during the thinning of the first initial wafer 10a to control the primary deformation of the first initial wafer 10a, thereby improving the deformation of the first wafer 10a.
[0066] See Figure 7 The first initial wafer 10a is thinned on the first initial surface 101a to form the first wafer 10 including the first surface 101 and the second surface 102. That is, the first initial surface 101a is thinned to form the first surface 101, and the second initial surface 102a becomes the second surface 102 of the first wafer 10.
[0067] The process of thinning the first initial wafer 10a on the first initial surface 101a after bonding may specifically include: removing part or all of the first substrate 11, and thinning the first initial wafer 10a to a target thickness, such as 1 μm to 50 μm. Specifically, mechanical polishing, chemical mechanical polishing, wet etching, dry etching, and other processes may be used.
[0068] In some embodiments, the step of forming the first wafer 10 may include: providing a plurality of sub-wafers (not shown); and stacking the plurality of sub-wafers to form the first wafer 10. Thus, the lower surface of the bottom sub-wafer is the first surface 101, and the upper surface of the top sub-wafer is the second surface 102.
[0069] In a specific example, two adjacent sub-wafers can be stacked in a manner where the front and back sides are bonded together, wherein the front side can be the surface with an interconnect layer, and the back side is the surface opposite to the front side.
[0070] It should be noted that the bottom sub-wafer can be an unthinned wafer, while the other sub-wafers are thinned wafers. Since the first wafer 10 is a stack of multiple sub-wafers, the first wafer 10 is more prone to deformation. Therefore, the deformation of the first wafer 10 can be effectively reduced through the subsequent bonding process of the first wafer 10 (steps S2 to S4).
[0071] Step S2: Provide a first carrier wafer 20, the first carrier wafer 20 including opposing third surface 201 and fourth surface 202. See details. Figure 8 .
[0072] In some embodiments, the first carrier wafer 20 may be a SiC substrate or <111> For silicon wafers with crystal orientation, because both materials have a large Young's modulus, they can help to improve the warpage of the first wafer 10 to a certain extent.
[0073] In some embodiments, the thickness of the first carrier wafer 20 can be selected according to actual needs. Selecting a thicker first carrier wafer 20 can also improve the warpage of the first wafer 10 to a certain extent. Furthermore, the first carrier wafer 20 is easy to remove in subsequent processes.
[0074] Step S3: A deformation-resistant layer 21 and a first bonding layer 22 located on the surface of the deformation-resistant layer 21 are formed on the third surface 201. See details. Figure 8 .
[0075] The deformation-resistant layer 21 and the first bonding layer 22 can be formed by a deposition process. The deposition process can be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), such as thermal oxidation, evaporation, sputtering, and other methods.
[0076] It is understood that the anti-deformation layer 21 is not used to reduce the deformation of the first wafer 10, but to maintain the deformation of the first wafer 10 after the deformation of the first wafer 10 has been reduced by the bonding process. In particular, it can effectively maintain the deformation of the first wafer 10 after the first carrier wafer 20 is thinned (which will introduce warpage deformation) (the process of thinning the first carrier wafer 20 is described in the following embodiment).
[0077] In some embodiments, the stiffness of the anti-deformation layer 21 is greater than that of the first bonding layer 22. The greater the stiffness, the greater the force required to resist deformation and the stronger the anti-deformation ability. Therefore, in this embodiment, the addition of the anti-deformation layer 21 can effectively maintain the reduced deformation of the first wafer 10 in subsequent processes, that is, improve the warpage deformation of the first wafer 10.
[0078] For a specific example, the material of the anti-deformation layer 21 includes at least one of Ti, TiN, Ta, TaN, SiCN, and SiC. The material of the first bonding layer 22 may include at least one of oxides and nitrides.
[0079] In some embodiments, the material of the deformation-resistant layer 21 further includes SiN.
[0080] In some embodiments, a buffer layer may be added between the substrate 20 and the anti-deformation layer 21 to increase adhesion.
[0081] In some embodiments, the thickness of the first bonding layer 22 can be greater than 10 nm and less than 100 nm, and the thickness of the anti-deformation layer 21 can be greater than 10 nm and less than 10000 nm.
[0082] In some embodiments, the thickness of the anti-deformation layer 21 is greater than the thickness of the first bonding layer 22. The thickness of the first bonding layer 22 needs to be within a preset range to ensure its bonding effect. The anti-deformation layer 21 is relatively larger than the thickness of the first bonding layer 22, so the anti-deformation layer 21 can provide greater anti-deformation capability.
[0083] Step S4: Bond the first surface 101 of the first wafer 10 to the first bonding layer 22. See details... Figures 8-9 .
[0084] See Figure 8 A second bonding layer 14b can be formed first on the first surface 101.
[0085] See Figure 9 In some embodiments, the second bonding layer 14b and the first bonding layer 22 can be bonded together by a melt bonding process. The deformation degree of the first wafer 10 can be further controlled by adjusting the bonding process parameters.
[0086] In other embodiments, the second bonding layer 14b and the first bonding layer 22 can also be bonded using a hybrid bonding process, and the deformation degree of the first wafer 10 can be controlled by adjusting the bonding process parameters. The difference is that bonding metal also needs to be formed on the bonding surfaces of the second bonding layer 14b and the first bonding layer 22.
[0087] For a specific example, when the first wafer 10 expands as a whole, the process parameters of the bonding machine can be adjusted to shrink the first wafer 10 as a whole; when the first wafer 10 shrinks as a whole, the process parameters of the bonding machine can be adjusted to expand the first wafer 10 as a whole.
[0088] Please see Figure 10 , Figure 10 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. Please refer to... Figures 11-18 , Figures 11-18 This is a schematic diagram of the semiconductor device fabrication process provided in some embodiments of this application. The formation method in this embodiment includes steps S1 to S4 of the above embodiments, so they will not be described again in this embodiment. The focus is on describing steps S5 to S10.
[0089] Step S5: Remove the second carrier wafer 30 and the fourth bonding layer 31. See details... Figure 11 .
[0090] For specific examples, you can first... Figure 9 The structure shown is flipped so that the first carrier wafer 20 is below and the second carrier wafer 30 is above. After step S4, the second carrier wafer 30 can be removed by chemical mechanical polishing, polishing, or etching, and the fourth bonding layer 31 can be removed by chemical mechanical polishing or etching to expose the third bonding layer 14a.
[0091] Step S6: A first bonding structure 15 is formed on the second surface 102 of the first wafer 10. See details... Figure 12 .
[0092] In some embodiments, since the third bonding layer 14a may include a first dielectric layer and a second dielectric layer (both of which are insulating materials), the third bonding layer 14a may be retained.
[0093] The method for forming the first bonding structure may include: forming a first dielectric film (not shown) for hybrid bonding on the third bonding layer 14a; forming a second dielectric film (not shown) to protect the first dielectric film on the first dielectric film; then forming the first bonding structure 15 on the first dielectric film; and forming vias connecting the first bonding structure 15 and the first interconnect layer 13 within the third bonding layer 14a and the first dielectric film. The second dielectric film can be removed during the formation of the first bonding structure 15, such as by etching or chemical mechanical polishing. Therefore, the third bonding layer 14a not only plays a bonding role in the above process but can also be used to form the first bonding structure 15, thus omitting the process of removing the third bonding layer 14a.
[0094] In some other embodiments, the third bonding layer 14a may be removed before the first bonding structure 15 is formed.
[0095] Specifically, the third bonding layer 14a can be etched to form a via, then a metal layer can be deposited and patterned to form a first bonding structure 15. Afterwards, an insulating layer covering the first bonding structure 15 can be formed, and a polishing process can be performed to expose the first bonding structure 15. The material of the first bonding structure 15 may include copper.
[0096] Step S7: After bonding, the first wafer 10 and the first carrier wafer 20 are diced, and the first wafer 10 is used to form multiple target chips 10A. See details... Figures 13-17 .
[0097] In some embodiments, see Figures 13-16 Before dicing, the first carrier wafer 20 can be thinned.
[0098] For specific examples, see [link / reference]. Figure 13 A sacrificial layer 16 is formed on one side of the first bonding structure 15. The material of the third carrier wafer 40 may include silicon, and the sacrificial layer 16 may be an insulating material. The sacrificial layer 16 can protect the first bonding structure 15 during the temporary bonding process.
[0099] See Figure 14 A third carrier wafer 40 is provided; the third carrier wafer 40 is temporarily bonded to the sacrificial layer 16.
[0100] The temporary bonding process can be specifically described as follows: bonding adhesive is formed on one side of the third carrier wafer 40 and one side of the sacrificial layer 16, respectively. Then, the bonding adhesive on one side of the third carrier wafer 40 is bonded to the bonding adhesive on one side of the sacrificial layer 16, forming bonding adhesive 17. The purpose of temporary bonding is to thin the first carrier wafer 20, thereby enabling the first carrier wafer 20 to reach the target thickness (e.g., 10μm to 300μm), and thinning the first carrier wafer 20 facilitates the subsequent dicing process of the first carrier wafer 20 and the first wafer 10. The thinned first carrier wafer 20 becomes the first carrier wafer 20A.
[0101] See Figure 15 After the temporary bonding, the first carrier wafer 20 is thinned on the fourth surface 202.
[0102] See Figure 16 After thinning the first carrier wafer 20, the third carrier wafer 40 is debonded.
[0103] The specific process for debonding can be: Figure 15 The structure shown is flipped and placed on a frame. The third carrier wafer 40 and the bonding adhesive 17 are removed to expose the sacrificial layer 16. The structure can then be cleaned.
[0104] It should be noted that after debonding, the overall structure is a thin sheet. Since the anti-deformation layer 21 is still present between the first carrier wafer 20A and the first wafer 10, forming a sandwich structure, it can still maintain the deformation degree of the first wafer 10 and maintain the warpage value, so that warping will not occur due to the overall structure being too thin.
[0105] See Figure 17 The specific process of step S7 can be: cutting the thinned first carrier wafer 20A and the first wafer 10 from one side of the first carrier wafer 20A to divide the first wafer 10 into multiple target chips 10A.
[0106] Step S8: Form the second wafer 50. See details. Figure 17 .
[0107] In some embodiments, the specific process of step S8 may include: 1) providing a second substrate; 2) forming a second device layer on the surface of the second substrate; 3) forming a second interconnect layer (not shown) on the surface of the second device layer. 。 The second device layer in the second wafer 50 may include logic circuits, that is, the second wafer 50 may be a logic wafer.
[0108] Step S9: Bond the second surfaces 102 of the plurality of target chips 10A to the second wafer 50 respectively. See details. Figure 17 .
[0109] It should be noted that the second surface 102 of the target chip 10A corresponds to the second surface 102 of the first wafer 10, that is, the second surface 102 of the target chip 10A and the second surface 102 of the first wafer 10 are the same surface. Before bonding, a target chip 10A of suitable size and good quality can be selected from the multiple target chips 10A obtained by dicing, and then the selected target chips 10A are bonded to the second wafer respectively.
[0110] In some embodiments, the specific process of step S9 can be: 1) forming a second bonding structure 51 on one side of the second wafer 50, the second bonding structure 51 being formed on the surface of the second interconnect layer; 2) removing the sacrificial layer 16 and performing a cleaning process; 3) activating the target chip 10A; 4) performing a mixed bonding of the first bonding structure 15 and the second bonding structure 51, thereby achieving an electrical connection between the second wafer 50 and the target chip 10A. Since the dicing process of step S7 is performed first, and then the sacrificial layer 16 is removed, the sacrificial layer 16 can protect the first wafer 10 during the dicing process.
[0111] Since the anti-deformation layer 21 is always present between the first carrier wafer 20A and the first wafer 10 during the dicing process, the deformation degree of the first wafer 10 can still be maintained, thereby reducing the deformation degree of the target chip 10A.
[0112] Step S10: After bonding, remove the first carrier wafer 20A, the anti-deformation layer 21, and the first bonding layer 22. See details. Figure 18 .
[0113] Specifically, mechanical polishing, chemical mechanical polishing, and etching processes (including dry etching and wet etching) can be used to remove the first carrier wafer 20A, the anti-deformation layer 21, and the first bonding layer 22.
[0114] In some embodiments, the second bonding layer 14b is removed after bonding.
[0115] like Figure 18 As shown, the method for forming this semiconductor device may further include: filling an insulating layer 10B between two adjacent target chips 10A; and planarizing the first surface 101 of the target chip 10A and the insulating layer 10B. Subsequent processes such as through-silicon vias (TSVs) can then be performed to achieve connections between target chips 10A and between target chips 10A and the second wafer 50.
[0116] In some embodiments, an insulating layer 10B may be filled between two adjacent target chips 10A before step S10 is performed.
[0117] This application also provides a semiconductor device, which can be referred to in the embodiments. Figure 16 The semiconductor device includes: a first wafer 10, including a first surface 101 and a second surface 102 opposite to each other; a first carrier wafer 20A bonded to the first wafer 10, including a third surface 201 and a fourth surface 202 opposite to each other; a deformation-resistant layer 21 located on the third surface 201; and a first bonding layer 22 located on the surface of the deformation-resistant layer 21, wherein the first surface 101 of the first wafer 10 is bonded to the first bonding layer 22.
[0118] In this embodiment of the application, the first carrier wafer 20A is bonded to the first wafer 10 through the first bonding layer 22, which can reduce the deformation of the first wafer 10. The anti-deformation layer 21 forms a sandwich structure between the first carrier wafer 20A and the first wafer 10, which can maintain the reduced deformation of the first wafer 10 in subsequent processes.
[0119] In some embodiments, the stiffness of the anti-deformation layer 21 is greater than the stiffness of the first bonding layer 22.
[0120] In some embodiments, the thickness of the anti-deformation layer 21 is greater than the thickness of the first bonding layer 22.
[0121] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A first wafer is formed, the first wafer including opposing first and second surfaces; A first carrier wafer is provided, the first carrier wafer including opposing third and fourth surfaces; A deformation-resistant layer and a first bonding layer located on the surface of the deformation-resistant layer are formed on the third surface; The first surface of the first wafer is bonded to the first bonding layer.
2. The method for forming a semiconductor device according to claim 1, characterized in that, Also includes: A second bonding layer is formed on the first surface of the first wafer; The step of bonding the first surface of the first wafer to the first bonding layer includes: The first bonding layer and the second bonding layer are bonded using a melt bonding process.
3. The method for forming a semiconductor device according to claim 1, characterized in that, Also includes: After bonding, the first wafer and the first carrier wafer are diced, and the first wafer is used to form multiple target chips. Forming a second wafer; The second surfaces of the plurality of target chips are respectively bonded to the second wafer; After bonding, the first carrier wafer, the anti-deformation layer, and the first bonding layer are removed.
4. The method for forming a semiconductor device according to claim 1, characterized in that, The steps for forming the first wafer include: A first initial wafer is provided, the first initial wafer including opposing first initial surfaces and second initial surfaces; The first initial wafer is thinned on the first initial surface to form the first wafer including the first surface and the second surface.
5. The method for forming a semiconductor device according to claim 4, characterized in that, The step of forming the first wafer before thinning the first initial wafer further includes: A third bonding layer is formed on the second initial surface; A second carrier wafer is provided, the second carrier wafer including opposing fifth and sixth surfaces; A fourth bonding layer is formed on the fifth surface; The third bonding layer is bonded to the fourth bonding layer.
6. The method for forming a semiconductor device according to claim 5, characterized in that, The step of bonding the third bonding layer to the fourth bonding layer includes: The third bonding layer and the fourth bonding layer are bonded using a melt bonding process.
7. The method for forming a semiconductor device according to claim 1, characterized in that, The stiffness of the deformation-resistant layer is greater than that of the first bonding layer.
8. The method for forming a semiconductor device according to claim 1, characterized in that, The thickness of the anti-deformation layer is greater than the thickness of the first bonding layer.
9. The method for forming a semiconductor device according to claim 1, characterized in that, The first carrier wafer includes a SiC substrate or <111> Silicon wafers with crystal orientation.
10. The method for forming a semiconductor device according to claim 5, characterized in that, After the step of bonding the first surface of the first wafer to the first bonding layer, the formation method further includes: Remove the second carrier wafer and the fourth bonding layer; A first bonding structure is formed on the second surface of the first wafer.
11. The method for forming a semiconductor device according to claim 10, characterized in that, After forming the first bonding structure, the forming method further includes: A sacrificial layer is formed on one side of the first bonding structure; Provide a third carrier wafer; The third carrier wafer is temporarily bonded to the sacrificial layer; After the temporary bonding, the first carrier wafer is thinned on the fourth surface; After thinning the first carrier wafer, the third carrier wafer is debonded.
12. A semiconductor device, characterized in that, include: The first wafer includes opposing first and second surfaces; The first carrier wafer bonded to the first wafer includes opposing third and fourth surfaces; The deformation-resistant layer is located on the third surface; The first bonding layer is located on the surface of the anti-deformation layer, and the first surface of the first wafer is bonded to the first bonding layer.
13. The semiconductor device according to claim 12, characterized in that, The stiffness of the deformation-resistant layer is greater than that of the first bonding layer.
14. The semiconductor device according to claim 12, characterized in that, The thickness of the anti-deformation layer is greater than the thickness of the first bonding layer.