Method for improving the nanotopography of the back surface of a heavily doped back-encapsulated wafer

Abstract

The application discloses a method for improving the nanotopography of the back surface of a heavy-doped back-sealed wafer, wherein the back surface of the wafer has a back-sealing structure, and the back-sealing structure at least comprises a polysilicon back seal; the polysilicon back seal is prepared by the following method: S1. first growing a first layer of polysilicon film on the surface of a wafer which has not been back-sealed or has been back-sealed by other back-sealing structures at 600-670 DEG C; S2. then rotating the wafer horizontally, and growing a second layer of polysilicon film at 600-670 DEG C; the horizontal rotation angle is > 30 DEG; S3. removing the first layer of polysilicon film and the second layer of polysilicon film on the front surface of the wafer. By adopting the method of multiple growth combined with rotating the wafer, the deposition direction of the polysilicon back seal can be improved at a limited temperature, so that the nanotopography of the back surface of the silicon wafer is effectively improved, and the demand of advanced semiconductor manufacturing is met.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for improving the nano-morphology of the back side of a heavily doped back-sealed wafer. Background Technology

[0002] The flatness of silicon wafers can be classified according to their spatial wavelength into geometry (geometric parameters, spatial wavelengths above 10nm, referring to parameters such as LTV, TTV, TIR, Warp, SFQR, SBIR, etc.), nanotopography (spatial wavelengths of about 0.2~10nm, referring to NT, nano-topography), and roughness (spatial wavelengths below 0.1nm, referring to roughness).

[0003] Although both NT (nanotope) and Roughness are short-wavelength parameters, there is no simple positive or negative correlation between nanotope and roughness.

[0004] Heavily doped wafers typically require back sealing to suppress self-doping or gettering. The deposition of the back sealing film can negatively impact the nanostructure of the back side of the silicon wafer.

[0005] Strict requirements for the nano-topography of the back side of silicon wafers are fundamental to the successful implementation of advanced lithography technologies. The main objectives are: 1. To ensure optimal thermal contact and uniformity between the wafer and the lithography machine e-Chuck, avoiding thermal expansion and deformation caused by localized temperature unevenness, thereby guaranteeing overlay and focus accuracy; 2. To ensure absolute stability and repeatability of the wafer's adsorption on the e-Chuck, preventing micro-slippage; 3. To provide a good foundation for overall and local flatness, enabling the lithography machine's focusing and leveling systems to operate more effectively; 4. To meet the physical requirements for efficient and stable operation of the electrostatic chuck. As technology nodes advance, the requirements for front-side nano-topography (NT) will become increasingly stringent, and the impact of back-side NT on front-side NT will gradually become more apparent.

[0006] Therefore, silicon wafer manufacturers will need to invest significant resources in precisely controlling, measuring, and ensuring the nanoscale topography of the wafer's back side to meet the demands of advanced semiconductor manufacturing. It can be said that the "nanoscale topography" of the wafer's back side is one of the prerequisites for ensuring the "precision" of the front side. With the shift of specialty processes from 8-inch fabs to 12-inch fabs, 12-inch wafers also increasingly need to address and resolve the negative effects of the back-sealing structure. Currently, back-sealing structures such as POLY (polysilicon) + LTO (silicon dioxide), LTO + POLY, LTO + POLY + LTO, and POLY + LTO + POLY are commonly used to meet the different practical needs of fabs. These complex back-sealing structures not only cause deterioration of the bow / warp of the silicon wafer but also deterioration of the back-side NT (non-tert-facet). Many current studies focus on improving bow / warp deterioration or front-side NT, while this patent focuses on improving back-side NT. Summary of the Invention

[0007] The purpose of this invention is to provide a method for improving the nano-morphology of the back side of heavily doped back-sealed wafers in order to overcome the shortcomings of the prior art.

[0008] The objective of this invention is achieved through the following technical solution: A method for improving the nanostructure of the back side of a heavily doped back-sealed wafer, wherein the back side of the wafer has a back-sealing structure, the back-sealing structure comprising at least a polycrystalline silicon back-sealing; the polycrystalline silicon back-sealing is prepared by the following method: S1. First, a first polycrystalline silicon film layer is grown on the surface of a wafer that has not been back-sealed or has been back-sealed at 600~670℃; S2. Then, the wafer is rotated horizontally to grow a second polycrystalline silicon film at 600~670°C; the horizontal rotation angle is >30°. S3. Remove the first polysilicon film layer and the second polysilicon film layer on the front side of the wafer.

[0009] Preferably, the total thickness of the polycrystalline silicon back seal is 4000~14000 Å.

[0010] Preferably, the polycrystalline silicon back seal is deposited using a low-pressure chemical vapor deposition process; the pressure is 100~140 mtorr.

[0011] Preferably, the deposition temperature in steps S1 to S2 is 610 to 630°C.

[0012] Preferably, in step S2, the rotation base point is the wafer center, and the rotation direction is clockwise or counterclockwise.

[0013] Preferably, the back seal structure includes the polysilicon back seal and a silicon dioxide back seal located outside or inside the polysilicon back seal.

[0014] Preferably, the thickness of the silica back seal is 1000~4000 Å.

[0015] Preferably, the silica back seal is deposited using an atmospheric pressure chemical vapor deposition process.

[0016] Preferably, step S3 uses a chemical mechanical polishing process to remove the first polycrystalline silicon film layer and the second polycrystalline silicon film layer on the front side of the wafer.

[0017] Preferably, the horizontal rotation angle in step S2 is ≤180°.

[0018] This application employs a multi-stage growth method combined with a rotating wafer to deposit polysilicon back-side seals at a limited temperature, thereby effectively improving the nano-morphology of the back side of the silicon wafer and meeting the needs of advanced semiconductor manufacturing. Attached Figure Description

[0019] Figure 1 This is a scanning electron microscope image of a polycrystalline silicon back seal; Figure 2 This is a schematic diagram of the horizontal wafer rotation process in this application; Figure 3 This is the wafer back-sealing structure provided in Embodiment 1 of this application; Wherein, 1-wafer body; 2-first polycrystalline silicon film layer; 3-second polycrystalline silicon film layer; 4-silicon dioxide film layer. Detailed Implementation

[0020] This application provides a method for improving the nanostructure of the back side of a heavily doped back-sealed wafer. The back side of the wafer has a back-sealing structure, which includes at least a polycrystalline silicon back-sealing structure. The polycrystalline silicon back-sealing is prepared by the following method: S1. First, a first polycrystalline silicon film layer is grown on the surface of a wafer that has not been back-sealed or has been back-sealed at 600~670℃; S2. Then, the wafer is horizontally rotated to grow a second polycrystalline silicon film at 600~670℃; the horizontal rotation angle is >30°. S3. Remove the first and second polysilicon film layers on the front side of the wafer.

[0021] Preferably, the total thickness of the polysilicon back seal on the wafer is 4000~14000 Å, and each polysilicon film layer is evenly distributed.

[0022] Polycrystalline silicon back seal and silicon dioxide back seal are both common back seal structures.

[0023] Among them, silica thin film deposition is an amorphous material. After atoms or molecules reach the substrate surface, without specific lattice orientation constraints, they randomly "stick" to the surface depressions or protrusions, tending to fill low-lying areas. This random deposition method allows the entire surface to grow at a relatively uniform rate, thus forming a very smooth and flat film. It does not have crystal defects such as grain boundaries or dislocations that would disrupt the surface continuity. Therefore, silica back sealing generally does not have the problem of affecting nanoscale morphology.

[0024] Polycrystalline silicon is a silicon material composed of multiple grains with different orientations (such as...). Figure 1 As shown in the diagram, the nano-morphology of the deposited polycrystalline silicon back-sealing surface is definitely not as smooth and flat as that of a surface that has undergone chemical mechanical polishing. The gettering effect of polycrystalline silicon is precisely provided by the grain boundaries between the grains. Furthermore, the higher the temperature, the larger the deposited grain volume. If a thick polycrystalline silicon layer is grown in one step, it is easier to deposit larger grains, affecting the nano-morphology. In existing technologies, polycrystalline silicon back-sealing structures are mostly completed in a single deposition. Even if multiple depositions are performed to form multiple layers of polycrystalline silicon film, the wafer orientation remains unchanged during the deposition process, which can easily lead to larger polycrystalline silicon grains and affect the nano-morphology.

[0025] Since polycrystalline silicon is composed of grains with different orientations, the applicant considered whether multiple growth and rotation could be used to improve grain size. Experiments revealed that using multiple growth cycles and rotating wafers, deposited at a limited temperature, could improve the polycrystalline silicon deposition orientation, resulting in uniformly sized grains and thus improving the nanostructure.

[0026] This application applies to the production of silicon wafers containing polysilicon back seals. The back seal structure may also include other back seal films, such as silicon dioxide back seal films. The silicon dioxide back seal film may be located on the outside or inside of the polysilicon back seal.

[0027] Preferably, such as Figure 2 As shown, the wafer rotation base point is the wafer center (where the left and right diagrams are schematic diagrams of the wafer before and after horizontal rotation, respectively), and the rotation direction can be clockwise or counterclockwise.

[0028] Preferably, the polycrystalline silicon back seal is deposited using a low-pressure chemical vapor deposition (LPCVD) process. The low-pressure environment facilitates gas diffusion, resulting in a more uniform film layer and further improving the nanostructure of the polycrystalline silicon back seal. The pressure is further specified as 100–140 mtorr.

[0029] Preferably, the horizontal rotation angle in step S2 is ≤180°.

[0030] Preferably, in a preferred embodiment of this application, the back seal structure is as follows: Figure 3As shown, the wafer back seal includes a polysilicon back seal and a silicon dioxide back seal located on the outer surface of the polysilicon back seal. The polysilicon back seal is prepared using the method described above. Specifically, the wafer back seal structure, from the inside out, includes a first polysilicon film layer 2, a second polysilicon film layer 3, and a silicon dioxide film layer 4 deposited on the wafer body 1, i.e., a POLY+POLY+LTO structure. This structure can use the inner POLY layer to achieve the function of external gettering, and can use the outer LTO layer to prevent autodoping.

[0031] Preferably, the thickness of the silica back seal is 1000~4000 Å.

[0032] Preferably, the silica back seal is deposited using an atmospheric pressure chemical vapor deposition process.

[0033] Preferably, step S3 uses a chemical mechanical polishing process to remove the first and second polysilicon films on the front side of the wafer. When other back-sealing films are present in the back-sealing structure, such as... Figure 3 When a silicon dioxide film is present on the wafer, the silicon dioxide film on the front side of the wafer is also removed simultaneously. The silicon dioxide film on the front side of the wafer is preferably removed using the HF cleaning method.

[0034] Preferably, the wafer used for back sealing is a wafer that has been polished on both sides.

[0035] Example 1 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 610 °C using the LPCVD method; 3. Rotate the wafer 60° counterclockwise around the center, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 610℃. 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by HF cleaning, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing. 6. Measure the back side of the wafer using a Wafersight instrument with NT=29.12nm for 10mm x 10mm and NT=15.64nm for 2mm x 2mm.

[0036] Comparative Example 1 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 8000 Å polycrystalline silicon film was grown at 680℃ using the LPCVD method; 3. A second 3500 Å silicon dioxide film was grown using the APCVD method; 4. First, remove the front silicon dioxide film layer by HF cleaning, and then remove the polycrystalline silicon film layer on the front of the substrate by chemical mechanical polishing. 5. The back side of the wafer was measured using a Wafersight instrument with NT=112.8nm for 10mm x 10mm and NT=39.36nm for 2mm x 2mm.

[0037] Comparative Example 2 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 680℃ using the LPCVD method; 3. A second 4000 Å polycrystalline silicon film was grown at 680℃ using the LPCVD method; 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by HF cleaning, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing.

[0038] 6. Measure the back side of the wafer using a Wafersight instrument with NT=84.56nm for 10mm x 10mm and NT=29.06nm for 2mm x 2mm.

[0039] Comparative Example 3 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 680℃ using the LPCVD method; 3. Rotate the wafer 30° counterclockwise around the center, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 680°C. 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by HF cleaning, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing. 6. Measure the back side of the wafer using a Wafersight instrument with NT=40.23nm for 10mm x 10mm and NT=23.22nm for 2mm x 2mm.

[0040] Comparative Example 4 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 680℃ using the LPCVD method; 3. Rotate 60° counterclockwise around the center of the wafer, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 680℃. 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by HF cleaning, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing. 6. Measure the back surface of the wafer using a Wafersight instrument: 10mm x 10mm NT=32.89nm and 2mm x 2mm NT=18.83nm.

[0041] Comparative Example 5 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 610 °C using the LPCVD method; 3. Rotate the wafer 30° counterclockwise around the center, and then use LPCVD to grow a second 4000Å polycrystalline silicon film at 610℃. 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by cleaning with HF, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing. 6. Measure the back side of the wafer using a Wafersight instrument with NT=30.01nm for 10mm x 10mm and NT=17.98nm for 2mm x 2mm.

[0042] As can be seen from the above comparative examples and embodiments, when no rotation or a small rotation angle is performed during polycrystalline silicon back-side deposition, the resulting wafer back-side nano-morphology is inferior to that of Example 1. Similarly, when the deposition temperature is higher, the resulting wafer back-side nano-morphology is also inferior to that of Example 1.

[0043] Example 2 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 3500 Å silicon dioxide film was grown using the APCVD method; 3. The front silica film layer is removed by cleaning with HF; 4. The first 4000 Å polycrystalline silicon film was grown at 610 °C using the LPCVD method; 5. Rotate 60° counterclockwise around the center of the wafer, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 610℃. 6. Remove the polycrystalline silicon film layer on the front side of the substrate using a chemical mechanical polishing process; 7. Measure the back side of the wafer using a Wafersight instrument with NT=29.83nm at 10mm x 10mm and NT=16.43nm at 2mm x 2mm.

[0044] Example 3 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 1500 Å silicon dioxide film was grown using the APCVD method; 3. The front-side silica film is removed by cleaning with HF. 4. The first 4000 Å polycrystalline silicon film was grown at 610 °C using the LPCVD method; 5. Rotate 60° counterclockwise around the center of the wafer, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 610℃. 6. Then, a second 1500 Å silicon dioxide film is grown using the APCVD method; 7. Remove the front-side silica film layer by cleaning with HF; 8. Then, the polycrystalline silicon film layer on the front side of the substrate is removed by chemical mechanical polishing. 9. Measure the back side of the wafer using a Wafersight instrument with NT=29.75nm at 10mm x 10mm and NT=16.54nm at 2mm x 2mm.

[0045] Example 4 1. Through processes such as slicing, chamfering, double-sided grinding, and double-sided polishing, double-sided polished heavily doped wafers are produced; 2. The first 4000 Å polycrystalline silicon film was grown at 630℃ using the LPCVD method; 3. Rotate 90° clockwise around the center of the wafer, and then use the LPCVD method to grow a second 4000Å polycrystalline silicon film at 610℃. 4. A third 3500 Å silicon dioxide film was grown using the APCVD method; 5. First, remove the front silicon dioxide film layer by cleaning with HF, and then remove the polycrystalline silicon film layer on the front side of the substrate by chemical mechanical polishing.

[0046] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if these modifications and variations of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A method for improving the nanostructure of the back side of a heavily doped back-sealed wafer, wherein the back side of the wafer has a back-sealing structure, the back-sealing structure comprising at least a polysilicon back-sealing structure; characterized in that, The polycrystalline silicon back seal is prepared by the following method: S1. First, a first polycrystalline silicon film layer is grown on the surface of a wafer that has not been back-sealed or has been back-sealed at 600~670℃; S2. Then, the wafer is rotated horizontally to grow a second polycrystalline silicon film at 600~670°C; the horizontal rotation angle is >30°. S3. Remove the first polysilicon film layer and the second polysilicon film layer on the front side of the wafer.

2. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, The total thickness of the polycrystalline silicon back seal is 4000~14000 Å.

3. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, The polycrystalline silicon back seal is deposited using a low-pressure chemical vapor deposition process; the pressure is 100~140 mtorr.

4. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, The deposition temperature for steps S1 to S2 is 610 to 630℃.

5. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, In step S2, the rotation base point is the center of the wafer, and the rotation direction is clockwise or counterclockwise.

6. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, The back seal structure includes the polycrystalline silicon back seal and a silicon dioxide back seal located outside or inside the polycrystalline silicon back seal.

7. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 6, characterized in that, The thickness of the silica back seal is 1000~4000 Å.

8. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 6, characterized in that, The silica back seal is deposited using an atmospheric pressure chemical vapor deposition process.

9. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, Step S3 uses a chemical mechanical polishing process to remove the first polysilicon film layer and the second polysilicon film layer on the front side of the wafer.

10. The method for improving the nanostructure of the back side of a heavily doped back-sealed wafer as described in claim 1, characterized in that, The horizontal rotation angle described in step S2 is ≤180°.

Images