Semiconductor structure and method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
Smart Images
Figure CN122121648A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] As process nodes shrink, interconnect structures become smaller and smaller, making them prone to short circuits between interconnect structures and gate structures. Currently, self-aligned processes are mainly used to avoid short circuits between interconnect structures and gate structures.
[0003] Figure 1 This is a schematic diagram of a semiconductor structure using a self-aligned process. The semiconductor structure includes a substrate 100, in which a source electrode 130 and a drain electrode 140 are formed. The semiconductor structure also includes an interlayer dielectric layer 110 located on the surface of the substrate, and a metal gate structure located in the interlayer dielectric layer 110 and between the source electrode 130 and the drain electrode 140. The metal gate structure includes a spacer layer 121 and a metal gate layer 122 and a protective layer 123 stacked sequentially between the spacer layers 121.
[0004] The protective layer 123 is made of the same or similar material as the hard mask layer and has good electrical insulation properties. When the interconnect structure 150 partially covers the surface of the metal gate structure, the protective layer 121 can ensure electrical insulation between the metal gate layer 122 and the interconnect structure 150.
[0005] However, continue to refer to Figure 1 The protective layer 123 generates a parasitic capacitance C0 between the metal gate layer 122 and the interconnect structure 150, which affects the output power of the semiconductor structure during use and increases the RC delay of the circuit.
[0006] Therefore, in some embodiments, the material of the protective layer 123 is replaced with a low dielectric constant material to reduce the parasitic capacitance C0; however, referring to... Figure 2 Low dielectric constant materials have poor fatigue resistance, which can cause edge and corner losses during the formation process of the interconnect structure 150 and during the contact process with the interconnect structure 150. In severe cases, it can cause a short circuit between the metal gate layer 122 and the interconnect structure 150.
[0007] Therefore, a semiconductor structure is needed that can reduce the parasitic capacitance caused by the protective layer, avoid edge losses of the protective layer, and ensure the electrical isolation effect of the protective layer. Summary of the Invention
[0008] The purpose of this application is to provide a semiconductor structure and a method for forming the same, which reduces the parasitic capacitance generated by the protective layer between the metal gate layer and the interconnect structure in the semiconductor structure while avoiding edge loss of the protective layer.
[0009] In a first aspect, this application provides a method for forming a semiconductor structure, comprising: providing a substrate and a first interlayer dielectric layer located on the surface of the substrate, wherein a metal gate structure is formed in the first interlayer dielectric layer, the metal gate structure comprising a gate dielectric layer and a metal gate layer stacked sequentially, and a spacer layer located on both sides of the gate dielectric layer and the metal gate layer, and a source electrode and a drain electrode are formed in the substrate on both sides of the metal gate structure; partially etching the metal gate layer to form a first opening; forming a sidewall on the sidewall of the first opening; and completely filling the first opening with a dielectric material layer, wherein the dielectric constant of the dielectric material layer is less than the dielectric constant of the sidewall material.
[0010] In some embodiments, the dielectric constant of the dielectric material layer is less than 3.5, and the dielectric constant of the sidewall material is greater than 15.
[0011] In some embodiments, the sidewall material includes one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate; and the dielectric material layer material includes one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide.
[0012] In some embodiments, a method of forming a sidewall on the sidewall of the first opening includes: forming a sidewall material layer on the surface of the first interlayer dielectric layer and on the sidewall and bottom of the first opening; and etching away the sidewall material layer located on the surface of the first interlayer dielectric layer and on the bottom of the first opening to form the sidewall.
[0013] In some embodiments, the method of completely filling the first opening with a dielectric material layer includes: depositing the dielectric material layer on the surfaces of the first interlayer dielectric layer, the spacer layer, the sidewall, and the metal gate layer, wherein the dielectric material layer fills the first opening; and chemically mechanically polishing to remove the dielectric material layer from the surfaces of the first interlayer dielectric layer, the spacer layer, and the sidewall, thereby making the dielectric material layer coplanar with the first interlayer dielectric layer, the spacer layer, and the sidewall.
[0014] In some embodiments, the method of forming the semiconductor structure further includes: forming a second interlayer dielectric layer on the surfaces of the first interlayer dielectric layer, the spacer layer, the dielectric material layer and the sidewall; sequentially etching the second interlayer dielectric layer and the first interlayer dielectric layer at the corresponding positions of the source and the drain to fully expose the source and the drain to form a contact hole; and filling the contact hole with a conductive material to form an interconnect structure.
[0015] In a second aspect, this application discloses a semiconductor structure comprising: a substrate and a first interlayer dielectric layer located on the surface of the substrate; a metal gate structure comprising a gate dielectric layer and a metal gate layer stacked sequentially, and spacer layers located on both sides of the gate dielectric layer and the metal gate layer, wherein the surface of the metal gate layer is lower than the surface of the spacer layers; a dielectric material layer and sidewalls located on both sides of the dielectric material layer, the dielectric material layer and the sidewalls being located on the surface of the metal gate layer and between the spacer layers, wherein the dielectric constant of the dielectric material layer is less than the dielectric constant of the sidewall material; and a source and a drain located on both sides of the metal gate structure in the substrate.
[0016] In some embodiments, the dielectric constant of the dielectric material layer is less than 3.5, and the dielectric constant of the sidewall material is greater than 15.
[0017] In some embodiments, the sidewall material includes one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate; and the dielectric material layer material includes one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide.
[0018] In some embodiments, the semiconductor structure further includes: a second interlayer dielectric layer located on the surfaces of the first interlayer dielectric layer, the spacer layer, the dielectric material layer, and the sidewall; and an interconnect structure penetrating the first interlayer dielectric layer and the second interlayer dielectric layer, and electrically contacting the source and / or the drain; wherein the spacer layer, the dielectric material layer, and the sidewall are all coplanar with the first dielectric layer.
[0019] The beneficial effects of the semiconductor structure provided in this application embodiment include, but are not limited to:
[0020] The semiconductor structure provided in this application embodiment has a dielectric material layer disposed on the surface of a metal gate layer and sidewalls containing a high-k dielectric material located on both sides of the dielectric material layer. The dielectric material layer ensures electrical isolation between the metal gate layer and the interconnect structure when the interconnect structure portion is located on the dielectric material layer. Furthermore, the dielectric material layer is made of a low-k dielectric material, which has a low relative permittivity, resulting in small parasitic capacitance and reducing power loss during use of the semiconductor structure. In addition, the sidewalls on both sides of the dielectric material layer prevent edge losses and ensure the electrical isolation effect of the dielectric material layer. Attached Figure Description
[0021] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0022] in:
[0023] Figure 1 This is a schematic diagram of a semiconductor structure;
[0024] Figure 2 for Figure 1 A schematic diagram of the semiconductor structure after edge and corner loss is shown;
[0025] Figures 3 to 9 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0026] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0027] This application provides a method for forming a semiconductor structure, comprising: providing a substrate and a first interlayer dielectric layer located on the surface of the substrate, wherein a metal gate structure is formed in the first interlayer dielectric layer, the metal gate structure comprising a gate dielectric layer and a metal gate layer stacked sequentially, and a spacer layer located on both sides of the gate dielectric layer and the metal gate layer, and a source electrode and a drain electrode are formed in the substrate on both sides of the metal gate structure; partially etching the metal gate layer to form a first opening; forming a sidewall on the sidewall of the first opening; and completely filling the first opening with a dielectric material layer, wherein the dielectric constant of the dielectric material layer is less than the dielectric constant of the sidewall material.
[0028] The sidewall can fill the contact hole with conductive material to form an interconnect structure that protects the dielectric material layer, reducing edge loss of the dielectric material layer and thus preventing short circuits between the interconnect structure and the metal gate, thereby improving product yield. In addition, the low dielectric constant of the dielectric material layer can also reduce parasitic capacitance and improve product performance.
[0029] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.
[0030] The various operations are described sequentially as multiple discrete operations in a manner most conducive to understanding this application; however, the order of description should not be interpreted as implying that these operations must depend on the order. More specifically, these operations need not be performed in the order presented.
[0031] refer to Figure 3 A substrate 200 and a first interlayer dielectric layer 210 located on the surface of the substrate 200 are provided. A metal gate structure 220 is formed in the first interlayer dielectric layer 210, penetrating the first interlayer dielectric layer 210. The metal gate structure 220 includes a gate dielectric layer 221a and a metal gate layer 221b sequentially located on the surface of the substrate 200, and a spacer layer 222 located on both sides of the gate dielectric layer 221a and the metal gate layer 221b. A source electrode 230 and a drain electrode 240 are formed in the substrate 200 on both sides of the metal gate structure 220.
[0032] In some embodiments, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or silicon on insulator (SOI) or (iv) a combination thereof.
[0033] In some embodiments, the material of the first interlayer dielectric layer 210 includes silicon oxide, silicon dioxide, etc.
[0034] In some embodiments, the material of the gate dielectric layer 221a includes at least one of silicon oxide, silicon nitride, and hafnium oxide.
[0035] In some embodiments, the material of the metal gate layer 221b includes, but is not limited to, (i) a metallic element, such as ruthenium, palladium, platinum, cobalt, or nickel; or (ii) a conductive metal oxide, such as ruthenium oxide, for forming a P-type transistor. In other embodiments, the material of the metal gate layer 221b includes, but is not limited to, (i) a metallic element, such as hafnium, zirconium, titanium, tantalum, or aluminum; or (ii) a metal alloy, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, for forming an N-type transistor. The metal gate layer 221b can be formed by methods and processes known in the art, such as etching and deposition.
[0036] In some embodiments, the material of the spacer layer 222 includes at least one of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, or carbon-doped silicon oxide.
[0037] refer to Figure 4 The metal gate layer 221b is partially etched to form a first opening 223.
[0038] In some embodiments, the process for forming the first opening 223 is a plasma etching process or a wet etching process.
[0039] refer to Figure 5 and 6 A sidewall 224 is formed on the sidewall of the first opening 223.
[0040] In some embodiments, the sidewall 224 is made of a high-K dielectric material, such as one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. Optionally, the sidewall 224 is made of a high-K dielectric material with a dielectric constant greater than 15. High-K dielectric materials have superior fatigue resistance and are less prone to unnecessary losses during processing. In some embodiments, the sidewall material includes at least one of hafnium oxide and tantalum oxide.
[0041] In some implementations, the thickness of the sidewall 224 is 3 to 5 nm.
[0042] In some embodiments, the method of forming a sidewall 224 on the sidewall of the first opening 223 includes forming a sidewall material layer 225 on the surface of the first interlayer dielectric layer 210 and on the sidewall and bottom of the first opening 223; and removing the sidewall material layer 225 located on the surface of the first interlayer dielectric layer 210 and on the bottom of the first opening 223 to form the sidewall 224.
[0043] In some embodiments, the methods for forming the sidewall material layer 225 include, but are not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering. Methods for removing the sidewall material layer 225 located on the surface of the first interlayer dielectric layer 210 and at the bottom of the first opening 223 include, for example, wet etching, dry etching, or CMP. In some embodiments, plasma etching is used to remove the sidewall material layer 225 located on the surface of the first interlayer dielectric layer 210 and at the bottom of the first opening 223.
[0044] refer to Figure 7 The dielectric material layer 226 is completely filled into the first opening 223.
[0045] In some embodiments, the relative permittivity of the dielectric material layer 226 is less than that of the sidewall 224 material. In some embodiments, the dielectric material layer 226 is a low-k dielectric material with a permittivity less than 3.5, such as one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide. In some embodiments, the dielectric layer material includes silicon oxide or silicon nitride at low temperatures.
[0046] The dielectric material layer 226 can prevent the metal gate structure 220 from short-circuiting with the conductive structure in subsequent processes. At the same time, because the dielectric constant of the dielectric material layer 226 is small, it avoids the generation of large parasitic capacitance in the dielectric material layer 226, which would affect the output power of the semiconductor structure during use.
[0047] In some embodiments, such as Figure 7 As shown, the method of completely filling the first opening 223 with the dielectric material layer 226 includes: depositing the dielectric material layer 226 on the surfaces of the first interlayer dielectric layer 210, the spacer layer 222, the sidewall 224, and the metal gate layer 221b, wherein the dielectric material layer 226 fills the first opening 223; then, removing the dielectric material layer 226 from the surfaces of the first interlayer dielectric layer 210, the spacer layer 222, and the sidewall 224 using a chemical mechanical polishing process, and making the dielectric material layer 226 coplanar with the first interlayer dielectric layer 210, the spacer layer 222, and the sidewall 224.
[0048] In some embodiments, reference Figure 8 A second interlayer dielectric 250 is formed on the surfaces of the first interlayer dielectric layer 210, the spacer layer 222, the dielectric material layer 226, and the sidewall 224. The second interlayer dielectric layer 250 and the first interlayer dielectric layer 210 at corresponding positions of the source electrode 230 and the drain electrode 240 are etched sequentially until the source electrode 230 and the drain electrode 240 are completely exposed, forming a contact hole 260.
[0049] In some embodiments, the material of the second interlayer dielectric layer 250 includes silicon oxide, silicon dioxide, or silicon nitride. In some embodiments, the material of the second interlayer dielectric layer 250 is the same as the material of the first interlayer dielectric layer 210.
[0050] In some embodiments, the method for forming the second interlayer dielectric layer 250 includes, but is not limited to, processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering.
[0051] In some embodiments, the process of forming the contact hole 260 includes, but is not limited to, photolithography and etching processes.
[0052] In some embodiments, the photolithography process in forming the contact hole 260 specifically includes: forming a patterned photoresist mask on the surface of the second interlayer dielectric layer 250, wherein the patterned photoresist mask defines the position of the contact hole 260 and aligns it with the positions of the source electrode 230 and the drain electrode 240; etching the second interlayer dielectric layer 250 and the first interlayer dielectric layer 210 to expose the source electrode 230 and / or the drain electrode 240, thereby forming the contact hole 260.
[0053] refer to Figure 9 Conductive material is filled into the contact hole 260 to form an interconnect structure 270.
[0054] In some embodiments, the conductive material is polycrystalline silicon or a metallic material.
[0055] In some embodiments, the process for forming the interconnect structure 270 includes, but is not limited to, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and sputtering.
[0056] During the formation of the contact hole 260, if the position of the contact hole 260 is not perfectly aligned and deviates, causing the dielectric material layer 226 to be partially exposed, the dielectric material layer 226 acts as a protective layer for the metal gate layer 221b after the interconnect structure 270 is formed within the contact hole 260, thus preventing a short circuit between the metal gate layer 221b and the interconnect structure 270. Furthermore, the sidewalls 224 located on both sides of the dielectric material layer 226 in this embodiment can prevent edge loss of the dielectric material layer 226 during the formation of the contact hole 260 and the interconnect structure 270, ensuring the electrical isolation effect of the dielectric material layer 226.
[0057] refer to Figure 9 This application also provides a semiconductor structure, including: a substrate 200 and a first interlayer dielectric layer 210 located on the surface of the substrate 200; a dielectric material layer 226 and a metal gate layer 221b stacked sequentially and penetrating the first interlayer dielectric layer 210, wherein sidewalls 224 are formed on both sides of the dielectric material layer 226, the sum of the widths of the sidewalls 224 and the dielectric material layer 226 is equal to the width of the metal gate layer 221b, and the dielectric constant of the dielectric material layer 226 is less than the dielectric constant of the sidewall 224; a spacer layer 222 penetrating the first interlayer dielectric layer 210 is formed on both sides of the dielectric material layer 226 and the metal gate layer 221b; and a source 230 and a drain 240 located on both sides of the spacer layer 222 in the substrate 200.
[0058] In some embodiments, the dielectric constant of the dielectric material layer 226 is less than 3.5, and the dielectric constant of the sidewall 224 material is greater than 15.
[0059] In some embodiments, the sidewall 224 is made of one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate; and the dielectric material layer 226 is made of one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide.
[0060] In some embodiments, the semiconductor structure further includes a second interlayer dielectric layer 250 located on the surfaces of the first interlayer dielectric layer 210, the spacer layer 222, the dielectric material layer 226, and the sidewall 224; and an interconnect structure 270 extending through the first interlayer dielectric layer 210 and the second interlayer dielectric layer 250 and in contact with the source 230 and / or the drain 240.
[0061] The semiconductor structure provided in this application and Figures 4-9 The semiconductor structures in the semiconductor structure formation methods shown are the same or similar, and will not be described in detail here for the sake of simplicity.
[0062] The beneficial effects of the semiconductor structure provided in this application embodiment include, but are not limited to:
[0063] The semiconductor structure provided in this application embodiment has a dielectric material layer disposed on the surface of a metal gate and sidewalls containing a high-k dielectric material located on both sides of the dielectric material layer. The dielectric material layer ensures electrical isolation between the metal gate and the interconnect structure when the interconnect structure portion is located on the dielectric material layer. Furthermore, the dielectric material layer is made of a low-k dielectric material, which has a low relative permittivity, resulting in small parasitic capacitance and reducing power loss during use of the semiconductor structure. In addition, the sidewalls on both sides of the dielectric material layer prevent edge losses and ensure the electrical isolation effect of the dielectric material layer.
[0064] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0065] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0066] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0067] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0068] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate and a first interlayer dielectric layer located on the surface of the substrate are provided. A metal gate structure is formed in the first interlayer dielectric layer, and the metal gate structure includes a gate dielectric layer and a metal gate layer stacked sequentially, and a spacer layer located on both sides of the gate dielectric layer and the metal gate layer. A source electrode and a drain electrode are formed in the substrate on both sides of the metal gate layer structure. Partial etching of the metal gate layer forms a first opening; A sidewall is formed on the sidewall of the first opening; as well as The first opening is completely filled with a dielectric material layer, the dielectric constant of which is less than that of the sidewall material.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The dielectric constant of the dielectric material layer is less than 3.5, and the dielectric constant of the sidewall material is greater than 15.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The sidewall material includes one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate; and the dielectric material layer material includes one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of forming a sidewall on the sidewall of the first opening includes: A sidewall material layer is formed on the surface of the first interlayer dielectric layer and on the sidewalls and bottom of the first opening; and The sidewall material layer located on the surface of the first interlayer dielectric layer and at the bottom of the first opening is etched away to form the sidewall.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of completely filling the first opening with a dielectric material layer includes: A dielectric material layer is deposited on the surfaces of the first interlayer dielectric layer, the spacer layer, the sidewall, and the metal gate layer, the dielectric material layer filling the first opening; and Chemical mechanical polishing removes the dielectric material layer from the surfaces of the first interlayer dielectric layer, the spacer layer, and the sidewall, making the dielectric material layer coplanar with the first interlayer dielectric layer, the spacer layer, and the sidewall.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: A second interlayer dielectric layer is formed on the surface of the first interlayer dielectric layer, the spacer layer, the dielectric material layer and the sidewall. The second interlayer dielectric layer and the first interlayer dielectric layer at the corresponding positions of the source and the drain are sequentially etched until the source and the drain are completely exposed to form contact holes. as well as The contact hole is filled with conductive material to form an interconnect structure.
7. A semiconductor structure, characterized in that, include: Substrate and a first interlayer dielectric layer located on the surface of the substrate; A metal gate structure, the metal gate structure comprising a gate dielectric layer and a metal gate layer stacked sequentially, and a spacer layer located on both sides of the gate dielectric layer and the metal gate layer, wherein the surface of the metal gate layer is lower than the surface of the spacer layer; A dielectric material layer and sidewalls located on both sides of the dielectric material layer, the dielectric material layer and the sidewalls being located on the surface of the metal gate layer and between the spacer layers, wherein the dielectric constant of the dielectric material layer is less than the dielectric constant of the sidewall material; and The source and drain are located in the substrate on both sides of the metal gate structure.
8. The semiconductor structure according to claim 7, characterized in that, The dielectric constant of the dielectric material layer is less than 3.5, and the dielectric constant of the sidewall material is greater than 15.
9. The semiconductor structure according to claim 8, characterized in that, The sidewall material includes one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate; and the dielectric material layer material includes one or more of silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, aluminum oxide, boron nitride, and boron carbide.
10. The semiconductor structure according to claim 7, characterized in that, Also includes: The second interlayer dielectric layer is located on the surface of the first interlayer dielectric layer, the spacer layer, the dielectric material layer, and the sidewall; as well as The interconnect structure extends through the first interlayer dielectric layer and the second interlayer dielectric layer, and is in electrical contact with the source and / or the drain; the spacer layer, the dielectric material layer, and the sidewall are all coplanar with the first dielectric layer.