A programmable power timing control system

Abstract

This invention relates to the field of automated testing technology and discloses a programmable power supply timing control system, comprising the following steps: constructing a modular hardware platform and completing software and hardware co-initialization; configuring the system and loading test tasks within the platform to generate a dynamically executable task list; based on this list, realizing collaborative data analysis of multiple test machines and closed-loop acquisition and analysis of a single test machine; processing abnormal modules and generating a structured test report. This invention supports flexible expansion through modular design, combines a dynamic list with a closed-loop feedback mechanism to achieve intelligent timing control and anomaly diagnosis, utilizes multi-machine collaboration to improve testing efficiency and consistency, and significantly improves the reliability, efficiency, and diagnostic capabilities of power supply timing testing.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology, and in particular to a programmable power timing control system. Background Technology

[0002] In the research, development, and production testing of electronic equipment, especially when performing long-term aging and functional verification on products such as OPS computers, conference screens, and ATV motherboards, power supply timing control is a critical step. Traditional testing methods face numerous technical bottlenecks in this stage: First, existing power sequence control devices are functionally limited and fixed, typically only able to execute preset power-on / off sequences, lacking flexible programming capabilities to adapt to diverse testing scenarios. More importantly, their control process is open-loop, only able to send power commands, unable to simultaneously acquire and verify the actual hardware state of the controlled device under the corresponding power sequence (such as power pin levels, device indicator lights, screen display content, etc.). This lack of status feedback makes it impossible to achieve closed-loop verification in the testing process, making it difficult to automatically determine whether the device responds as expected.

[0003] Secondly, when conducting parallel testing on multiple devices, the task assignment, initiation, and data collection are highly dependent on manual operation. Testers need to configure each device one by one, and after the test is completed, they also need to manually summarize the scattered logs and data generated by each device. The process is cumbersome, inefficient, and prone to errors, and cannot meet the needs of modern batch and automated testing.

[0004] Furthermore, defining complex test sequences often requires specialized coding skills, making on-site debugging and modification inconvenient and limiting the rapid iteration and flexibility of test solutions. For intermittent failures such as device startup failures, the timing of their occurrence is uncertain, and traditional methods require a large amount of manpower for long-term monitoring and manual triggering tests, resulting in extremely low reproduction efficiency and difficulty in fully recording the system's overall picture at the moment of failure (including power status, signal status, visual images, etc.), leading to a lack of key data support for subsequent analysis.

[0005] Therefore, there is an urgent need for a programmable power timing control method. This method can not only flexibly define complex power control sequences, but also integrate real-time feedback from multi-dimensional hardware states, forming a closed-loop logic of "control-monitoring-determination". By combining intuitive programmable methods (such as graphical interfaces or configuration files) with multi-device collaborative management mechanisms, rapid deployment, automatic execution, automatic anomaly capture, and unified data analysis of test tasks can be achieved, thereby significantly improving the automation level, coverage depth, and diagnostic efficiency of testing. Summary of the Invention

[0006] This invention overcomes the shortcomings of the prior art and provides a programmable power timing control system.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The first aspect of this invention provides a programmable power supply timing control method, comprising the following steps: Construct a modular hardware platform for programmable timing control of the power supply of programmable devices, and complete the collaborative initialization of the software environment within the modular hardware platform; Configure the system within the target modular hardware platform, load the test tasks, and generate a dynamic executable task list. By combining a dynamic executable task chain, collaborative data analysis of multiple test machines and closed-loop data acquisition and analysis of a single test machine are performed within the target modular hardware platform. Perform exception handling on abnormal modules and generate a structured test report for the test machine after exception handling.

[0008] Furthermore, in a preferred embodiment of the present invention, the construction of a modular hardware platform for programmable timing control of the power supply of the programmable device, and the completion of software environment co-initialization within the modular hardware platform, specifically includes: Acquire the programmable device power supply, calibrate it as the target device power supply, acquire the microcontroller unit, connect it to the target device power supply, and simultaneously acquire the test machine connected to the target device power supply. The test machine is a modular hardware platform, designated as a modular hardware platform to be processed, which includes different modules used for testing. The microcontroller unit performs a self-test initialization process on the modular hardware platform to be processed. The self-test initialization process is to perform a self-test on the basic hardware in the modular hardware platform to be processed through the startup loading program in the microcontroller unit, and control the basic hardware to maintain a stable working state. After the modular hardware platform to be processed undergoes self-test initialization, the microcontroller unit controls the power supply of the target device to connect to different modules within the modular hardware platform to be processed, thereby enabling the classified output processing of different modules of the modular hardware platform to be processed and the power supply of the target device. Simultaneously, the software environment of all modules is collaboratively initialized on the modular hardware platform to be processed, resulting in the target modular hardware platform.

[0009] Furthermore, in a preferred embodiment of the present invention, the step of configuring the system within the target modular hardware platform, loading the test task, and generating a dynamically executable task list specifically includes: The system configuration of different modules is handled by a microcontroller within the target modular hardware platform. Among them, the system configuration processing of different modules involves configuring standard standby status parameters within different modules and introducing target parameters of the test task to obtain the standard standby status parameters of different modules. Within the target modular hardware platform, preliminary module testing is performed on different modules using a visual graphical programming method. An XML test configuration file is preset using a text editor, and the XML test configuration file is loaded into the target modular hardware platform, which has undergone module system configuration processing, for secondary module testing via a microcontroller. Among them, the test logic that extracts the XML test configuration file before loading is marked as standard test logic. Through the standard test logic, real-time test tasks are extracted in the order of the standard test logic during the module testing process. Among them, the real-time test task is to record the channels and power output parameters of the target device connected to different modules, and to record the number of tests and the delay. By combining all real-time test tasks, a structured dynamic executable task list is constructed. The dynamic executable task list consists of different nodes, and each node records the real-time test task of a module.

[0010] Furthermore, in a preferred embodiment of the present invention, the step of combining a dynamic executable task list to perform collaborative data analysis of multiple test machines and closed-loop data acquisition and analysis of a single test machine within the target modular hardware platform specifically includes: For a single target modular hardware platform, i.e. a single test machine, all single test machines are clustered and networked through a wireless module with a pre-loaded Mesh protocol to obtain a cluster test machine network. In the cluster test machine network, a master control node test machine is dynamically elected, wherein the master control node test machine is the test machine with the earliest power-on time. All test machines in the cluster test machine except the master test machine are designated as node test machines. The master test machine is then controlled to send configuration files to all node test machines. The configuration files are XML test configuration files. Through the control center, all test machines are started synchronously, and closed-loop data acquisition and analysis of different individual test machines are performed synchronously to obtain qualified test machines and test machines to be processed. Within the control center, the status parameters of all test machines are displayed in real time through the host computer's UI interface, and the abnormal modules of the test machines to be processed are marked. At the same time, the running status of the test machines to be processed is dynamically displayed on the host computer.

[0011] Furthermore, in a preferred embodiment of the present invention, the step of synchronously starting all test machines and synchronously executing closed-loop data acquisition and analysis of different individual test machines to obtain qualified test machines and test machines to be processed specifically involves: For a single test machine, the operation is carried out according to the dynamic executable task chain, and the data output by different modules is monitored and collected in real time during the operation and calibrated as module output data. After the predetermined time, extract all module output data, and at the same time, preset the standard threshold of the module output data, determine whether the module output data is maintained within the standard threshold, and determine whether the state inside the test machine matches the expected state. If both are true, then the corresponding single test machine will be calibrated as a qualified test machine; If the module output data does not remain within the standard threshold or the state in the test machine does not match the expected state, then the corresponding single test machine will be marked as a test machine to be processed. The test machine is analyzed, and the module whose output data does not remain within the standard threshold is marked as an abnormal module. At the same time, the nodes in the test machine whose positioning status does not match the expected status, and different nodes in the test machine execute different running tasks, are marked as abnormal nodes. The modules in which the abnormal nodes are located are also called abnormal modules.

[0012] Furthermore, in a preferred embodiment of the present invention, the step of performing exception handling on the abnormal module and generating a structured test report for the test machine after exception handling specifically includes: When an abnormal module is marked on the host computer, the power supply of the target device is used to power off the entire test machine to be processed, thereby disconnecting the operation of all modules in the test machine to be processed, and recording all status parameters of the current abnormal module. Among them, all status parameters of the abnormal module include the power parameters of the power channel of the current target device, as well as the real-time status parameters of other modules connected to the abnormal module in the target modular hardware platform. All status parameters of the abnormal module are timestamped and recorded in the local log of the test machine to be processed; By combining the local logs of the test machine to be processed, a structured test report for the test machine to be processed is generated.

[0013] Furthermore, in a preferred embodiment of the present invention, the step of generating a structured test report for the test machine by combining the local logs of the test machine to be processed specifically includes: Aggregate all status parameters of the abnormal modules with timestamps stored in the local logs of all test machines to be processed, and perform time alignment processing on all status parameters of all abnormal modules based on the timestamps; Search for modules that are equal to the abnormal modules in the qualified testing machine, save the status parameters of the corresponding modules, and build timestamps for time alignment. After time alignment processing, the qualified test modules and abnormal modules are compared to generate a structured test report. The structured test report includes a comparison report of the modules and the status parameters of all modules. The structured test report is also uploaded to the control center.

[0014] This invention addresses the technical deficiencies in the background technology and offers the following beneficial effects: By constructing a modular hardware platform and completing software and hardware co-initialization, the system is configured and test tasks are loaded within the platform, generating a dynamically executable task list. Based on this list, collaborative data analysis of multiple test machines and closed-loop acquisition and analysis of a single test machine are achieved. Abnormal modules are processed, and structured test reports are generated. This invention supports flexible expansion through modular design, combines a dynamic list with a closed-loop feedback mechanism to achieve intelligent timing control and anomaly diagnosis, utilizes multi-machine collaboration to improve testing efficiency and consistency, and significantly enhances the reliability, efficiency, and diagnostic capabilities of power supply timing testing. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0016] Figure 1 A flowchart of a programmable power supply timing control method is shown; Figure 2 A flowchart illustrating a method for collaborative data analysis of multiple test machines within a target modular hardware platform is shown. Figure 3 A program view of a programmable power timing control system is shown. Figure 4 A schematic diagram of the test module in the target modular hardware platform is shown. Detailed Implementation

[0017] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0018] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0019] Figure 1 A flowchart of a programmable power supply timing control method is shown, including the following steps: S102: Construct a modular hardware platform for programmable timing control of the power supply of programmable devices, and complete the collaborative initialization of the software environment within the modular hardware platform; S104: Configure the system within the target modular hardware platform, load the test tasks, and generate a dynamic executable task list. S106: Combining a dynamic executable task chain, perform collaborative data analysis of multiple test machines within the target modular hardware platform, as well as closed-loop data acquisition and analysis of a single test machine. S108: Perform exception handling on the abnormal module and generate a structured test report for the test machine after exception handling.

[0020] Furthermore, in a preferred embodiment of the present invention, the construction of a modular hardware platform for programmable timing control of the power supply of the programmable device, and the completion of software environment co-initialization within the modular hardware platform, specifically includes: Acquire the programmable device power supply, calibrate it as the target device power supply, acquire the microcontroller unit, connect it to the target device power supply, and simultaneously acquire the test machine connected to the target device power supply. The test machine is a modular hardware platform, designated as a modular hardware platform to be processed, which includes different modules used for testing. The microcontroller unit performs a self-test initialization process on the modular hardware platform to be processed. The self-test initialization process is to perform a self-test on the basic hardware in the modular hardware platform to be processed through the startup loading program in the microcontroller unit, and control the basic hardware to maintain a stable working state. After the modular hardware platform to be processed undergoes self-test initialization, the microcontroller unit controls the power supply of the target device to connect to different modules within the modular hardware platform to be processed, thereby enabling the classified output processing of different modules of the modular hardware platform to be processed and the power supply of the target device. Simultaneously, the software environment of all modules is collaboratively initialized on the modular hardware platform to be processed, resulting in the target modular hardware platform.

[0021] It's important to note that the programmable power supply is the actuator that performs timing control, the microcontroller is the system's brain and coordination center, and the modular hardware platform carries various testing functions. Managing the programmable power supply and modular test platform collaboratively through a unified microcontroller differs from traditional single, fixed power sequencers or functionally distributed test equipment. This provides a unified hardware interface and management foundation for subsequent intelligent and programmable control. Self-testing the module platform allows it to enter a stable operating state, ensuring the hardware itself is fault-free. Initialization configures the basic operating environment, guaranteeing the reliability of the test execution carrier and preventing test errors or equipment damage due to hardware failure. By controlling the programmable power supply through the microcontroller, the entire system is directly powered. The entire system acts as a programmable power timing control system, directly powering all modules, achieving refined power management. This not only meets the specific power supply needs of different modules but also allows for flexible power shutdown when modules are idle or malfunctioning, saving energy and enhancing safety.

[0022] Furthermore, in a preferred embodiment of the present invention, the step of configuring the system within the target modular hardware platform, loading the test task, and generating a dynamically executable task list specifically includes: The system configuration of different modules is handled by a microcontroller within the target modular hardware platform. Among them, the system configuration processing of different modules involves configuring standard standby status parameters within different modules and introducing target parameters of the test task to obtain the standard standby status parameters of different modules. Within the target modular hardware platform, preliminary module testing is performed on different modules using a visual graphical programming method. An XML test configuration file is preset using a text editor, and the XML test configuration file is loaded into the target modular hardware platform, which has undergone module system configuration processing, for secondary module testing via a microcontroller. Among them, the test logic that extracts the XML test configuration file before loading is marked as standard test logic. Through the standard test logic, real-time test tasks are extracted in the order of the standard test logic during the module testing process. Among them, the real-time test task is to record the channels and power output parameters of the target device connected to different modules, and to record the number of tests and the delay. By combining all real-time test tasks, a structured dynamic executable task list is constructed. The dynamic executable task list consists of different nodes, and each node records the real-time test task of a module.

[0023] It should be noted that the microcontroller performs system configuration processing for different modules within the target modular hardware platform, specifically configuring the "standard standby state parameters" for each module on the platform. These parameters can be retrieved through the "target parameters of the test task," meaning that based on the module's model, specifications, and best practices, it is configured to a high-performance, low-noise, and stable ready state. This ensures that all modules are in a known and optimal baseline state, eliminating test deviations caused by manual configuration errors or improper configuration, and laying the foundation for high-precision, repeatable testing. Subsequently, preliminary module testing is performed using a visual graphical programming method, and a structured XML test configuration file is preset using a text editor and loaded into the system for secondary module testing, realizing dual-mode test task programming.

[0024] The visual programming provides an intuitive drag-and-drop interface, allowing users to quickly build simple test flows or perform functional verification on individual modules. XML configuration files define complex and precise test logic in a structured text format, suitable for describing advanced features such as conditional branches, loops, and parameterization, and facilitating version management and batch deployment. The test logic follows a test sequence, extracting real-time test tasks according to the order of standard test logic during module testing, improving the portability and reusability of the test program.

[0025] The target modular hardware platform includes a power management module, a digital I / O module, a protocol communication module, a vision acquisition module, an infrared control module, and a wireless networking module. The power management module provides precise, programmable power output and monitors and controls voltage, current, and power in real time. The digital I / O module detects the digital level status of the device under test (DUT) and outputs control signals to drive relays, indicator lights, etc. The protocol communication module communicates and monitors data with the DUT using bus protocols such as UART, I2C, and SPI. The vision acquisition module captures images through a camera and uses image processing algorithms to identify screen content or device physical status. The infrared control module transmits infrared remote control signals to simulate user remote control operations on the device. The wireless networking module enables network communication and collaborative control between multiple test units via Wi-Fi Mesh networking.

[0026] Furthermore, in a preferred embodiment of the present invention, the step of performing exception handling on the abnormal module and generating a structured test report for the test machine after exception handling specifically includes: When an abnormal module is marked on the host computer, the power supply of the target device is used to power off the entire test machine to be processed, thereby disconnecting the operation of all modules in the test machine to be processed, and recording all status parameters of the current abnormal module. Among them, all status parameters of the abnormal module include the power parameters of the power channel of the current target device, as well as the real-time status parameters of other modules connected to the abnormal module in the target modular hardware platform. All status parameters of the abnormal module are timestamped and recorded in the local log of the test machine to be processed; By combining the local logs of the test machine to be processed, a structured test report for the test machine to be processed is generated.

[0027] It should be noted that powering down the faulty module serves two purposes: preserving the data from the on-site debugging by R&D personnel and preventing the fault from escalating, thus protecting other parts of the system. Recording the state before power loss captures the last frame of data in the event of the fault. This achieves physical isolation of the fault, minimizing potential damage and improving the safety and reliability of the entire test system. Subsequent recording of the module's real-time status parameters is timestamped, ensuring the integrity and consistency of data recording and preventing data loss due to a complete power outage before data preservation is complete. Precise timestamps allow for accurate alignment of data from multiple modules and channels, reproducing the fault sequence; the orderly operation process ensures the integrity of the data packet's own logic.

[0028] Furthermore, in a preferred embodiment of the present invention, the step of generating a structured test report for the test machine by combining the local logs of the test machine to be processed specifically includes: Aggregate all status parameters of the abnormal modules with timestamps stored in the local logs of all test machines to be processed, and perform time alignment processing on all status parameters of all abnormal modules based on the timestamps; Search for modules that are equal to the abnormal modules in the qualified testing machine, save the status parameters of the corresponding modules, and build timestamps for time alignment. After time alignment processing, the qualified test modules and abnormal modules are compared to generate a structured test report. The structured test report includes a comparison report of the modules and the status parameters of all modules. The structured test report is also uploaded to the control center.

[0029] It should be noted that aggregating all status parameters of the faulty modules with timestamps from the local logs of all test machines aims to unify fault data scattered across multiple devices and time points onto a comparable time base, constructing a unified timeline and improving analysis efficiency. Subsequently, the time-aligned faulty module data is compared with normal module data to generate a structured test report containing a module comparison report and all relevant status parameters, which is then uploaded to the control center, enabling horizontal data comparison.

[0030] Figure 2A flowchart illustrating a method for collaborative data analysis across multiple test machines within a target modular hardware platform is provided, comprising the following steps: S202: Combining a dynamic executable task chain, perform collaborative data analysis of multiple test machines within the target modular hardware platform, as well as closed-loop data acquisition and analysis of a single test machine. S204: Synchronously start all test machines and simultaneously execute closed-loop data acquisition and analysis of different individual test machines to obtain qualified test machines and test machines to be processed.

[0031] Furthermore, in a preferred embodiment of the present invention, the step of combining a dynamic executable task list to perform collaborative data analysis of multiple test machines and closed-loop data acquisition and analysis of a single test machine within the target modular hardware platform specifically includes: For a single target modular hardware platform, i.e. a single test machine, all single test machines are clustered and networked through a wireless module with a pre-loaded Mesh protocol to obtain a cluster test machine network. In the cluster test machine network, a master control node test machine is dynamically elected, wherein the master control node test machine is the test machine with the earliest power-on time. All test machines in the cluster test machine except the master test machine are designated as node test machines. The master test machine is then controlled to send configuration files to all node test machines. The configuration files are XML test configuration files. Through the control center, all test machines are started synchronously, and closed-loop data acquisition and analysis of different individual test machines are performed synchronously to obtain qualified test machines and test machines to be processed. Within the control center, the status parameters of all test machines are displayed in real time through the host computer's UI interface, and the abnormal modules of the test machines to be processed are marked. At the same time, the running status of the test machines to be processed is dynamically displayed on the host computer.

[0032] It should be noted that each test machine automatically discovers and networks itself via a pre-installed Mesh protocol wireless module, forming a "cluster test machine network." Leveraging the self-organizing, self-healing, and multi-hop relay characteristics of Mesh networks, a decentralized and highly robust communication layer is constructed. The election of the master node enables autonomous cluster management, requiring no external server for initialization. This achieves "plug-and-play" clustering of test devices. The test network automatically forms upon power-on, significantly simplifying the deployment complexity of large-scale test systems. Simultaneously, there are master test machines and subordinate test machines. The master node acts as the manager and coordinator, ensuring that all execution units within the cluster receive completely consistent test task definitions. Within the control center, a host computer displays the real-time status parameters of all test machines through its UI interface, and identifies abnormal modules on test machines requiring processing. The host computer is a comprehensive decision support interface integrating topology, status, parameters, and real-time data. Developed under Windows, the host computer's UI interface is used to view device parameters.

[0033] Furthermore, in a preferred embodiment of the present invention, the step of synchronously starting all test machines and synchronously executing closed-loop data acquisition and analysis of different individual test machines to obtain qualified test machines and test machines to be processed specifically involves: For a single test machine, the operation is carried out according to the dynamic executable task chain, and the data output by different modules is monitored and collected in real time during the operation and calibrated as module output data. After the predetermined time, extract all module output data, and at the same time, preset the standard threshold of the module output data, determine whether the module output data is maintained within the standard threshold, and determine whether the state inside the test machine matches the expected state. If both are true, then the corresponding single test machine will be calibrated as a qualified test machine; If the module output data does not remain within the standard threshold or the state in the test machine does not match the expected state, then the corresponding single test machine will be marked as a test machine to be processed. The test machine is analyzed, and the module whose output data does not remain within the standard threshold is marked as an abnormal module. At the same time, the nodes in the test machine whose positioning status does not match the expected status, and different nodes in the test machine execute different running tasks, are marked as abnormal nodes. The modules in which the abnormal nodes are located are also called abnormal modules.

[0034] It should be noted that for a single test machine, operation is performed according to a dynamic executable task chain, and data output from different modules is monitored and collected in real time during operation. Because the chain provides precise timing and instructions, it ensures the standardization of actions, making the testing process fully data-driven and traceable. If the output data of a module does not match the standard value, the corresponding single test machine is designated as a test machine to be processed, achieving comprehensive verification from micro-parameters to macro-functionality. It not only ensures the correctness of each signal point but also ensures that the entire operation sequence achieves the expected functional goals, thus more comprehensively guaranteeing test quality. Finally, the abnormal module is obtained. This invention directly associates failure results with specific hardware modules and execution logic nodes, improving positioning accuracy. The value of testing extends from pre-quality control to rapid fault repair in production and R&D, significantly improving overall efficiency.

[0035] like Figure 3 As shown, a second aspect of the present invention also provides a programmable power timing control system, wherein the programmable power timing control system records a power timing control method program, and when the program is decoded and executed by a processor, the following steps are implemented: Construct a modular hardware platform for programmable timing control of the power supply of programmable devices, and complete the collaborative initialization of the software environment within the modular hardware platform; Configure the system within the target modular hardware platform, load the test tasks, and generate a dynamic executable task list. By combining a dynamic executable task chain, collaborative data analysis of multiple test machines and closed-loop data acquisition and analysis of a single test machine are performed within the target modular hardware platform. Perform exception handling on abnormal modules and generate a structured test report for the test machine after exception handling.

[0036] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A programmable power supply timing control method, characterized in that, Includes the following steps: Construct a modular hardware platform for programmable timing control of the power supply of programmable devices, and complete the collaborative initialization of the software environment within the modular hardware platform; Configure the system within the target modular hardware platform, load the test tasks, and generate a dynamic executable task list. By combining a dynamic executable task chain, collaborative data analysis of multiple test machines and closed-loop data acquisition and analysis of a single test machine are performed within the target modular hardware platform. Perform exception handling on abnormal modules and generate a structured test report for the test machine after exception handling.

2. The programmable power supply timing control method according to claim 1, characterized in that, The aforementioned modular hardware platform is used for programmable timing control of the power supply of programmable devices, and for completing the collaborative initialization of the software environment within the modular hardware platform, specifically as follows: Acquire the programmable device power supply, calibrate it as the target device power supply, acquire the microcontroller unit, connect it to the target device power supply, and simultaneously acquire the test machine connected to the target device power supply. The test machine is a modular hardware platform, designated as a modular hardware platform to be processed, which includes different modules used for testing. The microcontroller unit performs a self-test initialization process on the modular hardware platform to be processed. The self-test initialization process is to perform a self-test on the basic hardware in the modular hardware platform to be processed through the startup loading program in the microcontroller unit, and control the basic hardware to maintain a stable working state. After the modular hardware platform to be processed undergoes self-test initialization, the microcontroller unit controls the power supply of the target device to connect to different modules within the modular hardware platform to be processed, thereby enabling the classified output processing of different modules of the modular hardware platform to be processed and the power supply of the target device. Simultaneously, the software environment of all modules is collaboratively initialized on the modular hardware platform to be processed, resulting in the target modular hardware platform.

3. The programmable power supply timing control method according to claim 1, characterized in that, The process of configuring the system within the target modular hardware platform, loading test tasks, and generating a dynamically executable task list specifically involves: The system configuration of different modules is handled by a microcontroller within the target modular hardware platform. Among them, the system configuration processing of different modules involves configuring standard standby status parameters within different modules and introducing target parameters of the test task to obtain the standard standby status parameters of different modules. Within the target modular hardware platform, preliminary module testing is performed on different modules using a visual graphical programming method. An XML test configuration file is preset using a text editor, and the XML test configuration file is loaded into the target modular hardware platform, which has undergone module system configuration processing, for secondary module testing via a microcontroller. Among them, the test logic that extracts the XML test configuration file before loading is marked as standard test logic. Through the standard test logic, real-time test tasks are extracted in the order of the standard test logic during the module testing process. Among them, the real-time test task is to record the channels and power output parameters of the target device connected to different modules, and to record the number of tests and the delay. By combining all real-time test tasks, a structured dynamic executable task list is constructed. The dynamic executable task list consists of different nodes, and each node records the real-time test task of a module.

4. The programmable power supply timing control method according to claim 1, characterized in that, The process of combining a dynamic executable task list to perform collaborative data analysis across multiple test machines and closed-loop data acquisition and analysis for a single test machine within the target modular hardware platform specifically involves: For a single target modular hardware platform, i.e. a single test machine, all single test machines are clustered and networked through a wireless module with a pre-loaded Mesh protocol to obtain a cluster test machine network. In the cluster test machine network, a master control node test machine is dynamically elected, wherein the master control node test machine is the test machine with the earliest power-on time. All test machines in the cluster test machine except the master test machine are designated as node test machines. The master test machine is then controlled to send configuration files to all node test machines. The configuration files are XML test configuration files. Through the control center, all test machines are started synchronously, and closed-loop data acquisition and analysis of different individual test machines are performed synchronously to obtain qualified test machines and test machines to be processed. Within the control center, the status parameters of all test machines are displayed in real time through the host computer's UI interface, and the abnormal modules of the test machines to be processed are marked. At the same time, the running status of the test machines to be processed is dynamically displayed on the host computer.

5. The programmable power supply timing control method according to claim 4, characterized in that, The process involves synchronously starting all test machines and simultaneously executing closed-loop data acquisition and analysis on different individual test machines to identify qualified test machines and those awaiting processing. Specifically: For a single test machine, the operation is carried out according to the dynamic executable task chain, and the data output by different modules is monitored and collected in real time during the operation and calibrated as module output data. After the predetermined time, extract all module output data, and at the same time, preset the standard threshold of the module output data, determine whether the module output data is maintained within the standard threshold, and determine whether the state inside the test machine matches the expected state. If both are true, then the corresponding single test machine will be calibrated as a qualified test machine; If the module output data does not remain within the standard threshold or the state in the test machine does not match the expected state, then the corresponding single test machine will be marked as a test machine to be processed. The test machine is analyzed, and the module whose output data does not remain within the standard threshold is marked as an abnormal module. At the same time, the nodes in the test machine whose positioning status does not match the expected status, and different nodes in the test machine execute different running tasks, are marked as abnormal nodes. The modules in which the abnormal nodes are located are also called abnormal modules.

6. The programmable power supply timing control method according to claim 1, characterized in that, The process of handling exceptions in the abnormal module and generating a structured test report for the test machine after the exception handling is as follows: When an abnormal module is marked on the host computer, the power supply of the target device is used to power off the entire test machine to be processed, thereby disconnecting the operation of all modules in the test machine to be processed, and recording all status parameters of the current abnormal module. Among them, all status parameters of the abnormal module include the power parameters of the power channel of the current target device, as well as the real-time status parameters of other modules connected to the abnormal module in the target modular hardware platform. All status parameters of the abnormal module are timestamped and recorded in the local log of the test machine to be processed; By combining the local logs of the test machine to be processed, a structured test report for the test machine to be processed is generated.

7. The programmable power supply timing control method according to claim 6, characterized in that, The process of generating a structured test report for the test machine by combining its local logs is as follows: Aggregate all status parameters of the abnormal modules with timestamps stored in the local logs of all test machines to be processed, and perform time alignment processing on all status parameters of all abnormal modules based on the timestamps; Search for modules that are equal to the abnormal modules in the qualified testing machine, save the status parameters of the corresponding modules, and build timestamps for time alignment. After time alignment processing, the qualified test modules and abnormal modules are compared to generate a structured test report. The structured test report includes a comparison report of the modules and the status parameters of all modules. The structured test report is also uploaded to the control center.

8. A programmable power supply timing control system, characterized in that, The programmable power timing control system records a power timing control method program. When the program is stored in a memory and executed by a processor, it implements the programmable power timing control steps as described in any one of claims 1-7.

9. A programmable power supply timing control system, characterized in that, The target modular hardware platform in the programmable power timing control system includes the following test modules, specifically: Power management module; Digital I / O modules; Protocol communication module; Visual acquisition module; Infrared control module; Wireless networking module.

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