random number generator, chip

Abstract

This invention discloses a random number generator and chip, relating to the field of random number technology. The random number generator includes: a main random number generation circuit for generating random numbers; a cache control unit for sending multiple reference random numbers stored in the cache control unit to different multiple detection circuits, the number of reference random numbers being the same as the number of detection circuits; multiple detection circuits, each connected to the cache control unit and the main random number generation circuit, each detection circuit being used to obtain a first comparison result based on the random number and the reference random numbers; a comparison result generation device connected to the multiple detection circuits for obtaining a second comparison result based on the multiple first comparison results; and a random number output controller connected to the main random number generation circuit and the comparison result generation device, used to output the random number to an external device when the second comparison result determines that the random number is valid. This ensures the security of the final generated random number.

Description

Technical Field

[0001] This invention relates to the field of random number technology, and more particularly to a random number generator and chip. Background Technology

[0002] In modern cryptography, random numbers play a crucial role. Almost all cryptographic protocols, algorithms, and key generation utilize random numbers. Random number generators are considered a vital component of security systems. If a random number generator, due to design flaws or attacks, fails to generate random numbers that meet the required randomness, the security system becomes vulnerable to compromise, leading to serious consequences. Common random number generators utilize random noise from physical processes, such as thermal noise, shot noise, and metastability. With technological advancements, attack methods targeting true random number generators have become increasingly sophisticated, including glitches, temperature attacks, and electromagnetic attacks. Attackers can reduce the entropy of random numbers by altering the generator's noise environment or attacking key components, making the changes more predictable and easier to crack. Therefore, low-entropy random numbers cannot meet security requirements. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, a first objective of this invention is to provide a random number generator for generating secure random numbers.

[0004] The second objective of this invention is to provide a chip.

[0005] To achieve the above objectives, a first aspect of the present invention provides a random number generator, comprising: a random number generating main circuit for generating random numbers; a cache control unit for sending multiple reference random numbers stored in the cache control unit to different multiple detection circuits, wherein the number of the multiple reference random numbers is consistent with the number of the multiple detection circuits; the multiple detection circuits, each of which is connected to the cache control unit and the random number generating main circuit, and each of which is used to obtain a first comparison result based on the random number and the reference random number; a comparison result generating device connected to the multiple detection circuits, and used to obtain a second comparison result based on the multiple first comparison results; and a random number output controller connected to the random number generating main circuit and the comparison result generating device, wherein the random number output controller is used to output the random number to an external device when the random number is determined to be valid based on the second comparison result.

[0006] In addition, the random number generator according to embodiments of the present invention may also have the following additional technical features: According to one embodiment of the present invention, both the random number and the reference random number are binary random numbers, and the number of bits in the random number and the reference random number are the same. The main circuit for generating the random number is further configured to send the random number bit by bit to a plurality of the detection circuits. The buffer control unit is further configured to, for each reference random number, determine the detection circuit corresponding to the reference random number among the plurality of detection circuits, and send the reference random number bit by bit to the detection circuit corresponding to the reference random number. The time when the main circuit for generating the random number sends the first bit of the random number is the same as the time when the buffer control unit sends the first bit of the reference random number. The time interval between the time when the main circuit for generating the random number sends any two adjacent bits in the random number is the same as the time interval between the time when the buffer control unit sends any two adjacent bits in the reference random number.

[0007] According to one embodiment of the present invention, each of the detection circuits includes: an XOR gate, the first input of which is connected to the output of the random number generation main circuit, and the second input of which is connected to the output of the buffer control unit corresponding to the detection circuit; a reduction adder, the input of which is connected to the output of the XOR gate, the reduction adder being used to add the output data of the XOR gate after receiving the output of the XOR gate for each bit of the random number, to obtain a summing result; and a numerical judge, the input of which is connected to the output of the reduction adder, the numerical judge being used to output a first comparison result with a value of 0 when the summing result is within a preset range, and to output a first comparison result with a value of 1 when the summing result is not within the preset range.

[0008] According to one embodiment of the present invention, the comparison result generation device includes an OR gate, the output terminal of the OR gate is connected to the random number output controller, and the plurality of input terminals of the OR gate are connected one-to-one with the output terminals of the plurality of numerical judges. The OR gate is used to perform an OR logic operation on the plurality of first comparison results to generate a second comparison result.

[0009] According to one embodiment of the present invention, the preset range is (N, jN), where j is the number of bits of the random number, and N is a positive integer greater than 0 and less than j / 2.

[0010] According to one embodiment of the present invention, the random number output controller is specifically configured to: determine that the random number is invalid when the value of the second comparison result is 1, and determine that the random number is valid when the value of the second comparison result is 0.

[0011] According to one embodiment of the present invention, the random number generating main circuit is further connected to the cache control unit, and the random number generating main circuit is further configured to: send the random number to the cache control unit; the cache control unit is further configured to: store the random number as a new reference random number when it receives the random number.

[0012] According to one embodiment of the present invention, the plurality of reference random numbers includes a reference random number in which all bits are 1 and a reference random number in which all bits are 0.

[0013] According to one embodiment of the present invention, the output terminal of the OR gate is also connected to the input terminal of an external alarm device, so that the external alarm device issues an alarm message when it receives the second comparison result with a value of 1.

[0014] To achieve the above objectives, a second aspect of the present invention provides a chip including the random number generator described above.

[0015] A random number generator and chip according to an embodiment of the present invention includes: a main random number generating circuit for generating random numbers; a cache control unit for sending multiple reference random numbers stored in the cache control unit to different multiple detection circuits, wherein the number of multiple reference random numbers is consistent with the number of multiple detection circuits; multiple detection circuits, each detection circuit being connected to the cache control unit and the main random number generating circuit, and each detection circuit being used to obtain a first comparison result based on the random number and the reference random number; a comparison result generating device connected to the multiple detection circuits for obtaining a second comparison result based on the multiple first comparison results; and a random number output controller connected to the main random number generating circuit and the comparison result generating device for outputting the random number to an external device when the second comparison result determines that the random number is valid. Thus, multiple detection circuits can be used to compare the random number generated by the main random number generating circuit with the reference random number, thereby identifying random numbers generated by the main random number generating circuit that do not meet the requirements for difference from the reference random number, and discarding these random numbers, thereby ensuring the security of the finally generated random number.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of the random number generator according to an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of a random number generator according to an embodiment of the present invention; Figure 3 This is a structural block diagram of the chip according to an embodiment of the present invention. Detailed Implementation

[0018] The random number generator and chip of the present invention are described below with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the accompanying drawings are exemplary and should not be construed as limiting the present invention.

[0019] Figure 1 This is a structural block diagram of the random number generator according to an embodiment of the present invention.

[0020] like Figure 1 As shown, a random number generator 100 includes a main random number generation circuit 101 for generating random numbers; a buffer control unit 102 for sending multiple reference random numbers stored in the buffer control unit 102 to multiple different detection circuits 103, the number of reference random numbers being the same as the number of detection circuits 103; multiple detection circuits 103, each connected to the buffer control unit 102 and the main random number generation circuit 101, each detection circuit 103 for obtaining a first comparison result based on the random number and the reference random number; a comparison result generation device 105, connected to the multiple detection circuits 103, for obtaining a second comparison result based on the multiple first comparison results; and a random number output controller 104, connected to the main random number generation circuit 101 and the comparison result generation device 105, for outputting the random number to an external device when the second comparison result determines that the random number is valid.

[0021] The buffer control unit 102 includes multiple output terminals corresponding one-to-one with multiple detection circuits 103. The input terminal of each detection circuit 103 is connected to the corresponding output terminal of the buffer control unit 102. The number of reference random numbers is the same as the number of detection circuits 103. The buffer control unit 102 is specifically used to send multiple reference random numbers stored in the buffer control unit 102 to multiple detection circuits 103. Specifically, one reference random number is sent to one detection circuit 103, and any two reference random numbers are sent to different detection circuits 103.

[0022] In other words, the cache control unit 102 must ensure that the number of reference random numbers stored therein is equal to the number of detection circuits 103. When the cache control unit 102 sends the multiple reference random numbers stored therein, it must send each reference random number to only one detection circuit 103. It must also ensure that any two reference random numbers will be sent to different detection circuits 103, so that any two detection circuits 103 will receive different reference random numbers.

[0023] After the reference random number and the random number are sent to each detection circuit 103, each detection circuit 103 receives a random number and a reference random number. Each detection circuit 103 then compares the received random number with the reference random number to obtain a first comparison result, which is then sent to the comparison result generation device 105. Since the number of detection circuits 103 is the same as the number of reference random numbers, it is possible to compare the random number with each reference random number.

[0024] After receiving the first comparison results output by the multiple detection circuits 103, the comparison result generation device 105 generates a second comparison result based on the received first comparison results. The second comparison result can be used to characterize whether the random number is the same as, similar to, or significantly different from a certain reference random number.

[0025] When the random number output controller 104 determines, based on the second comparison result, that the random number is the same as, similar to, or significantly different from a certain reference random number, the random number output controller 104 determines that the random number is easily attacked and should be treated as a low-entropy random number, that is, determines that the random number is invalid and discards it; otherwise, determines that the random number is valid and outputs the random number to an external device.

[0026] In one specific embodiment, the reference random number stored in the cache control unit 102 may include automatically cached random numbers and configurable random numbers.

[0027] To obtain the aforementioned automatically cached random number, the random number generation main circuit 101 can be configured to also be connected to the cache control unit 102. The random number generation main circuit 101 is also used to: send the random number to the cache control unit 102; the cache control unit 102 is also used to: store the random number as a new reference random number when it receives the random number.

[0028] In other words, the cache control unit 102 can be set to automatically cache the random values ​​generated before the random number generation main circuit 101. The cache range can be configured, for example, the previous m consecutive random numbers can be cached and used as reference random numbers to be detected and compared with the currently generated random numbers.

[0029] The configurable random numbers mentioned above can include other random numbers with special meanings, such as all 0s, all 1s, or other specific values ​​that are easy for attackers to select. For example, the above multiple reference random numbers can be set to include a reference random number with all bits set to 1 and a reference random number with all bits set to 0.

[0030] Furthermore, the aforementioned configurable random numbers can also include random values ​​recently used by the application. These can be configured according to the application's needs, because these random values ​​have already been used to generate keys or cryptographic algorithms. If the current random value is equal to, similar to, or significantly different from these values, it is more likely to be cracked and should be treated as a low-entropy random number.

[0031] Therefore, the detection circuit 103 can compare the random numbers generated by the main random number generation circuit 101 with reference random numbers, thereby identifying random numbers generated by the main random number generation circuit 101 that do not meet the requirements for difference from the reference random numbers, and discarding these random numbers to ensure the security requirements of the final generated random numbers. Since multiple detection circuits 103 are used to detect the random numbers and multiple reference random numbers in parallel, a wide range of real-time detection can be achieved, so it will not significantly affect the efficiency of random number generation.

[0032] In some embodiments of the present invention, both the random number and the reference random number are binary random numbers, and the number of bits in the random number and the reference random number are the same. The main random number generating circuit 101 is further configured to send the random number bit by bit to multiple detection circuits 103. The buffer control unit 102 is further configured to, for each reference random number, determine the detection circuit 103 corresponding to the reference random number among the multiple detection circuits 103, and send the reference random number bit by bit to the detection circuit 103 corresponding to the reference random number. The time when the main random number generating circuit 101 sends the first bit of the random number is the same as the time when the buffer control unit 102 sends the first bit of the reference random number. The time interval between the time when the main random number generating circuit 101 sends any two adjacent bits in the random number is the same as the time interval between the time when the buffer control unit 102 sends any two adjacent bits in the reference random number.

[0033] Specifically, to compare the random number with the reference random number, both the random number and the reference random number are set to binary form, and the number of bits in the random number and the reference random number are set to be the same. Simultaneously, the timing of the random number generation main circuit 101 sending the first bit of the random number is set to coincide with the timing of the buffer control unit 102 sending the first bit of the reference random number. Furthermore, the time interval between the random number generation main circuit 101 sending any two adjacent bits of the random number is set to coincide with the time interval between the buffer control unit 102 sending any two adjacent bits of the reference random number. This allows the random number generation main circuit 101 and the buffer control unit 102 to simultaneously send the corresponding bits of the random number and the reference random number to the detection circuit 103.

[0034] Therefore, the detection circuit 103 can obtain the comparison result between the random number and the reference random number by simply comparing the data received from the random number generation main circuit 101 and the buffer control unit 102 at the same time, thereby supporting a simple, purely hardware-implemented detection circuit 103.

[0035] In some embodiments of the present invention, see Figure 2 Each detection circuit 103 includes: an XOR gate 1031, whose first input is connected to the output of the random number generation main circuit 101, and whose second input is connected to the output of the buffer control unit 102 corresponding to the detection circuit 103; a reduction adder 1032, whose input is connected to the output of the XOR gate 1031, and which adds the output data of the XOR gate 1031 after receiving the output of the XOR gate 1031 for each bit of the random number; and a numerical judge 1033, whose input is connected to the output of the reduction adder 1032, and which outputs a first comparison result of 0 when the addition result is within a preset range, and outputs a first comparison result of 1 when the addition result is not within the preset range. The numerical judge 1033 is also used to send the first comparison result to the comparison result generation device 105.

[0036] Specifically, for each detection circuit 103, after receiving data with the same bit position of the random number and the reference random number, the two data are XORed by the XOR gate 1031. If they are the same, the XOR gate 1031 outputs 0; if they are different, the XOR gate 1031 outputs 1.

[0037] A reduction adder 1032 is set after the XOR gate 1031. After receiving the output of the XOR gate 1031 for each bit of the random number, that is, after all bits of the random number and the reference random number have been XORed by the XOR gate 1031, the output data of the XOR gate 1031 are added together to obtain the sum.

[0038] The bit width k of the aforementioned reduce adder 1032 needs to be set to satisfy 2. k-1 ≥j, where j is the number of digits in the random number.

[0039] At this point, since the XOR gate 1031 outputs zero when the values ​​of the same bits of the random number and the aforementioned reference random number are the same, and output 1 when they are different, the sum of the bits output by the reduction adder 1032 is the number of different bits between the random number and the reference random number. As an example, suppose there is a 16-bit random number and a 16-bit reference random number, and the 2nd, 5th, and 8th bits of the random number are different from the 2nd, 5th, and 8th bits of the reference random number. Then the XOR gate 1031 will output 13 zeros and 3 ones, and the sum of the bits output by the reduction adder 1032 will be 3, that is, the number of different bits between the random number and the reference random number is 3.

[0040] Therefore, the difference between the random number and the reference random number can be obtained.

[0041] To avoid the above random numbers being low-entropy random numbers that are easily cracked, the difference between the random number and the reference random number should not be too small or too large. That is, the number of different bits should not be too small or too large. Therefore, the numerical judge 1033 is set to judge whether the summation result output by the reduce adder 1032 is within the preset range.

[0042] When the sum is within the preset range, it indicates that the random number has a higher entropy value than the reference random number, and the numerical judge 1033 outputs 0. When the sum is not within the preset range, it indicates that the random number has a lower entropy value than the reference random number, and the numerical judge 1033 outputs 1.

[0043] The preset range is (N, jN), where j is the number of bits in the random number and N is a positive integer greater than 0 and less than j / 2. The specific value of N can be set by the user according to their actual needs for the efficiency and quality of the random number generator 100. The larger the value of N, the more stringent the detection of random numbers. That is, the larger the value of N, the higher the quality of the random number generator 100 and the lower the efficiency. The smaller the value of N, the lower the quality of the random number generator 100 and the higher the efficiency. Therefore, an appropriate value of N can be set according to the application requirements to balance the efficiency and quality of random number generation.

[0044] Therefore, by setting the above preset range, users can adjust the efficiency and quality of the random number generator 100 themselves, thereby better meeting the needs of users.

[0045] The comparison result generation device 105 further includes an OR gate 1034. The output of the OR gate 1034 is connected to the random number output controller 104. The multiple inputs of the OR gate 1034 are connected one-to-one with the outputs of multiple numerical judges 1033. The OR gate 1034 is used to perform OR logic operation on the multiple first comparison results output by the multiple numerical judges 1033 to generate a second comparison result, and send the second comparison result to the random number output controller 104.

[0046] Specifically, the output of the numerical judge 1033 in each detection circuit 103 is input to the input of the OR gate 1034. Therefore, as long as the output of the numerical judge 1033 in one detection circuit 103 is 1, the comparison result of the OR gate 1034 will be 1. Only when the outputs of the numerical judges 1033 in all detection circuits 103 are 0 will the comparison result of the OR gate 1034 be 0.

[0047] The comparison result output by OR gate 1034 is input to the input terminal of random number output controller 104. Random number output controller 104 is specifically used to: determine that the random number is invalid when the value of the second comparison result is 1, and determine that the random number is valid when the value of the second comparison result is 0.

[0048] Therefore, the random number output controller 104 will only confirm the validity of a random number if the random number has a higher entropy value than all reference random numbers.

[0049] In some embodiments of the present invention, the output of the OR gate 1034 is also connected to the input of an external alarm device, so that when the external alarm device receives a second comparison result with a value of 1, it issues an alarm message to the user to issue a low-entropy alarm, so that the user knows that the current random number quality is insufficient and the probability of being attacked is high.

[0050] In summary, the random number generator of this invention includes a main random number generation circuit for generating random numbers; a cache control unit for sending multiple reference random numbers stored in the cache control unit to different multiple detection circuits, the number of reference random numbers being the same as the number of detection circuits; multiple detection circuits, each connected to the cache control unit and the main random number generation circuit, each detection circuit being used to obtain a first comparison result based on the random number and the reference random number; a comparison result generation device connected to the multiple detection circuits, used to obtain a second comparison result based on the multiple first comparison results; and a random number output controller connected to the main random number generation circuit and the comparison result generation device, used to output the random number to an external device when the second comparison result determines that the random number is valid. Thus, it is possible to set the detection circuits to compare the random numbers generated by the main random number generation circuit with the reference random numbers, thereby identifying random numbers generated by the main random number generation circuit that do not meet the requirements for difference from the reference random numbers, and discarding these random numbers, thereby ensuring the security of the finally generated random numbers. Because multiple detection circuits perform parallel detection of random numbers and multiple reference random numbers, a wide range of real-time detection can be achieved, thus largely without affecting the efficiency of random number generation. Furthermore, by setting a preset range of (N, jN), the efficiency and quality of the random number generator can be balanced by setting N, thereby improving the quality and security of the random numbers. Moreover, the aforementioned cache control unit, detection circuits, and random number output controller are all purely digital logic, resulting in low hardware costs and easy integration into random number generators or system circuits.

[0051] Furthermore, the present invention proposes a chip.

[0052] Figure 3 This is a structural block diagram of the chip according to an embodiment of the present invention.

[0053] like Figure 3 As shown, chip 10 includes the aforementioned random number generator 100.

[0054] The chip in this embodiment of the invention, through the random number generator of the above embodiment, can ensure the security of the final generated random number.

[0055] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein can be considered as a ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0056] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0057] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0058] In the description of this specification, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the present invention.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] In this specification, unless otherwise stated, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly defined. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0061] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0062] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A random number generator, characterized in that, include: A random number generation main circuit, which is used to generate random numbers; A cache control unit is configured to send multiple reference random numbers stored in the cache control unit to different multiple detection circuits, wherein the number of the multiple reference random numbers is the same as the number of the multiple detection circuits; The plurality of detection circuits are all connected to the cache control unit and the random number generation main circuit, and each detection circuit is used to obtain a first comparison result based on the random number and the reference random number; A comparison result generation device is connected to multiple detection circuits, and the comparison result generation device is used to obtain a second comparison result based on multiple first comparison results; A random number output controller is connected to the random number generation main circuit and the comparison result generation device. The random number output controller is used to output the random number to an external device when the random number is determined to be valid according to the second comparison result.

2. The random number generator according to claim 1, characterized in that, Both the random number and the reference random number are binary random numbers, and the number of bits in the random number and the reference random number are the same. The main circuit for generating the random number is further configured to send the random number bit by bit to multiple detection circuits. The buffer control unit is further configured to, for each reference random number, determine the detection circuit corresponding to the reference random number among the multiple detection circuits, and send the reference random number bit by bit to the detection circuit corresponding to the reference random number. The time when the main circuit for generating the random number sends the first bit of the random number is the same as the time when the buffer control unit sends the first bit of the reference random number. The time interval between the time when the main circuit for generating the random number sends any two adjacent bits in the random number is the same as the time interval between the time when the buffer control unit sends any two adjacent bits in the reference random number.

3. The random number generator according to claim 2, characterized in that, Each of the aforementioned detection circuits includes: An XOR gate, the first input of which is connected to the output of the random number generation main circuit, and the second input of which is connected to the output of the buffer control unit corresponding to the detection circuit; A reduction adder, wherein the input of the reduction adder is connected to the output of the XOR gate, and the reduction adder is used to add the output data of the XOR gate after receiving the output of the XOR gate for each bit of the random number, to obtain the addition result; A numerical judge is provided, the input of which is connected to the output of the reduction adder. The numerical judge is used to output a first comparison result with a value of 0 when the addition result is within a preset range, and to output a first comparison result with a value of 1 when the addition result is not within the preset range.

4. The random number generator according to claim 3, characterized in that, The comparison result generation device includes an OR gate, the output of which is connected to the random number output controller, and multiple inputs of the OR gate are connected one-to-one with the outputs of multiple numerical judges. The OR gate is used to perform an OR logic operation on multiple first comparison results to generate a second comparison result.

5. The random number generator according to claim 3, characterized in that, The preset range is (N, jN), where j is the number of bits of the random number, and N is a positive integer greater than 0 and less than j / 2.

6. The random number generator according to claim 4, characterized in that, The random number output controller is specifically used for: When the value of the second comparison result is 1, the random number is determined to be invalid; when the value of the second comparison result is 0, the random number is determined to be valid.

7. The random number generator according to claim 1, characterized in that, The random number generation main circuit is also connected to the cache control unit, and the random number generation main circuit is further used for: The random number is sent to the cache control unit; The cache control unit is also used for: Upon receiving the random number, the random number is stored as a new reference random number.

8. The random number generator according to claim 1, characterized in that, The plurality of reference random numbers includes a reference random number in which all bits are 1 and a reference random number in which all bits are 0.

9. The random number generator according to claim 4, characterized in that, The output of the OR gate is also connected to the input of an external alarm device, so that the external alarm device issues an alarm message when it receives the second comparison result with a value of 1.

10. A chip, characterized in that, Includes a random number generator according to any one of claims 1-9.

Images