Semiconductor device and method of operating a semiconductor device

Abstract

A semiconductor device and a method of operating the semiconductor device are disclosed. The semiconductor device includes: a plurality of identical semiconductor chips; and an intermediary on which the plurality of identical semiconductor chips are disposed. Each of the plurality of identical semiconductor chips manages a memory map including address information. The memory map includes a plurality of system memory regions respectively allocated to the plurality of identical semiconductor chips and a private memory region shared by the plurality of identical semiconductor chips. The private memory region is mirrored and copied to a mirror region of each of the plurality of system memory regions, and the plurality of identical semiconductor chips perform internal operations by using the private memory region.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0176902, filed on December 2, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices and methods of operating semiconductor devices. More specifically, this disclosure relates to semiconductor devices including homogeneous semiconductor chips and methods of operating semiconductor devices. Background Technology

[0003] In the semiconductor industry, the demand for high-capacity, thinner, and smaller semiconductor devices and the electronic devices that use these devices is increasing, and various packaging technologies associated with them continue to evolve. Semiconductor packages for electronic devices include semiconductor chips suitable for use in electronic products.

[0004] In general, semiconductor chips are manufactured in repeating patterns on wafers formed from semiconductor materials. The wafer is divided into a large number of individual semiconductor dies, and each of these dies is packaged into a semiconductor chip. Chiplet technology is used to form high-performance semiconductor packages by mounting various semiconductor chips on an interposer (or intermediate layer) substrate. Summary of the Invention

[0005] This disclosure (e.g., the inventive concept of this disclosure) provides a semiconductor device that performs stable control by including a similar semiconductor chip and a memory mapping managed by each of the similar semiconductor chips and including private regions.

[0006] According to one aspect of this disclosure (e.g., the inventive concept of this disclosure), a semiconductor device includes: a plurality of similar semiconductor chips; an intermediary on which the plurality of similar semiconductor chips are disposed, wherein each of the plurality of similar semiconductor chips manages a memory map including address information, the memory map including a plurality of system memory regions respectively allocated to the plurality of similar semiconductor chips and a private memory region shared by the plurality of similar semiconductor chips, the private memory region being mirrored and copied to a mirror region of each of the plurality of system memory regions, and the plurality of similar semiconductor chips performing internal operations by using the private memory region.

[0007] In one embodiment, each of the plurality of similar semiconductor chips may include a processor, a memory controller, and a network, the memory controller being configured to control external memory devices, the network being configured to manage memory mapping and connect the processor to the memory controller, and the processor being able to access the memory controller of the other semiconductor chip using a system memory region corresponding to the other semiconductor chip.

[0008] In one embodiment, each of the plurality of similar semiconductor chips may include a first interface for communicating with each other, and may access other semiconductor chips via the first interface using a corresponding system memory region.

[0009] In one embodiment, the semiconductor device may further include a plurality of memory chips for communicating with the plurality of semiconductor chips, and each of the plurality of semiconductor chips may include a second interface for communicating with the plurality of memory chips.

[0010] According to another aspect of this disclosure, a semiconductor device includes: a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being of the same type; and an intermediary on which the first semiconductor chip and the second semiconductor chip are mounted, wherein each of the first semiconductor chip and the second semiconductor chip manages a memory map including address information, the memory map including a private memory region, a first system memory region and a second system memory region, the private memory region being shared by the first semiconductor chip and the second semiconductor chip, the first system memory region being allocated to the first semiconductor chip and including a first mirror region in which the private memory region is copied, the second system memory region being allocated to the second semiconductor chip and including a second mirror region in which the private memory region is copied, and the first semiconductor chip accessing the second semiconductor chip by using the second system memory region, and the second semiconductor chip accessing the first semiconductor chip by using the first system memory region.

[0011] In one embodiment, the first semiconductor chip may perform internal operations by using either a private memory region or a first mirror region.

[0012] In one embodiment, the memory mapping may sequentially assign addresses from minimum to maximum to a private memory region, a first system memory region, and a second system memory region.

[0013] According to another aspect of this disclosure, a method of operating a semiconductor device including a plurality of semiconductor chips includes: assigning a unique number to the plurality of semiconductor chips; allocating, based on the unique number, a plurality of system memory regions, each corresponding to the plurality of semiconductor chips, to memory mappings including address information; allowing each of the plurality of semiconductor chips to access another semiconductor chip by using an address of another semiconductor chip in the plurality of system memory regions of the memory mappings; and performing internal operations of each of the plurality of semiconductor chips by using an address of a private memory region of the memory mappings. Attached Figure Description

[0014] Embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 This is a diagram illustrating a semiconductor device according to an embodiment;

[0016] Figure 2 This is a block diagram illustrating a first semiconductor chip and a second semiconductor chip according to an embodiment;

[0017] Figure 3 This is a diagram illustrating a memory mapping for each of a plurality of semiconductor chips included in a semiconductor device, according to an embodiment.

[0018] Figure 4A This is a diagram illustrating a memory mapping used to perform operations on a first semiconductor chip, and Figure 4B This is a diagram illustrating a memory mapping used to perform operations on a second semiconductor chip;

[0019] Figure 5 This is a flowchart illustrating an operation method of a semiconductor device according to an embodiment;

[0020] Figure 6A and Figure 6B This is a diagram illustrating an operation method of a semiconductor device according to an embodiment;

[0021] Figure 7 and Figure 8 This is a flowchart illustrating an operation method of a semiconductor device according to an embodiment;

[0022] Figure 9 This is a diagram illustrating a semiconductor device according to an embodiment;

[0023] Figure 10 This is a diagram illustrating the memory mapping used in each of a plurality of semiconductor chips included in a semiconductor device according to an embodiment;

[0024] Figure 11A and Figure 11B This is a diagram illustrating a semiconductor device according to an embodiment;

[0025] Figure 12 This is a diagram illustrating a semiconductor device according to an embodiment;

[0026] Figure 13 This is a cross-sectional view showing a memory chip included in a semiconductor device according to an embodiment; and

[0027] Figure 14 This is a block diagram illustrating a system of electronic devices including semiconductor devices according to an embodiment. Detailed Implementation

[0028] Various embodiments are described below with reference to the accompanying drawings.

[0029] Figure 1 This is a diagram illustrating a semiconductor device 10 according to an embodiment.

[0030] Reference Figure 1 The semiconductor device 10 may include an interposer (or intermediate layer) 300 and a plurality of semiconductor chips (e.g., a first semiconductor chip 110 and a second semiconductor chip 120). Here, the first semiconductor chip 110 and the second semiconductor chip 120 may be homogeneous semiconductor chips. Although Figure 1 Only the first semiconductor chip 110 and the second semiconductor chip 120 are shown, but this disclosure is not limited thereto, and the semiconductor device 10 may include a plurality of similar semiconductor chips and may further include heterogeneous semiconductor chips. In some embodiments, the semiconductor device 10 may be a system-on-a-chip (SoC), and may be a 2.5-dimensional (2.5D) SoC.

[0031] Intermediate 300 may be a redistributed substrate. Intermediate 300 may be configured such that the first semiconductor chip 110 is electrically connected to the second semiconductor chip 120, or the first semiconductor chip 110 and the second semiconductor chip 120 are electrically connected to another chip. Intermediate 300 may have wiring layers and vias connecting the wiring layers to each other. In some embodiments, intermediate 300 may be a silicon intermediate substrate including through-silicon vias (TSVs), but is not limited thereto.

[0032] The first semiconductor chip 110 and the second semiconductor chip 120 may be disposed (e.g., mounted) on the intermediate body 300 in a vertical direction (Z-axis direction). The first semiconductor chip 110 and the second semiconductor chip 120 may be arranged side-by-side on the upper surface of the intermediate body 300 in the X-axis direction. The first semiconductor chip 110 may communicate with the second semiconductor chip 120 via an interface (I / F). The first semiconductor chip 110 may be connected to the second semiconductor chip 120 via a high-speed input / output (HSIO) interface and may be coupled to the second semiconductor chip 120 via, for example, a die-to-die (D2D) interface or a chip-to-chip (C2C) interface. For example, the first semiconductor chip 110 may communicate with the second semiconductor chip 120 via a universal chiplet interconnect express (UCIe) interface.

[0033] although Figure 1 The illustration shows that each of the first semiconductor chip 110 and the second semiconductor chip 120 includes four interfaces arranged in a first direction (X-axis direction) and a second direction (Y-axis direction), but this disclosure is not limited thereto. Each of the first semiconductor chip 110 and the second semiconductor chip 120 may include at least one interface for communicating with each other, and may be disposed (e.g., mounted) on an intermediary 300 such that at least one interface faces each other.

[0034] Intermediate 300 may be on a substrate. The substrate may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a strip wiring substrate, etc. According to an embodiment, the substrate may be a large-area package substrate on which the first semiconductor chip 110 and the second semiconductor chip 120 are disposed (e.g., mounted). For example, the substrate may have a flat shape (such as a square or rectangle).

[0035] In some embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 may each be a logic semiconductor chip. In some embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 may each be a server chip or an accelerator chip. For example, the first semiconductor chip 110 may include a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller. The semiconductor device 10 may be an application processor (AP) (such as an application-specific integrated circuit (ASIC)), but is not limited thereto.

[0036] In this disclosure, a semiconductor chip may refer to a semiconductor die. A semiconductor die can be a unit constituting a semiconductor die including one or more cores. Multiple dies can be integrated to serve as a single semiconductor die. In some embodiments, multiple dies that can serve as a single semiconductor die can be individualized to construct individualized upper packages. The individualized upper packages can be disposed (e.g., mounted) on a lower module substrate and can be electrically connected to each other via the lower module substrate. When individualized upper packages are disposed (e.g., mounted) on a lower module substrate, a semiconductor package module including the lower module substrate can be configured as a package capable of performing the functions of a single semiconductor die.

[0037] In some embodiments, the plurality of die-grids may refer to individual chips constituting a multi-chip module (MCM). For example, each of the plurality of die-grids may include at least one of input / output circuitry, analog circuitry, memory circuitry, and serial-to-parallel conversion circuitry. Optionally, each of the plurality of die-grids may include at least one of a CPU, a GPU, and an FPGA. The number of die-grids disposed (e.g., mounted) on the interposer 300 is not particularly limited, and a greater number of die-grids than shown in the figures may also be disposed (e.g., mounted) on the interposer 300.

[0038] Figure 2 This is a block diagram illustrating a first semiconductor chip 110 and a second semiconductor chip 120 according to an embodiment.

[0039] Reference Figure 2 The first semiconductor chip 110 may include a processor 111, function blocks (intellectual property (IP)) 112, a network 113, a memory controller 114, shared memory 115, a bridge 116, first peripheral function blocks (PERI1) 117_1 to nth peripheral function blocks (PERIn) 117_n, and an interface 118. The second semiconductor chip 120 may include a processor 121, function blocks 122, a network 123, a memory controller 124, shared memory 125, a bridge 126, first peripheral function blocks 127_1 to nth peripheral function blocks 127_n, and an interface 128. The first semiconductor chip 110 and the second semiconductor chip 120 are analogous semiconductor chips and may include the same configuration, and the description of the internal configuration of the first semiconductor chip 110 can be applied to the internal configuration of the second semiconductor chip 120.

[0040] The processors 111 and 121, respectively included in the first semiconductor chip 110 and the second semiconductor chip 120, may include similar multi-core or heterogeneous multi-core processors. For example, processors 111 and 121 may be any of a CPU, GPU, image signal processor (ISP), digital signal processor (DSP), vision processing unit (VPU), and neural processing unit (NPU), and the number of processors 111 and 121 may be one or more. Processors 111 and 121 may execute various types of software (applications, operating systems, file systems, device driver code, boot code, etc.) loaded in shared memories 115 and 125, respectively.

[0041] Functional blocks 112 and 122, respectively included in the first semiconductor chip 110 and the second semiconductor chip 120, can be circuits or chips designed to perform specific functions. For example, functional blocks 112 and 122 may each include circuitry for artificial intelligence (AI) operations.

[0042] Network 113 of the first semiconductor chip 110 can provide communication paths between internal components of the first semiconductor chip 110. For example, network 113 can provide communication paths between processor 111, function block 112, memory controller 114, shared memory 115, bridge 116, first peripheral function blocks 117_1 to nth peripheral function blocks 117_n, and interface 118.

[0043] Processor 111 can access the components of first semiconductor chip 110 in a memory-mapped input / output (MMIO) manner, and can also access the components using memory mapping via network 113. Network 113 manages memory mapping including address information.

[0044] Network 123 of the second semiconductor chip 120 provides communication paths between internal components of the second semiconductor chip 120. Processor 121 can access the various components of the second semiconductor chip 120 in an MMIO manner and can access the components via memory mapping using network 123. In some embodiments, networks 113 and 123 may each be a network on-chip (NoC).

[0045] The memory mapping of the first semiconductor chip 110 and the memory mapping of the second semiconductor chip 120 may include the same address information. Therefore, when using the first semiconductor chip 110 and the second semiconductor chip 120, the semiconductor device 10 can have the same effect as using a single semiconductor chip, and the space used for loading software executed in the first semiconductor chip 110 and the second semiconductor chip 120 can be reduced, and maintainability can be improved.

[0046] The memory controller 114 of the first semiconductor chip 110 and the memory controller 124 of the second semiconductor chip 120 can each control the external memory devices of the first semiconductor chip 110 and the second semiconductor chip 120 (e.g., Figure 12 (210, 220, 230 and 240).

[0047] In some embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 can perform addition / subtraction / multiplication / division operations, vector operations, address operations, Fast Fourier Transform (FFT) operations, etc., using a memory device. Furthermore, the first semiconductor chip 110 and the second semiconductor chip 120 can perform inference functions using a memory device. Here, inference can be performed using a deep learning algorithm of an artificial neural network. The deep learning algorithm may include training operations for training a model with various data and inference operations for identifying data using the trained model. Additionally, the memory device can be used as a temporary storage device for operating system and application data by loading operating system and application data, or as an execution space for various types of software code.

[0048] For example, semiconductor device 10 may include multiple dynamic random access memories (DRAMs), and memory controllers 114 and 124 may be DRAM controllers. However, semiconductor device 10 is not limited to this, and any memory device (such as phase-change random access memory (PRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), or hybrid RAM) may be used as semiconductor device 10, provided that bandwidth, response speed, and voltage conditions are met.

[0049] Memory controllers 114 and 124 can access external memory devices via direct memory access (DMA). For example, memory controller 114 may include a command queue, a command scheduler, a read data queue, a write data queue, a physical layer (PHY), etc.

[0050] The shared memory 115 included in the first semiconductor chip 110 can store applications, operating systems, file systems, device drivers, etc., used to drive the first semiconductor chip 110, and the shared memory 125 included in the second semiconductor chip 120 can store applications, operating systems, file systems, device drivers, etc., used to drive the second semiconductor chip 120. For example, the shared memories 115 and 125 included in the first semiconductor chip 110 and the second semiconductor chip 120, respectively, can each be an SRAM device, which has a greater capacity than external memory devices (e.g., those connected to the memory controller 114 of the first semiconductor chip 110 and the memory controller 124 of the second semiconductor chip 120, respectively). Figure 12 The 210, 220, 230 and 240) have fast data input / output speeds.

[0051] A bridge 116 of the first semiconductor chip 110 can be connected to first peripheral function blocks 117_1 to nth peripheral function blocks 117_n, and a bridge 126 of the second semiconductor chip 120 can be connected to first peripheral function blocks 127_1 to nth peripheral function blocks 127_n. For example, data processed by first peripheral function blocks 117_1 to nth peripheral function blocks 117_n and first peripheral function blocks 127_1 to nth peripheral function blocks 127_n can be sent to other configurations of the first semiconductor chip 110 and the second semiconductor chip 120 for use thereon via bridges 116 and 126, respectively, and in this case, bridges 116 and 126 can each perform operations (such as protocol conversion or switching).

[0052] The first peripheral function blocks 117_1 to nth peripheral function blocks 117_n of the first semiconductor chip 110 and the first peripheral function blocks 127_1 to nth peripheral function blocks 127_n of the second semiconductor chip 120 may each include a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface (SPI), a mailbox, a system register block, etc. The first peripheral function blocks 117_1 to nth peripheral function blocks 117_n and the first peripheral function blocks 127_1 to nth peripheral function blocks 127_n may each include, for example, a remapping register block for remapping memory maps. When a remapping signal (or removal signal) for changing the memory mapping is received from outside the first semiconductor chip 110 and the second semiconductor chip 120, or when a signal for assigning a unique number to each of the first semiconductor chip 110 and the second semiconductor chip 120 is received, the processor (e.g., processor 111 or 121) of each of the first semiconductor chip 110 and the second semiconductor chip 120 may access the remapping register block to change the memory mapping managed by the network (e.g., network 113 or 123).

[0053] Figure 3 This is a diagram illustrating the memory mapping used in each of a plurality of semiconductor chips included in a semiconductor device 10 according to an embodiment. Figure 4A This is a diagram illustrating the memory mapping used to perform operations on the first semiconductor chip 110, and Figure 4B This is a diagram illustrating the memory mapping used to perform operations on the second semiconductor chip 120.

[0054] Reference Figure 1 and Figure 3 The memory mapping may include multiple system memory regions (e.g., a first system memory region and a second system memory region) corresponding to multiple semiconductor chips (e.g., a first semiconductor chip 110 and a second semiconductor chip 120) included in the semiconductor device 10. The multiple semiconductor chips may correspond 1:1 to the multiple system memory regions (e.g., the multiple semiconductor chips may have a one-to-one relationship with the multiple system memory regions). Furthermore, the memory mapping may include private memory regions shared by the multiple semiconductor chips (e.g., the first semiconductor chip 110 and the second semiconductor chip 120). The first semiconductor chip 110 and the second semiconductor chip 120 may use the same memory mapping including the same address information; therefore, the semiconductor device 10 may have the effect of using the first semiconductor chip 110 and the second semiconductor chip 120 as a single semiconductor chip.

[0055] The minimum to maximum addresses in the memory mapping can be sequentially assigned to the private memory region, the first system memory region, and the second system memory region. For example, the minimum address could be the starting address (START ADDRESS 0) of the private memory region, and addresses from the starting address (START ADDRESS 0) to the first starting address (START ADDRESS 1) of the first system memory region can be assigned to the private memory region. Furthermore, addresses from the first starting address (START ADDRESS 1) to the second starting address (START ADDRESS 2) of the second system memory region can be assigned to the first system memory region. Addresses from the second starting address (START ADDRESS 2) to the maximum address can be assigned to the second system memory region. Figure 3 The diagram illustrates a memory mapping in which two similar memory chips are included in a semiconductor device 10, and the configuration of the memory mapping can also be changed depending on the number of similar semiconductor chips included in the semiconductor device 10.

[0056] The private memory region can be accessed by the first semiconductor chip 110 and the second semiconductor chip 120, and can be the address space used by the first semiconductor chip 110 to perform internal operations, and can also be the address space used by the second semiconductor chip 120 to perform internal operations. That is, the first semiconductor chip 110 and the second semiconductor chip 120 can perform internal operations by accessing the private memory region, which is the same address space in the memory mapping.

[0057] For example, when performing a remapping operation to change address information in the memory mapping, the first semiconductor chip 110 and the second semiconductor chip 120 can execute boot code or perform the operation by using a private region of the memory mapping (e.g., a private memory region). The private region can be an address space unaffected by the memory mapping change operation; therefore, stable operation can be performed, and the design complexity of the semiconductor device can be reduced. Furthermore, because each of the semiconductor chips can perform internal operations by using a private region, the logic used to identify and process each of the semiconductor chips can be removed when executing code; therefore, the code can be optimized, and operational performance can be improved.

[0058] The first system memory region may be an address space containing address information regarding the operation of the first semiconductor chip 110, and the second system memory region may be an address space containing address information regarding the operation of the second semiconductor chip 120. To drive the first semiconductor chip 110 and the second semiconductor chip 120, a unique number may be assigned to each of the first semiconductor chip 110 and the second semiconductor chip 120 as identification information, and the first system memory region may be assigned to the first semiconductor chip 110 to correspond to the unique number, and the second system memory region may be assigned to the second semiconductor chip 120 to correspond to the unique number. When the unique number of the first semiconductor chip 110 and the second semiconductor chip 120 is changed, the system memory regions corresponding to the first semiconductor chip 110 and the second semiconductor chip 120, respectively, may also be changed. For example, the first semiconductor chip 110 may be changed to correspond to the second system memory region, and the second semiconductor chip 120 may be changed to correspond to the first system memory region. Each of the first system memory region and the second system memory region may include a mirror region to which a private memory region has been copied.

[0059] Reference Figure 1 and Figure 4A The first semiconductor chip 110 can perform operations using either the first system memory region or a private memory region. The second semiconductor chip 120 can access the configuration of the first semiconductor chip 110 using the first system memory region to perform operations on the first semiconductor chip 110.

[0060] The first system memory region may include a mirror region to which the private memory region is copied. Therefore, in order for the second semiconductor chip 120 to perform operations on the first semiconductor chip 110 using the private memory region, the second semiconductor chip 120 may access the mirror region of the first system memory region.

[0061] Reference Figure 1 and Figure 4B The second semiconductor chip 120 can perform operations using either a second system memory region or a private memory region. The first semiconductor chip 110 can access the configuration of the second semiconductor chip 120 using the second system memory region to perform operations on the second semiconductor chip 120.

[0062] The second system memory region may include a mirror region to which the private memory region is copied. Therefore, in order for the first semiconductor chip 110 to perform operations on the second semiconductor chip 120 using the private memory region, the first semiconductor chip 110 may access the mirror region of the second system memory region.

[0063] Figure 5 This is a flowchart illustrating an operation method of the semiconductor device 10 according to an embodiment. Figure 6A and Figure 6B This is a diagram illustrating the operation method of the semiconductor device 10 according to an embodiment.

[0064] Reference Figure 1 and Figure 5 In operation S10, the semiconductor device 10 can assign a unique number to multiple semiconductor chips (e.g., the first semiconductor chip 110 and the second semiconductor chip 120).

[0065] In operation S20, the semiconductor device 10 can allocate system memory regions corresponding to multiple semiconductor chips, respectively, to memory maps including address information, based on the assigned unique numbers. For example, Figure 3 The first system memory region can be allocated to the first semiconductor chip 110, and Figure 3 The second system memory region can be allocated to the second semiconductor chip 120. Optionally, based on the unique assigned number, Figure 3 The second system memory region can also be allocated to the first semiconductor chip 110, and Figure 3 The first system memory area can also be allocated to the second semiconductor chip 120.

[0066] The first semiconductor chip 110 and the second semiconductor chip 120 can each receive information about unique identifiers for the first semiconductor chip 110 and the second semiconductor chip 120 from the outside as semiconductor chip identification information. The first semiconductor chip 110 can identify the memory-mapped address space assigned to the first semiconductor chip 110 from the information about the unique identifiers, and the second semiconductor chip 120 can identify the memory-mapped address space assigned to the second semiconductor chip 120 from the information about the unique identifiers.

[0067] Reference Figure 5 and Figure 6A In operation S30, each of the plurality of semiconductor chips can access the other semiconductor chip by using an address of a system memory region mapped by memory. For example, the processor 121 of the second semiconductor chip 120 can access the first semiconductor chip 110 and its memory controller 114 by using an address of the first system memory region. The processor 111 of the first semiconductor chip 110 can also access the memory controller 114 by using an address of the first system memory region.

[0068] Reference Figure 5 and Figure 6B In operation S40, each of the plurality of semiconductor chips can perform internal operations by using addresses of private memory regions mapped by memory. For example, the processor 111 of the first semiconductor chip 110 can access the shared memory 115 or the first peripheral function blocks 117_1 to nth peripheral function blocks 117_n by using the private memory region. The private memory region is mirrored to a mirror region of the system memory region; therefore, the processor 111 of the first semiconductor chip 110 can also access the shared memory 115 or the first peripheral function blocks 117_1 to nth peripheral function blocks 117_n by using the mirror region instead of the private memory region.

[0069] In some embodiments, the first semiconductor chip 110 is executable with boot code to execute a boot sequence, and the processor 111 may execute the boot code loaded into shared memory 115 using a private memory region. In some embodiments, the first semiconductor chip 110 is executable with boot code to execute a boot sequence, and the processor 111 may execute the boot code loaded into shared memory 115 using at least one of a mirror region and a private memory region. To execute the boot sequence, in addition to shared memory 115, which serves as internal memory of the first semiconductor chip 110, external memory (e.g., DRAM) of the first semiconductor chip 110 may also be used, and the processor 111 may also access memory controller 114 using a private memory region to execute the boot sequence. Optionally, the processor 111 may access iROM or iRAM using a private memory region to execute the boot sequence.

[0070] Optionally, in some embodiments, the nth peripheral functional block 117_n may be a remapping register block for changing the memory mapping, and the processor 111 may access the remapping register block using a mirror region or a private memory region. The processor 111 may remap the memory mapping in response to a remapping signal or semiconductor chip identification information of the first semiconductor chip 110 received from an external source by accessing the remapping register block. The remapping operation for changing the address information of the memory mapping may be performed using the address information (e.g., an address) of the private memory region of the memory mapping; therefore, the remapping operation can be stably performed even when information about the system memory regions corresponding to the semiconductor devices is changed.

[0071] Optionally, in some embodiments, device driver code for controlling the first peripheral function block 117_1 to the nth peripheral function block 117_n may be loaded into shared memory 115. Processor 111 may execute the device driver code using a private memory region.

[0072] In some embodiments, operation S40 may be executed independently of operations S10 and S20 (that is, operation S40 may be executed in parallel with operations S10 and S20). In other words, even when the system memory region is not allocated to multiple semiconductor chips, each of the multiple semiconductor chips can perform internal operations (e.g., boot sequences) using a private memory region. Therefore, stable boot sequence operations can be executed, logic for identifying and processing semiconductor chips during boot code execution can be removed to optimize the code, and operational performance can be improved.

[0073] Figure 7 and Figure 8This is a flowchart illustrating a method of operating a semiconductor device 10 according to some embodiments.

[0074] Reference Figure 1 and Figure 7 In operation S110, multiple semiconductor chips (e.g., first semiconductor chip 110 and second semiconductor chip 120) may receive a remapping signal. In operation S120, in response to the remapping signal, first semiconductor chip 110 and second semiconductor chip 120 may each execute actions to change system memory regions in the memory mapping other than private memory regions (e.g., Figure 3 This involves remapping the address information of the first system memory region and the second system memory region. For example, the unique number of the semiconductor chip can be changed so that the second system memory region is assigned to the first semiconductor chip 110, and the first system memory region is assigned to the second semiconductor chip 120. For example, the remapping signal can also be sent from outside the first semiconductor chip 110 and the second semiconductor chip 120, or it can be generated by the system register block inside the first semiconductor chip 110 and the second semiconductor chip 120.

[0075] Reference Figure 1 and Figure 8 In operation S210, multiple semiconductor chips (i.e., the first semiconductor chip 110 and the second semiconductor chip 120) can receive a removal signal. For example, the removal signal may include... Figure 7 In the remapping signal. In operation S220, the first semiconductor chip 110 and the second semiconductor chip 120 can remove private memory regions from the memory map in response to the removal signal. For example, the processor 111 of the first semiconductor chip 110 and the processor 121 of the second semiconductor chip 120 can access the remapping register block to remove the private memory regions from the memory map. When it is determined that private memory regions are not needed in multiple semiconductor chips, the semiconductor device 10 can use only multiple system memory regions by removing private memory regions, and when performing internal operations or operations for other semiconductor chips, the multiple semiconductor chips can use the address information of the system memory regions corresponding to a specific semiconductor chip.

[0076] Figure 9 This is a diagram illustrating a semiconductor device 10a according to an embodiment. Figure 10 This is a diagram illustrating the memory mapping used in each of a plurality of semiconductor chips included in a semiconductor device 10a according to an embodiment. In the description... Figure 9 When referring to the semiconductor device 10a, the above reference Figure 1 Redundant descriptions have been omitted.

[0077] Reference Figure 9 and Figure 10 The semiconductor device 10a may include an intermediary 300 and a plurality of semiconductor chips (e.g., a first semiconductor chip 110, a second semiconductor chip 120, a third semiconductor chip 130, and a fourth semiconductor chip 140). Here, the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 may be similar semiconductor chips. In some embodiments, the semiconductor device 10a may be a SoC (System-on-a-Chip).

[0078] The first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can be disposed (e.g., mounted) on the intermediate body 300 in the vertical direction (Z-axis). For example, the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can be arranged on the intermediate body 300 in two rows (X-axis direction) and two columns (Y-axis direction). The first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can communicate with each other through an interface.

[0079] The memory mapping may include first system memory regions to fourth system memory regions corresponding to a plurality of semiconductor chips (e.g., first semiconductor chip 110, second semiconductor chip 120, third semiconductor chip 130, and fourth semiconductor chip 140) included in the semiconductor device 10a, respectively. Furthermore, the memory mapping may include private memory regions shared by the plurality of semiconductor chips (i.e., first semiconductor chip 110, second semiconductor chip 120, third semiconductor chip 130, and fourth semiconductor chip 140).

[0080] The minimum to maximum addresses of the memory mapping can be sequentially assigned to private memory regions and first system memory regions to fourth system memory regions. For example, the minimum address could be the starting address (START ADDRESS 0) of the private memory region, and addresses from the starting address (START ADDRESS 0) to the first starting address (START ADDRESS 1) of the first system memory region can be assigned to the private memory region. Furthermore, addresses from the first starting address (START ADDRESS 1) to the second starting address (START ADDRESS 2) of the second system memory region can be assigned to the first system memory region, addresses from the second starting address (START ADDRESS 2) to the third starting address (START ADDRESS 3) of the third system memory region can be assigned to the second system memory region, addresses from the third starting address (START ADDRESS 3) to the fourth starting address (START ADDRESS 4) of the fourth system memory region can be assigned to the third system memory region, and addresses from the fourth starting address (START ADDRESS 4) to the maximum address can be assigned to the fourth system memory region. Figure 10 The memory mapping illustrates an example of four similar memory chips included in a semiconductor device 10a, and the configuration of the memory mapping can also be changed depending on the number of similar semiconductor chips included in the semiconductor device 10a.

[0081] To drive the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, unique numbers can be assigned to identify them. For example, a first system memory region can be assigned to the first semiconductor chip 110 to correspond to a first unique number, and a second system memory region can be assigned to the second semiconductor chip 120 to correspond to a second unique number. A third system memory region can be assigned to the third semiconductor chip 130 to correspond to a third unique number, and a fourth system memory region can be assigned to the fourth semiconductor chip 140 to correspond to a fourth unique number. When the unique numbers of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 are changed, the first system memory region, the second system memory region, the third system memory region, and the fourth system memory region corresponding to the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, respectively, can also be changed.

[0082] Each of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 1400 can perform operations by using a system memory region selected from the first system memory region to the fourth system memory region as the access point. Since the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can use memory mappings including the same address information, the semiconductor device 10a can have the effect of using the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 as a single semiconductor chip.

[0083] The private memory region is a memory region accessible by each of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, and can be the address space used by each of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 to perform internal operations. That is, each of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can perform internal operations by accessing the private memory region, which serves as the same address space in the memory mapping.

[0084] For example, the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 can each perform operations by using a private memory region of the memory map when executing boot code, performing a remapping operation to change address information in the memory map, or executing device driver code to control peripheral functional blocks. The private memory region is an address space unaffected by memory map changes; therefore, stable operation can be performed, and the design complexity of the semiconductor device can be reduced. Furthermore, because each of the semiconductor chips can perform internal operations using a private memory region, the logic used to identify and process the semiconductor chip during code execution can be removed; therefore, the code can be optimized, and operational performance can be improved.

[0085] The first through fourth system memory regions may each include a mirror region to which a private memory region has been copied. Therefore, the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 may each use the mirror region to perform internal operations, and may also use the mirror region of the corresponding system memory region. For example, the first semiconductor chip 110 may use the first system memory region to perform memory controller (e.g., ...) operations. Figure 2The operation of 114) can be performed, and shared memory (e.g.,) can be performed by using private memory regions or mirror regions. Figure 2 The operation of 115).

[0086] Figure 11A and Figure 11B This is a diagram illustrating a semiconductor device 10a according to an embodiment.

[0087] Reference Figure 11A The orientation in which the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, included in the semiconductor device 10a, access each other can be set. The memory mapping can be managed by a network included in the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140, and the orientation in which the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 access each other can be set in the memory mapping. For example, the orientation can be set such that the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140 access each other in a clockwise direction according to the arrangement of the first semiconductor chip 110, the second semiconductor chip 120, the third semiconductor chip 130, and the fourth semiconductor chip 140. In other words, the first semiconductor chip 110 can directly access the second semiconductor chip 120, and the first semiconductor chip 110 can pass through the second semiconductor chip 120 to access the fourth semiconductor chip 140, and the first semiconductor chip 110 can pass through the second semiconductor chip 120 and the fourth semiconductor chip 140 to access the third semiconductor chip 130.

[0088] Reference Figure 11B Faults can be detected in communications between specific semiconductor chips and other semiconductor chips. For example, when testing the operation of semiconductor device 10a, a fault can be detected in communications between specific semiconductor chips and other semiconductor chips. When a fault is detected, semiconductor device 10a can change the direction in which multiple semiconductor chips (e.g., first semiconductor chip 110, second semiconductor chip 120, third semiconductor chip 130, and fourth semiconductor chip 140) access each other.

[0089] For example, a fault can be detected in communication between the first semiconductor chip 110 and the second semiconductor chip 120 due to the interface of the first semiconductor chip 110 or the second semiconductor chip 120. The semiconductor device 10a can change and reset the access direction, such that the first semiconductor chip 110 accesses the third semiconductor chip 130 in a counter-clockwise direction, and that the first semiconductor chip 110 can pass through the third semiconductor chip 130 and the fourth semiconductor chip 140 to access the second semiconductor chip 120. Therefore, even if a fault is detected in communication between the semiconductor chips, the semiconductor device 10a can continue to be used by resetting the access direction between the semiconductor chips.

[0090] Figure 12 This is a diagram illustrating the semiconductor device 10b according to an embodiment.

[0091] Reference Figure 12 The semiconductor device 10b may include an intermediary 300, a plurality of semiconductor chips (e.g., a first semiconductor chip 110b and a second semiconductor chip 120b), and a plurality of memory chips (e.g., a first memory chip 210, a second memory chip 220, a third memory chip 230, and a fourth memory chip 240). Here, the first semiconductor chip 110b and the second semiconductor chip 120b may be of the same type. In some embodiments, the semiconductor device 10b may be a System-on-a-Chip (SoC). Figure 1 The descriptions of the first semiconductor chip 110 and the second semiconductor chip 120 shown in the figure can be applied in the same manner to the descriptions of the first semiconductor chip 110b and the second semiconductor chip 120b.

[0092] The first semiconductor chip 110b, the second semiconductor chip 120b, and the first memory chip 210, the second memory chip 220, the third memory chip 230, and the fourth memory chip 240 can be disposed (e.g., mounted) on the intermediate body 300 in a vertical direction (Z-axis direction). The first semiconductor chip 110b can communicate with the first memory chip 210 and the second memory chip 220 through a second interface, and the second semiconductor chip 120b can communicate with the third memory chip 230 and the fourth memory chip 240 through a second interface. The first semiconductor chip 110b can communicate with the second semiconductor chip 120b through a first interface.

[0093] In some embodiments, the first memory chip 210, the second memory chip 220, the third memory chip 230 and the fourth memory chip 240 may each be a volatile memory device (such as DRAM or SRAM), or may include a non-volatile memory device (such as flash memory, PRAM, MRAM, FeRAM or RRAM), or may include a high-performance memory device (such as high-bandwidth memory (HBM), hybrid memory cube (HMC) etc.).

[0094] Figure 13 This is a cross-sectional view showing a memory chip 200 included in a semiconductor device 10b according to an embodiment. Figure 13 The memory chip 200 can be, for example... Figure 12 One of the first memory chip 210, the second memory chip 220, the third memory chip 230, and the fourth memory chip 240.

[0095] Reference Figure 13 The memory chip 200 can be a three-dimensionally stacked memory device. The memory chip 200 may include a buffer die 1200 and multiple memory dies (e.g., first memory dies 1301 to nth memory dies 130n stacked on the buffer die 1200). n can be a natural number greater than or equal to 3, and for example, n can be 4 or 8 and can be modified in various ways. The buffer die 1200 and the first memory dies 1301 to nth memory dies 130n can be configured as a single semiconductor package.

[0096] The memory chip 200 may include a plurality of through-vias (TVs) passing through the buffer die 1200 and the first memory dies 1301 to the nth memory dies 130n, and a plurality of microbumps (MBPs) electrically connecting the through-vias (TVs) to each other. The plurality of through-vias (TVs) and the plurality of microbumps (MBPs) provide electrical paths between the buffer die 1200 and the first memory dies 1301 to the nth memory dies 130n in the memory chip 200. The number of through-vias (TVs) and the number of microbumps (MBPs) may be varied and are not limited to these specifications. Figure 13 The number shown in the figure. The nth memory die 130n may not include through vias, but is not particularly limited to this.

[0097] The first memory die 1301 to the nth memory die 130n may each be a DRAM chip. For example, the first memory die 1301 to the nth memory die 130n may each be a general-purpose DRAM device (such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM)), a mobile DRAM device (such as Low Power Double Data Rate (LPDDR) SDRAM), a graphics DRAM device (such as Graphics Double Data Rate (GDDR) Synchronous Graphics Random Access Memory (SGRAM)), or a DRAM device providing high capacity and high bandwidth (such as Wide Input / Output (I / O), High Bandwidth Memory (HBM), HBM2, HBM3, or Hybrid Memory Cube (HMC)). However, this disclosure is not limited thereto, and the first memory die 1301 to the nth memory die 130n may each be a volatile memory device other than DRAM, or a non-volatile memory device.

[0098] According to an embodiment, the first memory die 1301 to the nth memory die 130n may have substantially the same dimensions. That is, the first memory die 1301 to the nth memory die 130n may have substantially the same planar shape and planar dimensions.

[0099] The buffer die 1200 can provide data input / output signals, commands, addresses, and chip select signals received from the memory controller to first memory dies 1301 through nth memory dies 130n, or it can perform interface operations to provide data input / output signals received from first memory dies 1301 through nth memory dies 130n to a first semiconductor chip (e.g., Figure 12 110b) or a second semiconductor chip (e.g., Figure 12 The memory controller (120b) is included. The buffer die 1200 may include a PHY 1100 as interface circuitry to perform interface operations. The PHY 1100 can interact with... Figure 12 The second interface corresponds to this.

[0100] Figure 14 This is a block diagram illustrating a system of electronic devices including semiconductor devices 10, 10a, or 10b according to an embodiment.

[0101] Reference Figure 14System 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAM 2500a and 2500b, flash memory 2600a and 2600b, I / O devices 2700a and 2700b, and an access point (AP) 2800. System 2000 may be implemented using a laptop computer, mobile phone, smartphone, tablet computer, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, system 2000 may be implemented using a server or personal computer.

[0102] Camera 2100 can capture still or moving images under user control and can store or transmit captured images to display 2200. Audio processor 2300 can process audio data or network content included in flash memory 2600a and 2600b. Modem 2400 can modulate and transmit signals for wired / wireless data transmission and reception, and can demodulate signals and recover the original signals through a receiver. I / O devices 2700a and 2700b may include devices that provide digital input and / or output functions, such as Universal Serial Bus (USB), storage devices, digital cameras, Secure Digital (SD) cards, Digital Universal Discs (DVDs), network adapters, and touchscreens.

[0103] AP 2800 can control all operations of system 2000. AP 2800 may include controller 2810, accelerator 2820 (e.g., the accelerator is implemented as an accelerator block or accelerator chip), and interface 2830. AP 2800 can control display 2200 such that a portion of the data stored in flash memory 2600a and 2600b is displayed on display 2200. When user input is received through I / O devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input. AP 2800 may include accelerator 2820 as dedicated circuitry for AI data arithmetic operations, or may have an accelerator chip separate from AP 2800. DRAM 2500b may be additionally disposed (e.g., mounted) in accelerator block or accelerator chip 2820. Accelerator 2820 is a function block dedicated to performing specific functions of AP 2800, and may include a GPU as a function block dedicated to performing graphics data processing, an NPU as a function block dedicated to performing AI computation and inference, and a data processing unit (DPU) as a function block dedicated to data transfer.

[0104] In some embodiments, the accelerator block or accelerator chip 2820 may include a reference Figure 1 The first semiconductor chip 110 and the second semiconductor chip 120 described herein, with reference to Figure 9The first semiconductor chip 110 to the fourth semiconductor chip 140 described herein, or refer to Figure 12 The first semiconductor chip 110b and the second semiconductor chip 120b are described. According to the semiconductor device of this disclosure, multiple semiconductor chips can operate as a single chip, thus improving operational performance.

[0105] System 2000 may include DRAM 2500a and 2500b. AP 2800 can control DRAM 2500a and 2500b via command and mode register (MRS) settings conforming to Joint Electronic Devices Engineering Committee (JEDEC) standards, or via setting the DRAM interface protocol to use company-specific features such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functionality. For example, AP 2800 can communicate with DRAM 2500a via JEDEC-compliant interfaces such as LPDDR4 and LPDDR5, and accelerator block or accelerator chip 2820 can perform communication by setting a new DRAM interface protocol to control DRAM 2500b for accelerators with higher bandwidth than DRAM 2500a.

[0106] although Figure 14 Only DRAMs 2500a and 2500b are shown, but this disclosure is not limited thereto, and any memory (such as PRAM, SRAM, MRAM, RRAM, FeRAM, or hybrid RAM) can be used, provided that the bandwidth, response speed, and voltage conditions of AP 2800 or accelerator chip 2820 are met. DRAMs 2500a and 2500b may have relatively lower latency than I / O devices 2700a and 2700b or flash memory 2600a and 2600b and relatively higher bandwidth than I / O devices 2700a and 2700b or flash memory 2600a and 2600b. DRAMs 2500a and 2500b may be initialized at power-up time of system 2000 to be used as temporary storage devices for operating system and application data when operating system and application data are loaded, or as execution areas for various types of software code.

[0107] DRAMs 2500a and 2500b can perform four basic operations (such as addition, subtraction, multiplication, and division), vector arithmetic, address arithmetic, or FFT. Furthermore, functions for performing inference can be performed by DRAMs 2500a and 2500b. Here, inference can be performed using deep learning algorithms employing artificial neural networks. Deep learning algorithms may include training operations that train a model using various data and inference operations that identify data using the trained model. In some embodiments, images captured by a user via camera 2100 can be signal-processed and stored in DRAM 2500b, and the accelerator block or accelerator chip 2820 can perform AI data arithmetic operations for identifying data using data stored in DRAM 2500b and functions for inference.

[0108] System 2000 may include multiple storage devices or flash memory 2600a and 2600b having capacities larger than those of DRAM 2500a and 2500b. Accelerator block or accelerator chip 2820 may perform training operations and AI data arithmetic operations using flash memory 2600a and 2600b. In some embodiments, flash memory 2600a and 2600b may include memory controller 2610 and flash memory 2620, and training operations and inference AI data arithmetic operations performed by AP 2800 and / or accelerator chip 2820 may be performed more efficiently by using arithmetic operation means included in memory controller 2610. Flash memory 2600a and 2600b may store images captured by camera 2100 or data transmitted via a data network. For example, flash memory 2600a and 2600b may store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0109] As described above, embodiments are disclosed in the accompanying drawings and this disclosure. Although specific terminology is used to describe the embodiments, these terms are for the purpose of describing the technical concept of this disclosure only and are not intended to limit the meaning or scope of this disclosure as described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be derived from them. Consequently, the true technical scope of this disclosure should be determined by the technical concept of the appended claims.

[0110] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Multiple similar semiconductor chips; An intermediary, wherein the plurality of similar semiconductor chips are disposed on the intermediary. in, Each of the plurality of similar semiconductor chips manages a memory mapping including address information. The memory mapping includes multiple system memory regions allocated to the plurality of similar semiconductor chips, and a private memory region shared by the plurality of similar semiconductor chips. The private memory region is mirrored and copied to a mirror region of each of the plurality of system memory regions, and The multiple similar semiconductor chips perform internal operations by using a private memory region.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of similar semiconductor chips includes a processor, internal memory, and a network. Boot code is loaded into the internal memory, and the network is configured to manage memory mapping and connect the processor to the internal memory. The processor accesses internal memory by using at least one of a memory-mapped private memory region and a mirror region to execute boot code.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of similar semiconductor chips includes a processor, a plurality of peripheral functional blocks, internal memory, and a network. Device driver code for controlling the plurality of peripheral functional blocks is loaded into the internal memory. The network is configured to manage memory mapping and connect the processor to the internal memory. The processor accesses internal memory by using at least one of a memory-mapped private memory region and a mirror region to execute device driver code.

4. The semiconductor device according to claim 1, wherein, Each of the plurality of similar semiconductor chips includes a processor, a remapped register block, and a network. The remapped register block is used to change the memory mapping, and the network is configured to manage the memory mapping and connect the processor to the remapped register block. The processor remaps the memory map by accessing the remapped register block through a private memory region of the memory map.

5. The semiconductor device according to claim 4, wherein, The processor accesses the remapped register block to remove the private memory region from the memory map.

6. The semiconductor device according to claim 1, wherein, The plurality of similar semiconductor chips includes four semiconductor chips arranged in two columns and two rows, and The directions in which the four semiconductor chips access each other are preset.

7. The semiconductor device according to claim 1, wherein, The memory mapping sequentially assigns addresses from minimum to maximum to private memory regions and the multiple system memory regions corresponding to the multiple similar semiconductor chips.

8. A semiconductor device, comprising: The first semiconductor chip and the second semiconductor chip are of the same type. as well as An intermediary, on which the first semiconductor chip and the second semiconductor chip are disposed. in, Each of the first and second semiconductor chips manages a memory mapping that includes address information. The memory mapping includes a private memory region, a first system memory region, and a second system memory region. The private memory region is shared by the first semiconductor chip and the second semiconductor chip. The first system memory region is allocated to the first semiconductor chip and includes a first mirror region where the private memory region is copied. The second system memory region is allocated to the second semiconductor chip and includes a second mirror region where the private memory region is copied. The first semiconductor chip accesses the second semiconductor chip by using the second system memory region, and the second semiconductor chip accesses the first semiconductor chip by using the first system memory region.

9. The semiconductor device according to claim 8, wherein, Each of the first and second semiconductor chips includes a processor, internal memory, and a network. Boot code is loaded into the internal memory, and the network is configured to manage memory mapping and connect the processor to the internal memory. The processor accesses the boot code in internal memory by using one of the first and second mirror regions of the memory mapping or a private memory region.

10. The semiconductor device according to claim 8, wherein, Each of the first and second semiconductor chips includes a processor, a plurality of peripheral functional blocks, internal memory, and a network. Device driver code for controlling the plurality of peripheral functional blocks is loaded into the internal memory. The network is configured to manage memory mapping and connect the processor to the internal memory. The processor accesses internal memory by using one of the first and second mirror regions of the memory mapping or a private memory region to execute device driver code.

11. The semiconductor device according to claim 8, wherein, Each of the first and second semiconductor chips includes a processor, a remapping register block, and a network. The remapping register block is used to change the memory mapping, and the network is configured to manage the memory mapping and connect the processor to the remapping register block. The processor remaps the memory map by accessing the remapped register block through one of the first and second mirror regions of the memory map or a private memory region.

12. The semiconductor device according to claim 11, wherein, The processor accesses the remapped register block to remove the private memory region from the memory map.

13. The semiconductor device according to claim 8, further comprising: At least one memory chip is configured to communicate with one of a first semiconductor chip and a second semiconductor chip.

14. The semiconductor device according to claim 13, wherein, The at least one memory chip includes a buffer die and a plurality of memory dies stacked on the buffer die.

15. A method of operating a semiconductor device, the semiconductor device comprising a plurality of semiconductor chips, the method comprising: A unique number is assigned to the plurality of semiconductor chips; Based on the unique number, multiple system memory regions corresponding to the multiple semiconductor chips are allocated memory mappings, including address information. Each of the plurality of semiconductor chips is allowed to access the other semiconductor chip by using the address of the other semiconductor chip in the plurality of system memory regions mapped by memory; as well as The internal operations of each of the plurality of semiconductor chips are performed by using the addresses of private memory regions mapped by memory.

16. The operating method according to claim 15, wherein, Independent of the steps of assigning the unique number to the plurality of semiconductor chips and allocating the plurality of system memory regions corresponding to the plurality of semiconductor chips respectively, the step of performing internal operations of each of the plurality of semiconductor chips by using the address of a private memory region mapped by memory is performed.

17. The operating method according to claim 15, further comprising: The internal operations of each of the plurality of semiconductor chips are performed by using the address of the mirror region to which the private memory region of each of the plurality of system memory regions is copied.

18. The operating method according to claim 15, further comprising: The address information of regions other than the private memory region in the memory map is remapped by using the address of the private memory region.

19. The operating method according to claim 18, further comprising: The remapping signal is received from outside the plurality of semiconductor chips by the plurality of semiconductor chips. The address information is remapped in response to the remapping signal.

20. The operating method according to claim 15, further comprising: Remove the private memory region from the memory map.

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