Data reading methods, apparatus, computer equipment, readable storage media and program products

Abstract

This application relates to a data reading method, apparatus, computer device, computer-readable storage medium, and computer program product. The method includes: receiving a data loading instruction sent by a domain shader; the data loading instruction carrying at least one control point access request; calculating the vertex access address corresponding to each control point access request; reading a reference access address from a flag cache unit; comparing each vertex access address with the reference access address; when each vertex access address is equal and consistent with the reference access address, reading control point attribute information from the flag cache unit; and returning the control point attribute information to the register file unit. This method can improve the processing efficiency of the domain shader.

Description

Technical Field

[0001] This application relates to the field of graphics drawing technology, and in particular to a data reading method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of real-time rendering of 3D graphics and programmable pipeline technology of GPU (Graphics Processing Unit), tessellation technology has emerged. This technology can automatically generate a large number of new vertices during the rendering stage to improve the surface detail and realism of the model. The tessellation calculation is completed in collaboration with the Hull Shader (HS), the hardware tessellation unit (TS), and the Domain Shader (DS).

[0003] DS is the final stage of surface tessellation. It uses the control points output by HS and the domain coordinates subdivided by TS to calculate the spatial coordinates, colors, and texture maps of the new vertices. DS reads the control point attribute information output by HS from the vertex buffer unit when processing each domain coordinate, which leads to the slow processing speed of DS. Summary of the Invention

[0004] Therefore, it is necessary to provide a data reading method, apparatus, computer device, computer-readable storage medium, and computer program product that can improve the processing efficiency of domain shaders, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a data reading method, including:

[0006] Receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request.

[0007] Calculate the vertex access address corresponding to each of the control point access requests;

[0008] Read the reference access address from the flag cache unit, and compare each vertex access address with the reference access address;

[0009] When the access addresses of all the vertices are equal and consistent with the reference access address, the control point attribute information is read from the flag cache unit;

[0010] The control point attribute information is returned to the register file unit.

[0011] In one embodiment, the data loading instruction carries a control point access request corresponding to the current channel group; the reference access address is the target vertex access address corresponding to the previous channel group; the target vertex access address is obtained from the vertex access address corresponding to the previous channel group according to a preset rule.

[0012] In one embodiment, the method further includes:

[0013] When at least one of the vertex access addresses is inconsistent with the reference access address, the control point attribute information is read from the vertex cache unit according to the vertex access address;

[0014] The target vertex access address is determined from the vertex access address according to the preset rules;

[0015] The target vertex access address and the corresponding control point attribute information are stored in the flag cache unit, and the control point attribute information corresponding to the vertex access address is saved to the register file unit.

[0016] In one embodiment, the method further includes:

[0017] When the reference access address is not present in the flag cache unit, the control point attribute information is read from the vertex cache unit according to the vertex access address;

[0018] The target vertex access address is determined from the vertex access address according to the preset rules;

[0019] The target vertex access address and the corresponding control point attribute information are stored in the flag cache unit, and the control point attribute information corresponding to the vertex access address is saved to the register file unit.

[0020] In one embodiment, reading the reference access address from the flag cache unit and comparing each vertex access address with the reference access address includes:

[0021] Read the detection mark of the mark detection unit;

[0022] When the detection flag is valid, the reference access address is read from the flag cache unit, and the access addresses of each vertex are compared with the reference access address.

[0023] In one embodiment, the data loading instruction is generated by the domain shader after determining the target control point based on the domain coordinates sent by the hardware subdivision unit, generating the control point access request based on the target control point, and then sending the control point access request in groups.

[0024] Secondly, this application also provides a data reading device, comprising:

[0025] The receiving module is used to receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request.

[0026] The address calculation module is used to calculate the vertex access address corresponding to each control point access request;

[0027] The comparison module is used to read the reference access address from the flag cache unit and compare each vertex access address with the reference access address;

[0028] The reading module is used to read control point attribute information from the flag cache unit when the access addresses of each vertex are equal and consistent with the reference access address;

[0029] The return module is used to return the control point attribute information to the register file unit.

[0030] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0031] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0032] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0033] The aforementioned data reading method, apparatus, computer equipment, computer-readable storage medium, and computer program product include an ILD that receives data loading instructions sent by a DS and calculates the vertex access addresses corresponding to each control point access request based on the control point access requests carried in the data loading instructions. Then, the vertex access addresses are compared with reference access addresses. When all vertex access addresses are equal and consistent with the reference access addresses, the pre-stored control point attribute information can be directly read from the flag cache unit without having to read it from the VB unit. This effectively reduces the number of times the VB unit is read, alleviates the read / write pressure on the VB unit, and thus improves the processing efficiency of the DS. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a drawing pipeline for the curve subdivision module in one embodiment;

[0036] Figure 2 This is a schematic diagram of domain shader data reading in one embodiment;

[0037] Figure 3 This is a schematic diagram of the control point data access mechanism in one embodiment;

[0038] Figure 4 This is an application environment diagram of a data reading method in one embodiment;

[0039] Figure 5 This is a flowchart illustrating a data reading method in one embodiment;

[0040] Figure 6 This is a schematic diagram of the structure of the input loading unit in an exemplary embodiment;

[0041] Figure 7 This is a schematic diagram of vertex access address checking in one embodiment;

[0042] Figure 8 This is a structural block diagram of a data reading device in one embodiment;

[0043] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] Combination Figure 1 , Figure 1The rendering pipeline for the curve subdivision module in one embodiment comprises three parts: HS, DS, and TS. HS performs the pre-calculation process for surface subdivision, while DS is the post-processing process. For each subdivision patch, HS calculates multiple control points (CPs) and subdivision parameters (PCs). The subdivision parameters PCs are sent to TS to calculate the 2D UV coordinates of the new vertices. The control points CPs are then sent to DS, where DS interpolates the final 3D coordinates and attribute information such as color based on the control points and the vertex UV coordinates output by TS. DS then outputs the generated new vertex data to GS for subsequent geometric processing.

[0046] The DS interpolates the final 3D vertex coordinates and attribute information such as color based on the control point attribute information and the domain coordinates output by the TS. The control point attribute information output by the HS is stored in the vertex buffer unit, and this information can be retrieved from the vertex buffer unit through the ILD (Input Load) unit.

[0047] In GPUs, 32 or 64 parallel lanes are typically organized into a wave (thread bundle) and executed using SIMD32 or SIMD64 methods, respectively. In a Domain Shader Wave (DSW), each lane processes a domain coordinate output by the tessellation shader and calculates the corresponding vertex attribute data based on those coordinates. Therefore, a DSW with a SIMD32 execution width can perform vertex data calculations for 32 domain coordinates in parallel within one execution cycle.

[0048] For example, in combination Figure 2 , Figure 2 This is a schematic diagram of domain shader data reading in one embodiment. It includes: DSWC (Domain Shader Wave Controller), WVC (Wave Controller), IC (Instruction Cache), EU (Execution Unit), ILD (Input Load), VB (Vertex Buffer), and RF (Register File).

[0049] Among them, DSWC is used to receive the domain coordinates output by TS, pack them into DSW, and send the subdivision block address (PatchAddr) of the domain coordinates to the ILD unit for storage; WVC is used to manage and schedule the control unit of each thread, including thread selection, instruction fetching, decoding, and instruction issuing; IC instruction buffer is used to store instruction information, process WVC instruction fetch requests and return instructions to WVC unit; EU is used to execute ALU instructions and bypass ILD instructions to ILD unit; ILD is used to store the system generated values ​​of HS / DS / GS and read vertex and control point attribute information stored in vertex buffer unit; VB is used to process the read requests of ILD unit, return control point attribute data to ILD, and process read and write requests from other modules; RF is used to temporarily store intermediate data during the operation process.

[0050] For example, after receiving the domain coordinates from 32 TS outputs, the DSWC will package them into a DSW, with each lane of the DSW processing one domain coordinate. In the DS, control point attribute information stored in the VB unit is read via ILD instructions. After the DSW starts, it notifies the WVC to send an instruction fetch command to the IC unit. The WVC decodes the instruction returned by the IC and sends it to the EU for execution. If the current instruction is an ALU instruction, it is executed in the EU; if it is an ILD instruction, it is bypassed and executed in the ILD unit. The VB unit reads the attribute information from the cache according to the cache address in the ILD request and sends it back to the ILD unit, which then writes this information into the RF. The DSW interpolates the domain coordinates into new vertices based on the domain coordinates and control point attribute information, and these vertices can make the graphic details richer and more realistic.

[0051] As the final stage of the tessellation pipeline, DS receives control points and tessellation factors from HS output, and domain coordinates from TS output. The tessellation factor determines the number of domain coordinates generated by TS; a larger tessellation factor results in more domain coordinates generated by TS. This means many domain coordinates may be generated by the same tessellation block through TS. Therefore, when processing different domain coordinates, the same set of control point attribute data output by HS needs to be accessed repeatedly. However, DS needs to read the corresponding control point attribute information from the vertex buffer unit (VB) via ILD for each domain coordinate, leading to slow DS processing speed.

[0052] In an exemplary embodiment, the transmission bandwidth between the ILD unit and the VB unit is 512 bits. When the ILD unit reads VB in 4V1E mode, the bandwidth is fully utilized. One ILD instruction requires eight loops to complete. Here, the lanes (sub-units) of the four control points read are called Quads (channel groups), resulting in 8 Quads for 32 lanes, from Quad0 to Quad7. The read operation on the current Quad is abandoned only when all four lanes in the Quad are invalid. Figure 3 As shown, first, the ILD sends a read request to Quad0, with the VB_ADDR of the four lanes being 0 0 0 1 respectively. Then, it reads Quad1 to Quad6 in sequence. Since the lanes of Quad7 are all invalid, the VB_ADDR of the invalid lanes is represented by x, and the ILD no longer sends read requests to VB.

[0053] As mentioned earlier, VB retrieves attribute information from SRAM based on VB_ADDR sent down by ILD. If VB_ADDR is the same, the data returned by VB to ILD will definitely be the same as well. Figure 3 In this case, the VB_ADDR of the last lane in Quad0 is the same as the VB_ADDR of the four lanes in Quad1, and the VB_ADDR of the last lane in Quad3 is the same as the VB_ADDR of the four lanes in Quad4. Such an ILD instruction requires sending 7 read requests to VB.

[0054] Therefore, this application proposes a data reading method that can improve the efficiency of DS processing, and is applied to... Figure 4 In the application environment shown, the domain shader 102 sends a data loading instruction to the input loading unit 104, which then reads data from the vertex buffer unit 106 according to the instruction. The ILD includes a flag buffer unit (check_buf) and a flag detection unit (cmp_buf). The flag buffer unit stores the target vertex access address of the last valid lane in the previous channel group (Quad). The flag detection unit matches the cache address stored in the flag buffer unit with the subdivision block cache address to be read, as described in the following embodiments.

[0055] In one exemplary embodiment, such as Figure 5 As shown, a data reading method is provided, which can be applied to... Figure 4 Taking the input loading unit 104 as an example, the explanation includes the following steps 502 to 510. Wherein:

[0056] Step 502: Receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request.

[0057] The ILD instruction is used to read attribute information of vertices or control points from the Vertex Buffer Unit (VB). It performs different data reading tasks in different shading stages: in the HS stage, it reads vertex attributes output by the VS; in the DS stage, it reads control point attributes output by the HS; and in the GS stage, it reads vertex attributes output by the DS. Each vertex can contain 1 to 48 elements, each element has 4 channels (x, y, z, w), and each channel occupies 32 bits. Therefore, the data width of a single element is 128 bits, which can be abstracted as a float4 structure. The ILD instruction consists of a predicate control field, a destination register field, a control point index field, an attribute index field, and a field for the number of attributes to read. It controls which lanes participate in the reading, from which control point the attribute is read, and the number of attributes read at once within the SIMD thread bundle, and writes the reading results to the destination register file. The ILD unit reads data from the VB in batches using an nV1E method, meaning it reads the same attribute from n control points in parallel each time. The maximum number of data reads is limited by the transmission bandwidth between the ILD and VB; for example, when the transmission bandwidth is 512 bits, a maximum of 128 bits of attribute data from four control points can be read in a single transmission. When initiating a read request, the ILD needs to calculate the storage address of the target control point attribute in the SRAM cache. After receiving the request, the VB unit retrieves the attribute data from the corresponding location in the SRAM based on the address and returns the read attribute data to the ILD unit. The ILD unit then writes the attribute data into the RF for subsequent calculations by the DS.

[0058] Optionally, the ILD is used to receive load instructions from multiple programmable coloring stages. Therefore, it is necessary to determine whether the current load instruction comes from the DS. Only when the current load instruction comes from the DS will the subsequent detection process begin.

[0059] The ILD instruction is used by the domain shader to determine the target control point based on the domain coordinates sent by the hardware subdivision unit. It then generates a control point access request based on the target control point and sends the request in groups. These groups refer to dividing the request into multiple channel groups, or multiple quads.

[0060] For example, a DS Wave contains 32 parallel execution lanes, divided into 8 quads with 4 lanes per quad. Each lane corresponds to a domain coordinate, and the index of the target control point it needs to access is calculated based on the domain coordinate, thereby generating the corresponding control point access request. Therefore, a quad includes control point access requests corresponding to 4 domain coordinates.

[0061] The ILD instruction describes a single load operation of a Wave. At the hardware execution level, the ILD instruction is broken down into multiple Quad rounds and executed sequentially, with each round handling a control point access request for one Quad.

[0062] Step 504: Calculate the vertex access address corresponding to each control point access request.

[0063] Each control point access request includes a subdivision block address, a control point index, and an attribute index. For example, this can be represented by a structure: `struct VB_ADDR {uint32 eleId:6; uint32 vertexId:5; uint32 patchAddr:21}`. Here, `eleId:6` represents the attribute index, occupying 6 bits; `vertexId:5` represents the control point index, occupying 5 bits; and `patchAddr` represents the subdivision block address, occupying 21 bits.

[0064] Therefore, ILD extracts patchAddr, control point index, and attribute index from each control point access request, and performs bit concatenation on the above fields according to the preset bit width rules to generate the corresponding vertex access address.

[0065] For example, if patchAddr is 1, vertexId is 2, and eleId is 3, their binary representation in memory is 0b100010000011. Therefore, the vertex access address calculated by ILD is 0x883.

[0066] Step 506: Read the reference access address from the flag cache unit and compare the access address of each vertex with the reference access address.

[0067] Optionally, ILD reads the reference access address in check_buf, and then compares the vertex access addresses corresponding to multiple lanes in the current Quad with the reference access address using cmp_buf.

[0068] Here, the reference access address is the target vertex access address corresponding to the previous quad, and the target vertex access address is obtained from the vertex access addresses corresponding to the previous quad according to preset rules. For example, it can be the vertex access address corresponding to the last valid lane in the previous quad.

[0069] Step 508: When the access addresses of each vertex are equal and consistent with the reference access address, read the control point attribute information from the flag cache unit.

[0070] Since the flag cache unit stores the control point attribute information corresponding to the reference access address, when each vertex access address is the same and consistent with the reference access address, the control point attribute information can be read directly from the flag cache unit without having to read it from VB.

[0071] Step 510: Return the control point attribute information to the register file unit.

[0072] Optionally, after reading the control point attribute information from the flag cache unit, the control point attribute information is copied to the valid lanes in the current Quad, thereby returning the control point attribute information to the register file unit so that each valid lane can perform subsequent vertex attribute calculations in parallel.

[0073] In the above embodiment, the ILD receives the data loading instruction sent by the DS and calculates the vertex access address corresponding to each control point access request based on the control point access request carried in the data loading instruction. Then, the vertex access address is compared with the reference access address. When all vertex access addresses are equal and consistent with the reference access address, the pre-stored control point attribute information can be directly read from the flag cache unit without having to read it from the VB. This effectively reduces the number of times the VB is read, alleviates the read / write pressure on the VB unit, and thus improves the processing efficiency of the DS.

[0074] Furthermore, the above method also includes: when at least one vertex access address is inconsistent with the reference access address, reading control point attribute information from the vertex cache unit according to the vertex access address; determining the target vertex access address from the vertex access address according to a preset rule; and storing the target vertex access address and the control point attribute information corresponding to the target vertex access address into the flag cache unit.

[0075] For example, suppose a Quad includes 4 lanes, the reference access address is 0x1, and the vertex access address corresponding to the current Quad is [0x1, 0x1, 0x1, 0x2]. In this case, a miss is determined, that is, there is at least one vertex access address that is inconsistent with the reference access address.

[0076] When at least one vertex access address is inconsistent with the reference access address, the ILD needs to read the corresponding control point attribute information from VB based on each vertex access address. Then, the target vertex access address is determined, and the target vertex access address and the corresponding control point attribute information are stored in the flag buffer unit. The control point attribute information corresponding to each vertex access address is saved to the register file unit.

[0077] Optionally, the ILD determines the target access address from the access addresses of each vertex according to a preset rule. For example, the preset rule could be the access address of the control point corresponding to the last valid lane in each quad.

[0078] In the above embodiment, when at least one vertex access address is inconsistent with the reference access address, it indicates that the current Quad has not hit the control point attribute information in the flag cache unit, and the corresponding control point attribute information needs to be read from VB. Simultaneously, the target vertex access address is determined from the vertex access addresses, and the target vertex access address and its corresponding control point attribute information are stored in the flag cache unit. The control point attribute information corresponding to the vertex access address in the Quad is also saved to the register file unit, so that the control point attribute information for the same vertex access address can be quickly hit and reused in subsequent accesses.

[0079] Furthermore, in one embodiment, the above method further includes: when there is no reference access address in the flag cache unit, reading control point attribute information from the vertex cache unit according to the vertex access address; determining the target vertex access address from the vertex access address according to a preset rule; storing the target vertex access address and the control point attribute information corresponding to the target vertex access address in the flag cache unit, and saving the control point attribute information corresponding to the vertex access address in the Quad to the register file unit.

[0080] When there is no reference access address in check_buf, it indicates that the current vertex access address is the first access, and the corresponding control point attribute information has not yet been cached in the cache unit. Therefore, it is necessary to read the control point attribute information from the vertex cache unit.

[0081] After reading the control point access information, it is also necessary to save the target vertex access address and the corresponding control point attribute information. For details, please refer to the description in the above embodiments; further elaboration will not be repeated here.

[0082] In the above embodiment, when there is no reference access address in check_buf, it indicates that the current vertex access address is the first access. At this time, it is necessary to read the control point access information from VB and save the target vertex access address and the control point attribute information corresponding to the target vertex access address so that the control point attribute information of the same vertex access address can be quickly hit and reused in subsequent accesses.

[0083] Furthermore, in one embodiment, reading a reference access address from a flag cache unit and comparing each vertex access address with the reference access address includes: reading a detection flag from a flag detection unit; when the detection flag is valid, reading a reference access address from a flag cache unit and comparing each vertex access address with the reference access address.

[0084] Before the ILD reads the reference access address from check_buf, it needs to determine whether the cmp check detection flag is valid. If the detection flag is valid, it means that the flag detection unit is enabled, and only then will the reference access address be read from the flag buffer unit and compared with the reference access address.

[0085] In the above embodiment, the detection process will only be entered when the flag detection unit is in the enabled state, that is, the step of reading the reference access address and comparing the access address of each vertex with the reference access address.

[0086] In one exemplary embodiment, combined with Figure 6 , Figure 6 This is a schematic diagram of the structure of the input loading unit in an exemplary embodiment.

[0087] As mentioned above, the main function of DSW is to convert domain coordinates into vertex coordinates. Each lane in DSW processes one domain coordinate. To accomplish this, DSWC first sends the patch address (patchAddr) of the subdivision block containing the domain coordinates to the ILD unit. ILD stores this in ILD_BUF, a cache used to store the addresses of the attribute information required by HS, DS, and GS in the VB unit. cmp_check and check_buf are two newly added modules. The check_buf unit is a storage module that stores the VB_ADDR of the last valid lane in the last ILD request to VB and the 4-channel data of the control point attributes of the last lane returned by VB. The cmp_check unit is a comparison module used to check whether the VB_ADDR of the four lanes currently sent by ILD to VB is equal to the VB_ADDR stored in check_buf. When the VB_ADDR of the valid lanes out of the four lanes is not equal to the VB_ADDR in the check_buf for some lanes, the ILD first writes the VB_ADDR of the last valid lane out of the four lanes into the VB_ADDR location in the check_buf. Then, the ILD sends a read request to the VB. The VB retrieves the control point attribute information from the SRAM based on the VB_ADDR sent by the ILD and sends it back to the ILD. The ILD writes the 4-channel data of the last valid lane into the data location in the check_buf, and finally sends the data of the valid lanes to the RF for use when converting domain coordinates to vertices. When the VB_ADDR of the valid lanes out of the four lanes is equal to the VB_ADDR in the check_buf, the attribute data in the check_buf is copied to the valid lanes and the data is sent to the RF. In this case, no further read requests are sent to the VB, thus reducing the number of times the ILD reads the VB. Here, VB_ADDR is the vertex access address in the above embodiment.

[0088] In yet another exemplary embodiment, a flowchart of the steps of a data reading method in an embodiment is provided.

[0089] Step 1: Determine the current shader.

[0090] Specifically, it determines whether the current shader is a domain shader. The detection process is only followed if it is a domain shader; otherwise, the normal process is followed for other shader stages.

[0091] Step 2: Determine whether the detection mark of the mark detection unit is valid.

[0092] Optionally, the detection flag switch can be set to select between the detection process and the normal process. When the detection flag is on, the detection process begins; when the detection flag is off, the normal process is followed.

[0093] Step 3: Determine if the current ILD instruction is being accessed for the first time.

[0094] Specifically, the first access follows the normal process, and the VB_ADDR of the last valid lane in the Quad is saved in check_buf, as are the attribute data of the last valid lane returned by VB.

[0095] Step 4: Determine whether the vertex access addresses corresponding to each valid lane in the current quad are consistent with the reference access address. The reference access address is the VB_ADDR of the last valid lane in the previous quad.

[0096] Specifically, it checks whether the VB_ADDR of the current valid thread in the Quad is equal to the VB_ADDR previously stored in check_buf. If they are equal, ILD no longer sends read data requests for this Quad to VB, and copies the 4-channel attribute data previously recorded in check_buf to the valid thread in the current Quad; if they are not equal, the VB_ADDR in check_buf is replaced with the VB_ADDR of the last valid thread in the current Quad, and the data is updated to the 4-channel attribute data of the last valid thread read back by VB.

[0097] Step 5: Determine whether the current Quad is the last Quad of the instruction.

[0098] If the current Quad is not the last Quad, jump to Step 4; otherwise, the current instruction ends.

[0099] It should be noted that in this embodiment, the conventional process is followed, which involves reading the control point attribute information from VB.

[0100] In yet another exemplary embodiment, combined with Figure 7 , Figure 7 This is a schematic diagram of vertex access address checking in one embodiment.

[0101] In this embodiment, it can be understood as how the ILD unit processes a received ILD instruction. When the ILD unit determines that the current ILD instruction belongs to the domain shader and detects that the flag is enabled, the ILD unit calculates the VB_ADDR of the last valid lane of Quad0 as 0x1, stores 0x1 in the VB_ADDR location in the check_buf module, and then requests the attribute data of these 4V1E from the VB unit. There is a line in the figure connecting to the VB unit. When the ILD unit receives the attribute data returned by the VB unit, it writes the 4-channel data of the last valid thread into the data location in check_buf, and at the same time writes the attribute data returned by VB into RF.

[0102] When the ILD unit requests Quad1 data from the VB unit, the cmp_check module determines that the VB_ADDR of the valid lane in Quad1 and the value of VB_ADDR stored in the check_buf module are both 0x1. At this time, it is determined to be a hit. The ILD unit no longer requests Quad1 data from the VB unit, but instead copies all the 4 channels of data in the data in the check_buf module to the four valid lanes in Quad1. These data are then written to the RF unit. As can be seen in the figure, the data stream of Quad1 is disconnected from the VB unit.

[0103] When the ILD unit requests Quad2 data from the VB unit, the cmp_check module detects that the VB_ADDR values ​​of the valid lanes in Quad2 are not the same as those stored in the check_buf module. The VB_ADDR of the first lane in Quad2 is 0x1, while the others are 0x2, resulting in a data miss. At this point, the VB_ADDR value in the check_buf module is updated to 0x2, representing the VB_ADDR of the last valid lane in Quad2. Then, a read attribute data request is sent to the VB unit, and the 4-channel data of the last valid lane in Quad2, returned by the VB unit, is written to the data location in the check_buf module.

[0104] When the ILD unit requests Quad3 data from the VB unit, the process is the same as when processing Quad2. Since the VB_ADDR of the valid lane in Quad3 is not exactly the same as the value 0x2 stored in VB_ADDR in check_buf, it will be judged as a miss by the cmp_check module. At this time, VB_ADDR in check_buf will be replaced with 0x4, and then a read attribute data request will be sent to VB.

[0105] When the ILD unit requests Quad4 data from the VB unit, the process is the same as when processing Quad1. Since the VB_ADDR field check_buf of the valid lane in Quad4 contains 0x4, the cmp_check module determines it as a hit and no longer sends a read request to VB.

[0106] When the ILD unit requests Quad5 data from the VB unit, the process is the same as when processing Quad2. Since the VB_ADDR of the valid lane in Quad5 is not exactly the same as the value 0x4 stored in VB_ADDR in check_buf, it will be judged as a miss by the cmp_check module. At this time, VB_ADDR in check_buf will be replaced with 0x5, and then a read attribute data request will be sent to VB.

[0107] When the ILD unit requests Quad6 data from the VB unit, the process is the same as when processing Quad1. Since the VB_ADDR field check_buf of the valid lane in Quad6 contains 0x5, the cmp_check module determines it as a hit and no longer sends a read request to VB.

[0108] When the ILD unit requests data for Quad7 from the VB unit, since there is no valid lane in Quad7, Quad7 is not functioning and no operation is performed on it.

[0109] After adding the `check_buf` and `cmp_check` submodules to the ILD unit, the number of requests sent to the VB unit was reduced from 7 to 4. In practice, VB_ADDR in multiple consecutive quads may often be the same, which further reduces the number of reads from the VB unit. Therefore, adding detection technology to the ILD unit can effectively reduce the number of read requests sent from the ILD unit to the VB unit, speed up the execution of DSW, and alleviate the read pressure on the VB unit.

[0110] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0111] Based on the same inventive concept, this application also provides a data reading device for implementing the data reading method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more data reading device embodiments provided below can be found in the limitations of the data reading method described above, and will not be repeated here.

[0112] In one exemplary embodiment, such as Figure 8 As shown, a data reading device is provided, including: a receiving module 100, an address calculation module 200, a comparison module 300, a reading module 400, and a return module 500, wherein:

[0113] The receiving module 100 is used to receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request.

[0114] The address calculation module 200 is used to calculate the vertex access address corresponding to each control point access request.

[0115] The comparison module 300 is used to read the reference access address from the flag cache unit and compare the access address of each vertex with the reference access address.

[0116] The reading module 400 is used to read control point attribute information from the flag cache unit when the access addresses of each vertex are equal and consistent with the reference access address.

[0117] Return module 500 is used to return control point attribute information to the register file unit.

[0118] In one embodiment, the data loading instruction in the above device carries a control point access request corresponding to the current channel group; the reference access address is the target vertex access address corresponding to the previous channel group; and the target vertex access address is obtained from the vertex access address corresponding to the channel group according to a preset rule.

[0119] In one embodiment, the above-described apparatus further includes a first storage module, the first storage module comprising:

[0120] The first address determination unit is used to read control point attribute information from the vertex cache unit based on the vertex access address when at least one vertex access address is inconsistent with the reference access address.

[0121] The first address determination unit is used to determine the target vertex access address from the vertex access address according to preset rules.

[0122] The first information storage unit is used to store the target vertex access address and the control point attribute information corresponding to the target vertex access address into the flag cache unit.

[0123] In one embodiment, the above-described apparatus further includes a second storage module, the second storage module comprising:

[0124] The second address determination unit is used to read control point attribute information from the vertex cache unit based on the vertex access address when there is no reference access address in the flag cache unit.

[0125] The second address determination unit is used to determine the target vertex access address from the vertex access address according to preset rules.

[0126] The second information storage unit is used to store the target vertex access address and the control point attribute information corresponding to the target vertex access address into the flag cache unit.

[0127] In one embodiment, the comparison module includes:

[0128] The flag reading unit is used to read the detection flags from the flag detection unit.

[0129] The address comparison unit is used to read the reference access address from the flag cache unit when the detection flag is valid, and compare the access address of each vertex with the reference access address.

[0130] In one embodiment, the data loading instruction in the above-described device is generated by the domain shader after determining the target control point based on the domain coordinates sent by the hardware subdivision unit, and then the control point access request is grouped and sent.

[0131] Each module in the aforementioned data reading device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0132] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores control point attribute information. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a data reading method.

[0133] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0134] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0135] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0136] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0137] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0138] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0139] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data reading method, characterized in that, The method includes: Receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request. Calculate the vertex access address corresponding to each of the control point access requests; Read the reference access address from the flag cache unit, and compare each vertex access address with the reference access address; When the access addresses of all the vertices are equal and consistent with the reference access address, the control point attribute information is read from the flag cache unit; The control point attribute information is returned to the register file unit.

2. The method according to claim 1, characterized in that, The data loading instruction carries a control point access request corresponding to the current channel group. The reference access address is the target vertex access address corresponding to the channel group mentioned above; the target vertex access address is obtained from the vertex access address corresponding to the channel group mentioned above according to a preset rule.

3. The method according to claim 2, characterized in that, The method further includes: When at least one of the vertex access addresses is inconsistent with the reference access address, the control point attribute information is read from the vertex cache unit according to the vertex access address; The target vertex access address is determined from the vertex access address according to the preset rules; The target vertex access address and the corresponding control point attribute information are stored in the flag cache unit, and the control point attribute information is returned to the register file unit.

4. The method according to claim 2, characterized in that, The method further includes: When the reference access address is not present in the flag cache unit, the control point attribute information is read from the vertex cache unit according to the vertex access address; The target vertex access address is determined from the vertex access address according to the preset rules; The target vertex access address and the corresponding control point attribute information are stored in the flag cache unit, and the control point attribute information corresponding to the vertex access address is returned to the register file unit.

5. The method according to claim 1, characterized in that, The step of reading the reference access address from the flag cache unit and comparing each vertex access address with the reference access address includes: Read the detection mark of the mark detection unit; When the detection flag is valid, the reference access address is read from the flag cache unit, and the access addresses of each vertex are compared with the reference access address.

6. The method according to claim 1, characterized in that, The data loading instruction is generated by the domain shader after determining the target control point based on the domain coordinates sent by the hardware subdivision unit, generating the control point access request based on the target control point, and then sending the control point access request in groups.

7. A data reading device, characterized in that, The device includes: The receiving module is used to receive a data loading instruction sent by the domain shader; the data loading instruction carries at least one control point access request. The address calculation module is used to calculate the vertex access address corresponding to each control point access request; The comparison module is used to read the reference access address from the flag cache unit and compare each vertex access address with the reference access address; The reading module is used to read control point attribute information from the flag cache unit when the access addresses of each vertex are equal and consistent with the reference access address; The return module is used to return the control point attribute information to the register file unit.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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