单比特数据延迟仿真处理系统
By setting delay simulation modules in the input, metastability detection, and output transmission paths of single-bit data, the problem of not introducing delay information in front-end simulation is solved, enabling the discovery of design defects at the front end and improving chip development efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-07-17
AI Technical Summary
In the chip development process, existing technologies have failed to effectively incorporate latency information during front-end simulation, which affects development efficiency when problems are discovered in the back-end design and makes it difficult to detect design defects as early as possible.
Delay simulation modules are set up in the input, metastability detection and output transmission paths of single-bit data respectively. By randomly generating delay values for simulation, delay information is introduced in the front-end simulation stage to discover potential problems.
By introducing latency information during the front-end simulation stage, problems in chip design can be detected as early as possible, improving chip development efficiency and ensuring the consistency and accuracy of back-end design.
Smart Images
Figure CN122133576B_ABST