Device model establishment method and device based on three-dimensional integration process

Abstract

This invention provides a method and apparatus for establishing a device model based on three-dimensional integrated circuit technology. The method includes: determining two-dimensional and three-dimensional process information based on the product requirements of the three-dimensional integrated circuit; determining the critical dimensions of the test structure based on the two-dimensional and three-dimensional process information; designing the test structure for the device based on the three-dimensional integrated circuit technology; fabricating the test structure using both two-dimensional and three-dimensional processes, and performing data testing and data collection on the fabricated test structure; and using the collected data to establish a device model based on the three-dimensional integrated circuit technology. This invention enables customized modeling of device variations caused by three-dimensional integrated circuits, thereby improving circuit simulation accuracy and reducing the risk of affecting product yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method and apparatus for establishing device models based on three-dimensional integrated circuit technology. Background Technology

[0002] As integrated circuit manufacturing technology continues to evolve, the integration density of chips is constantly increasing with the miniaturization of device and interconnect dimensions. However, as integrated circuit processes advance to 7nm and below, traditional silicon processes are gradually reaching their limits, making it increasingly difficult to improve integration density through size reduction. Therefore, in the post-Moore's Law era, the improvement of chip integration density cannot be achieved through simple size reduction. Three-dimensional integrated circuits (3DIC) have become the key to solving this problem and are currently the focus of industry research.

[0003] 3D integration is mainly achieved through key technologies such as through silicon via (TSV) and hybrid bonding. By vertically stacking, interconnects are shortened, chip transmission speed is increased, and power consumption is reduced.

[0004] Through-Silicon Vias (TSVs) are a process that penetrates through silicon, inevitably affecting the performance of front-end-of-line (FEOL) transistors. The primary impact stems from the metal filling of the TSVs (currently mainly Cu processes). The significant mismatch in thermal expansion coefficients between the metal and silicon leads to thermal stress during the process, causing performance variations. Furthermore, the geometric differences between the device and the TSV further exacerbate these performance variations. Accurate modeling of device electrical performance is crucial for integrated circuit design, especially for analog circuits. Failure to accurately model these performance variations resulting from three-dimensional integration will negatively impact product success.

[0005] Currently, the SPICE (Simulation Program with Integrated Circuit Emphasis) model of MOS (Metal-Oxide-Semiconductor) field-effect transistors is constructed based on the electrical performance of the device in two-dimensional integrated circuit (2DIC) technology, using BSIM4 / BSIM_Bulk / BSIM_CMG (BSIM: Berkeley Short-channel IGFET Model), and the constructed SPICE model is provided to circuit designers for simulation design.

[0006] Currently, we have entered the 3DIC scenario. The existing SPICE model of MOS field-effect transistor is only applicable to 2DIC application scenarios and cannot be applied to 3DIC application scenarios. This may lead to a mismatch between the MOS field-effect transistor model and the actual electrical behavior of the device, which may affect the product yield. Summary of the Invention

[0007] The device modeling method, apparatus, and computer-readable storage medium based on three-dimensional integrated circuit technology provided by this invention can perform customized modeling of device variations caused by three-dimensional integrated circuits, thereby improving circuit simulation accuracy and reducing the risk of affecting product yield.

[0008] In a first aspect, the present invention provides a method for establishing a device model based on three-dimensional integrated technology, the method comprising:

[0009] Based on the product requirements of 3D integrated circuits, determine the 2D and 3D process information; Based on the aforementioned two-dimensional and three-dimensional process information, the key dimensions of the test structure are determined. Design test structures for devices based on three-dimensional integrated circuit technology; The test structure is fabricated using two-dimensional and three-dimensional processes, and data testing and data collection are performed on the fabricated test structure. Using the collected data, a device model based on three-dimensional integrated circuit technology is established.

[0010] Optionally, determining the key dimensions of the test structure based on the two-dimensional and three-dimensional process information includes: The lower boundary of the critical dimension of the test structure is determined based on two-dimensional and three-dimensional process design rules. The upper boundary of the critical dimensions of the test structure was determined by simulation based on computer-aided design technology.

[0011] Optionally, the overall layout of the test structure is determined by both two-dimensional and three-dimensional process information; wherein, the through-silicon via (TSV) size information is determined by the three-dimensional process information, and the transistor size information is determined by the two-dimensional process information.

[0012] Optionally, the data testing and data collection on the completed test structure includes: collecting Itsvx / dtsvy data under different device types and sizes, at different temperatures, and with different device sizes. d -V g Curve, I d- V dThe curves are Cgg and Cgc; where dtsvx represents the distance in the X direction between the center of the transistor and the center of the through-silicon via (TSV), dtsvy represents the distance in the Y direction between the center of the transistor and the center of the TSV, and I... d -V g The curve represents the situation with a fixed drain-source voltage V. D Drain-source current I d With gate-source voltage V g Changing curve, I d- V d The curve represents the situation with a fixed gate-source voltage V. G Drain-source current I d The curves show how the drain-source voltage Vd changes, where Cgg represents the capacitance between the gate and the source, and Cgc represents the capacitance between the gate and the drain.

[0013] Optionally, the step of using the collected data to establish a device model based on three-dimensional integrated circuit technology includes: Obtain the first model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx and gate length at the nominal temperature, the second model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy and gate length, the third model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx and fin number or nanosheet width, and the fourth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy and fin number or nanosheet width. The original parameter function of the device model under the two-dimensional process is added to the parameter variation functions of the first model, the second model, the third model, and the fourth model to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0014] Optionally, the step of using the collected data to establish a device model based on three-dimensional integrated circuit technology further includes: Obtain the fifth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx with gate length and fin number or nanosheet width at the nominal temperature, and the sixth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy with gate length and fin number or nanosheet width. The original parameter function of the device model under the two-dimensional process is added to the parameter variation functions of the first model, the second model, the third model, the fourth model, the fifth model, and the sixth model to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0015] Optionally, the step of using the collected data to establish a device model based on three-dimensional integrated circuit technology further includes: Obtain the temperature change function at other temperatures and the nominal temperature; The customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature is added to the temperature change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at other temperatures.

[0016] Secondly, the present invention provides a device for establishing a device model based on three-dimensional integrated circuit technology, the device comprising: The first determining unit is used to determine the two-dimensional process information and the three-dimensional process information based on the product requirements of the three-dimensional integrated circuit. The second determining unit is used to determine the key dimensions of the test structure based on the two-dimensional process information and the three-dimensional process information. Design unit, used for designing test structures for devices based on three-dimensional integrated circuit technology; The data testing and collection unit is used to perform two-dimensional and three-dimensional fabrication of the test structure, and to perform data testing and data collection on the completed test structure. The model building unit is used to build a device model based on three-dimensional integrated circuit technology using the data collected by the data testing and collection unit.

[0017] Optionally, the second determining unit includes: The first determination module is used to determine the lower boundary of the critical dimension of the test structure based on two-dimensional process design rules and three-dimensional process design rules. The second determination module is used to determine the upper boundary of the critical dimensions of the test structure based on computer-aided design technology simulation.

[0018] Optionally, the overall layout of the test structure is determined by both two-dimensional and three-dimensional process information; wherein, the through-silicon via (TSV) size information is determined by the three-dimensional process information, and the transistor size information is determined by the two-dimensional process information.

[0019] Optionally, the data testing and data collection on the completed test structure includes: collecting Itsvx / dtsvy data under different device types and sizes, at different temperatures, and with different device sizes. d -V g Curve, I d- V d The curves are Cgg and Cgc; where dtsvx represents the distance in the X direction between the center of the transistor and the center of the through-silicon via (TSV), dtsvy represents the distance in the Y direction between the center of the transistor and the center of the TSV, and I... d -V gThe curve represents the situation with a fixed drain-source voltage V. D Drain-source current I d With gate-source voltage V g Changing curve, I d- V d The curve represents the situation with a fixed gate-source voltage V. G Drain-source current I d The curves show how the drain-source voltage Vd changes, where Cgg represents the capacitance between the gate and the source, and Cgc represents the capacitance between the gate and the drain.

[0020] Optionally, the model building unit includes: The first acquisition module is used to acquire the first model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and gate length at the nominal temperature, the second model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and gate length, the third model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and fin number or nanosheet width, and the fourth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and fin number or nanosheet width. The function creation module is used to add the original parameter function of the device model under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function and the fourth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0021] Optionally, the model building unit further includes: The second acquisition module is used to acquire the fifth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx with gate length and fin number or nanosheet width at the nominal temperature, and the sixth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy with gate length and fin number or nanosheet width. The function establishment module is further used to add the original function of the device model parameters under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function, the fourth model parameter change function, the fifth model parameter change function and the sixth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0022] Optionally, the model building unit further includes: The third acquisition module is used to acquire the temperature change function between other temperatures and the nominal temperature; The function establishment module is further used to add the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature to the temperature change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at other temperatures.

[0023] Thirdly, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the above-described method for establishing a device model based on three-dimensional integrated technology.

[0024] The present invention provides a method, apparatus, and computer-readable storage medium for establishing device models based on three-dimensional integrated circuit technology. After determining the critical dimensions of the test structure based on two-dimensional and three-dimensional process information, a test structure for the device based on three-dimensional integrated circuit technology is designed. The test structure is then fabricated using both two-dimensional and three-dimensional processes. Data testing and data collection are performed on the fabricated test structure. Using the collected data, a device model based on three-dimensional integrated circuit technology is established. Since the data collected after testing the test structure includes parameters related to device variation, customized modeling of device variations caused by three-dimensional integrated circuits can be performed, thereby improving circuit simulation accuracy and reducing the risk of affecting product yield. Attached Figure Description

[0025] Figure 1 This is a flowchart of a device model establishment method based on three-dimensional integrated technology according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a device model building apparatus based on three-dimensional integrated technology according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] This invention provides a method for establishing a device model based on three-dimensional integrated circuit technology, such as... Figure 1 As shown, the method includes: S11. Based on the product requirements of three-dimensional integrated circuits, determine the two-dimensional process information and the three-dimensional process information.

[0028] S12. Based on the two-dimensional and three-dimensional process information, determine the key dimensions of the test structure.

[0029] S13. Design the test structure for devices based on three-dimensional integrated circuit technology.

[0030] S14. Perform two-dimensional and three-dimensional fabrication of the test structure, and conduct data testing and data collection on the completed test structure.

[0031] S15. Using the collected data, establish a device model based on three-dimensional integrated circuit technology.

[0032] The device model establishment method based on three-dimensional integrated circuit technology provided in this invention determines the key dimensions of the test structure based on two-dimensional and three-dimensional process information, designs the test structure of the device based on three-dimensional integrated circuit technology, and performs two-dimensional and three-dimensional process fabrication of the test structure. Data testing and data collection are performed on the fabricated test structure. Using the collected data, a device model based on three-dimensional integrated circuit technology is established. Since the data collected after data testing of the test structure includes parameters related to device variation, it is possible to perform customized modeling of device variation caused by three-dimensional integrated circuits, thereby improving the accuracy of circuit simulation and reducing the risk of affecting product yield.

[0033] The following section uses a MOS field-effect transistor as an example to describe in detail the device model establishment method based on three-dimensional integrated technology of the present invention.

[0034] The device model establishment method based on three-dimensional integrated technology provided in this embodiment includes the following steps: S21. Based on the product requirements of three-dimensional integrated circuits, determine the two-dimensional process information and the three-dimensional process information.

[0035] The two-dimensional and three-dimensional process information mainly includes process design rules.

[0036] S22. Based on the two-dimensional and three-dimensional process information, determine the key dimensions of the test structure (Testkey).

[0037] The determination of the key dimensions of the test structure (Testkey) based on the two-dimensional and three-dimensional process information specifically includes: The lower boundary of the critical dimension of the test structure is determined based on two-dimensional and three-dimensional process design rules. The upper boundary of the critical dimensions of the test structure was determined based on TCAD (Technology Computer-Aided Design) simulation.

[0038] S23. Design a test structure for a MOS field-effect transistor based on three-dimensional integrated circuit technology.

[0039] The layout of the overall test structure for MOS field-effect transistors is determined by both 2D and 3D process information. Specifically, the through-silicon via (TSV) dimensions are determined by the 3D process, while the transistor dimensions are determined by the 2D process. For FinFETs (Fin Field-Effect Transistors), the transistor dimensions include different device types / gate lengths (L...). gate ) and / or number of fins (nfin); for NS-GAA (nanosheet full-ring gate), transistor size information includes different device types / gate length / nanosheet width (NSW).

[0040] The test structure includes a MOS field-effect transistor array. The lower boundaries of its dtsvx (distance between the center of the transistor and the center of the through-silicon via in the X direction) and dtsvy (distance between the center of the transistor and the center of the through-silicon via in the Y direction) are defined by the design rules of both 2D and 3D processes. Considering the high integration requirements, dtsvx and dtsvy should be as small as possible. The upper boundaries of dtsvx and dtsvy are determined by TCAD simulation. The input of TCAD simulation is relevant information of 2D and 3D processes, and the output is the change of device electrical performance with dtsvx and dtsvy. The upper boundaries are dtsvx and dtsvy when the change of the device electrical performance threshold voltage Vth / saturation current Idsat with dtsvx and dtsvy is less than 3mV / 0.5%.

[0041] Optionally, considering the possible differences between TCAD simulation and actual process results, the final upper boundary of dtsvx and dtsvy can be increased by 10% to 30% based on the upper boundary of TCAD simulation.

[0042] The test structure includes a through-silicon via (TSV) array, with a MOS field-effect transistor array positioned around the effective TSVs, and the remaining TSVs in the TSV array serving as pseudo TSVs.

[0043] S24. Perform two-dimensional and three-dimensional fabrication of the test structure, and conduct data testing and data collection on the completed test structure.

[0044] After completing the design of the MOS field-effect transistor test structure based on 3D integrated technology, 2D and 3D fabrication processes were performed. Data testing and data collection were then conducted on the fabricated test structure. Specifically, data collection included: The collection includes different dtsvx, dtsvy, MOS transistor device types, and MOS transistor device sizes (FinFET: L). gate and nfin; GAA: L gate Data from (and NSW); Collect temperature data including ambient temperature, low temperature, and high temperature (e.g., -40℃, 0℃, 25℃, 85℃, 125℃); Collect MOS field-effect transistors at a fixed drain-source voltage (V D Under these conditions, the drain-source current (I) d ) with gate-source voltage (V g The changing curve, i.e., I d -V g Curve. For example: V D =0.05V, 1 / 2 Vdd, and Vdd; where Vdd is the chip's operating voltage; Collect MOS field-effect transistors at a fixed gate-source voltage (V G Under these conditions, the drain-source current (I) d ) with drain-source voltage (V d The changing curve, i.e., I d -V d Curve. For example: V G =0V, 1 / 4 Vdd, 1 / 2 Vdd, 3 / 4 Vdd and Vdd; Collect the capacitance curves Cgg between the gate and source of the MOS field-effect transistor and the capacitance curves Cgc between the gate and drain.

[0045] Finally, data collection was completed, and a series of I values ​​were obtained for different MOS field-effect transistor device types and sizes, at different temperatures, and with different dtsvx / dtsvy ratios. d -V g Curve, I d- V d Curve, Cgg and Cgc curve.

[0046] For circuit design, especially analog circuit design, the key electrical performance parameters of MOS field-effect transistors mainly include Vth (threshold voltage), Idlin (characteristic current in the linear region), Idsat (characteristic current in the saturation region), Idoff (characteristic leakage current at the drain), gm (characteristic transconductance), and rO (characteristic output resistance).

[0047] By extracting the test data obtained above, these key electrical performance parameters can be obtained.

[0048] S25. Using the collected data, establish a SPICE model of a MOS field-effect transistor based on three-dimensional integrated circuit technology.

[0049] Taking FinFET as an example, the performance variation of MOS devices caused by three-dimensional integration process is mainly affected by dtsvx, dtsvy, device type, and gate length (L). gate The coupling effect of the number of fins (nfin) and the number of fins.

[0050] For NS-GAA, replace the number of fins (nfin) with the nanosheet width (NSW).

[0051] At nominal temperature, the customized parameter functions of the SPICE model of the MOS field-effect transistor based on three-dimensional integrated technology are obtained as follows: Obtaining the reflection of dtsvx and L gate The first model parameter change function f(dtsvx, L) for device performance variation caused by coupling effects gate ); Obtain the reflection of dtsvy and L gate The second model parameter variation function f(dtsvy, L) for device performance variation caused by coupling effects gate ); Obtain the third model parameter variation function f(dtsvx, nfin) that reflects the device performance variation caused by the coupling effect between dtsvx and nfin; Obtain the fourth model parameter variation function f(dtsvy, nfin) that reflects the device performance variation caused by the coupling effect between dtsvy and nfin; The customized parameter function for the SPICE model of the MOS field-effect transistor based on three-dimensional integrated technology is as follows: F = f(2D origin) + f(dtsvx, L) gate )+f(dtsvy, L gate )+f(dtsvx, nfin)+f(dtsvy,nfin); Where f(2D origin) is the original function of the two-dimensional process MOS device model parameters.

[0052] Optionally, to improve model fit, data reflecting the relationship between dtsvx and L can also be obtained. gate The fifth model parameter variation function f(dtsvx, L) for device performance variation caused by coupling with nfin. gate , nfin), and reflect dtsvy and L gate The sixth model parameter variation function f(dtsvy, L) for device performance variation caused by coupling with nfin. gate , nfin); The customized parameter function for the SPICE model of the MOS field-effect transistor based on three-dimensional integrated technology is as follows: F = f(2D origin) + f(dtsvx, L) gate )+f(dtsvy, L gate)+f(dtsvx, nfin)+f(dtsvy,nfin)+f(dtsvx, L gate , nfin)+f(dtsvy, L gate (, nfin).

[0053] Furthermore, at other temperatures, the customized parameter function of the SPICE model for the MOS field-effect transistor based on the three-dimensional integrated process can be based on the customized parameter function of the SPICE model at the nominal temperature, plus the temperature variation function f(T / T) between the nominal and other temperatures. NOM ).

[0054] Through the customized development of SPICE models for MOS field-effect transistors using 3DIC technology, a high degree of fit between the customized SPICE model simulation data and test data was ultimately achieved.

[0055] The following is an example of establishing a customized model for a MOS field-effect transistor using the 3DIC process.

[0056] (1) Threshold voltage V th (V) thnom ): Using large L gate / CV curves (capacitor-voltage characteristic curves) for different dtsvx and dtsvy under large nfin conditions are used to obtain V FB (Flat band voltage) offset, new function fV FB (dtsvx, L gate ), fV FB (dtsvy, L gate ), fV FB (dtsvx,nfin) and fV FB (dtsvy, nfin), due to the current large L gate With a fixed nfin, the model V is adjusted by modifying four functions. FB Offset ΔV FB,3D Consistent with test data: ΔV FB,3D =fV FB (dtsvx, L gate )+fV FB (dtsvy, L gate )+fV FB (dtsvx, nfin)+fV FB (dtsvy,nfin); Using L gate V is obtained from the CV curves of different dtsvx and different dtsvy under large nfin, from large to small. FBThe offset is adjusted by fV. FB (dtsvx, L gate ), fV FB (dtsvy, L gate ), making model V FB The offset matches the test data; Using large L gate V is obtained by using CV curves with different dtsvx and dtsvy values ​​from largest to smallest using nfin. FB The offset is adjusted by fV. FB (dtsvx, nfin), fV FB (dtsvy, nfin) makes model V FB The offset matches the test data; Verify L gate V under different dtsvx and different dtsvy values ​​from largest to smallest, and nfin from largest to smallest. FB Offset and corresponding model ΔV FB Does it match (<3mV)? If it matches, then ΔV FB,3D The parameter model customization is complete. If any issues arise, several coupling functions will be added, fV FB (dtsvx, L gate (, nfin) and fV FB (dtsvy, L gate (, nfin) and adjust it to finally meet the requirements, at this time ΔV FB,3D =fV FB (dtsvx, L gate )+fV FB (dtsvy, L gate )+fV FB (dtsvx, nfin)+fV FB (dtsvy,nfin)+fV FB (dtsvx, L gate , nfin)+fV FB (dtsvy, L gate , nfin); Threshold voltage V th0 =V FB +ψS+(Q is +Q bs ) / Cox; The threshold voltage V at the nominal temperature of the customized model th0,3D =V FB +ΔV FB,3D +ψS+(Q is +Q bs) / Cox; Threshold voltage V at nominal temperature th (V thnom )=V th0,3D +ΔV th,2D ; Among them, V FB Let Q be the flat-band voltage, ψS be the surface potential, and Q be the voltage across the flat band. is Q is the interface charge density. bs Where V is the volume charge density, Cox is the gate oxide capacitance, and ΔV is the voltage density. th,2D Other factors that cause changes in the threshold voltage of 2D processes include SCE (short channel effect) and DIBL (drain-induced barrier reduction).

[0057] Using L at different temperatures gate V is obtained by using CV curves with different dtsvx and dtsvy values ​​from largest to smallest and from largest to smallest using nfin. FB Offset, based on each temperature V FB The offset is increased by fV. FB,3D (T / T nom The function is used to compensate for the effect of 3D processing on the temperature effect of the threshold voltage of MOS transistors; finally, the threshold voltage V at each temperature is obtained. th,3D =V th0,3D +ΔV th,2D +fV FB,3D (T / T nom ).

[0058] (2) Output current characteristics with low drain-end electric field: Using large L gate / I under different dtsvx and different dtsvy under big nfin d -V g The curve obtains the Idlin (linear region current) offset. Considering the impact of 3D processing on low field mobility, a new function fμ0(dtsvx, L) is added. gate ), fμ0(dtsvy, L gate ), fμ0(dtsvx, nfin), fμ0(dtsvy, nfin), because the current large L gate With nfin fixed, substitute the already completed 3DIC threshold voltage V. th,3D The customized model, by adjusting four newly added mobility functions, makes the Idlin offset of the model match the test data. The mobility change is as follows: Δμ0 3D =fμ0(dtsvx, L gate )+fμ0(dtsvy, L gate )+fμ0(dtsvx, nfin)+fμ0(dtsvy,nfin); Using L gate From largest to smallest, I under different dtsvx and different dtsvy under large nfin d -V g The Idlin offset is obtained by adjusting fμ0(dtsvx, L) gate ), fμ0(dtsvy, L gate This ensures that the Idlin offset of the model matches the test data; Using large L gate , nfin from largest to smallest I for different dtsvx and different dtsvy d -V g The Idlin offset is obtained by curves. By adjusting fμ0(dtsvx, nfin) and fμ0(dtsvy, nfin), the Idlin offset of the model is made to match the test data. Verify whether the Idlin offsets for different dtsvx and dtsvy under Lgate (from largest to smallest) and nfin (from largest to smallest) are consistent with the corresponding model ΔIdlin (<0.5%). If they are consistent, then Δμ0 3D The parameter model customization is complete. If any issues arise, several coupling functions will be added, such as fμ0(dtsvx, L). gate , nfin) and fμ0(dtsvy, L gate (, nfin) and adjust it to finally meet the requirements, at this time Δμ0 3D =fμ0(dtsvx, L gate )+fμ0(dtsvy, L gate )+fμ0(dtsvx, nfin)+fμ0(dtsvy,nfin)+fμ0(dtsvx, L gate , nfin)+fμ0(dtsvy, L gate , nfin); Using L at different temperatures gate From largest to smallest, nfin from largest to smallest, I for different dtsvx and different dtsvy d -V g Obtain the Idlin offset from the curve and substitute it into the completed 3DIC threshold voltage V. th,3D A customized model, with fμ0 added based on the Idlin offset at each temperature. 3D (T / T nom The function is used to compensate for the impact of 3D processing on the output current of MOS transistors under low drain electric field; finally, the low-field carrier mobility μ0 is obtained at various temperatures. 3D =μ0 2D +Δμ03D +fμ0 3D (T / T nom ).

[0059] (3) Output current characteristics with high drain-end electric field: Using large L gate / I under different dtsvx and different dtsvy under big nfin d -V g The curve obtains the Idsat (saturated drain current) offset. Considering the impact of 3D processing on the high-field carrier saturation velocity, a new function fvsat(dtsvx, L) is added. gate ), fvsat(dtsvy, L gate ), fvsat(dtsvx, nfin), fvsat(dtsvy, nfin), because the current large L gate With nfin fixed, substitute the already completed 3DIC threshold voltage V. th,3D and μ0 3D The customized model, by adjusting four newly added saturation velocity functions, makes the model's Idsat offset consistent with the test data, and the mobility change is: Δvsat 3D =fvsat(dtsvx, L gate )+fvsat(dtsvy, L gate )+fvsat(dtsvx, nfin)+fvsat(dtsvy, nfin); Using L gate From largest to smallest, I under different dtsvx and different dtsvy under large nfin d -V g The Idsat offset is obtained from the curve by adjusting fvsat(dtsvx, L gate ), fvsat(dtsvy, L gate This ensures that the model's Idsat offset matches the test data; Using large L gate , nfin from largest to smallest I for different dtsvx and different dtsvy d -V g The Idsat offset is obtained from the curve. By adjusting fvsat(dtsvx, nfin) and fvsat(dtsvy, nfin), the Idsat offset of the model is made to match the test data. Verify L gate Check if the Idsat offsets for different dtsvx and dtsvy values ​​under varying nfin values ​​(from largest to smallest) match the corresponding model ΔIdsat (<0.5%). If they all match, then Δvsat...3D The parameter model customization is complete. If any issues arise, several coupling functions will be added, such as fvsat(dtsvx, L gate , nfin) and fvsat(dtsvy, L gate (, nfin) and adjust it to finally meet the requirements, at this time Δvsat 3D =fvsat(dtsvx, L gate )+fvsat(dtsvy, L gate )+fvsat(dtsvx, nfin)+fvsat(dtsvy, nfin)+fvsat(dtsvx, L gate , nfin)+fvsat(dtsvy, L gate , nfin); Using L at different temperatures gate From largest to smallest, nfin from largest to smallest, I for different dtsvx and different dtsvy d -V g Obtain the Idsat offset from the curve and substitute it into the completed 3DIC threshold voltage V. th,3D and μ0 3D A customized model, with fvsat added based on the Idsat offset for each temperature. 3D (T / T nom The function is used to compensate for the impact of 3D processing on the output current of MOS transistors under high drain electric field; finally, the carrier saturation velocity under high drain electric field at various temperatures is obtained as vsat. 3D =vsat 2D +Δvsat 3D +fvsat 3D (T / T nom ).

[0060] Finally, I was tested under various temperatures and conditions. d -V g Curve and I d -V d Curve calibration optimization, specifically: Substitute the already completed 3DIC threshold voltage V th,3D μ0 3D and vsat 3D A customized model was developed, and the differences between the 3DIC model and test data were compared. Emphasis was placed on parameters such as Idoff (characteristic drain current), gm (characteristic transconductance), and rO (characteristic output resistance). The customized model parameters were added and adjusted using the aforementioned 3D parameter addition method, ensuring that the customized 3DIC model was compatible with Idoff under various temperatures and test conditions. d -Vg Curve and I d -V d The curves match; if discrepancies exist, a customized model optimization can be achieved by adding terms such as carrier mobility degradation caused by 3DIC, leakage-induced barrier reduction effect, and subthreshold swing. The steps are the same as for V. th,3D μ0 3D vsat 3D Consistency was achieved, and the customized SPICE model was finally completed.

[0061] S26. Use the established SPICE model to design a three-dimensional integrated circuit.

[0062] The device model establishment method based on three-dimensional integrated process provided in this invention can realize customized modeling of the variation of MOS field-effect transistor device caused by three-dimensional integrated process, achieve better model accuracy, thereby improving circuit simulation accuracy and reducing the risk of affecting product yield.

[0063] This invention also provides a device for building a device model based on three-dimensional integrated circuit technology, such as... Figure 2 As shown, the device includes: The first determining unit 11 is used to determine the two-dimensional process information and the three-dimensional process information based on the product requirements of the three-dimensional integrated circuit. The second determining unit 12 is used to determine the key dimensions of the test structure based on the two-dimensional process information and the three-dimensional process information. Design unit 13 is used for designing test structures for devices based on three-dimensional integrated circuit technology; The data testing and collection unit 14 is used to perform two-dimensional and three-dimensional fabrication of the test structure, and to perform data testing and data collection on the completed test structure. The model building unit 15 is used to build a device model based on three-dimensional integrated circuit technology using the data collected by the data testing and collection unit.

[0064] The device model building apparatus based on three-dimensional integrated circuit technology provided in this embodiment of the invention determines the key dimensions of the test structure based on two-dimensional and three-dimensional process information, designs the test structure of the device based on three-dimensional integrated circuit technology, and performs two-dimensional and three-dimensional process fabrication of the test structure. Data testing and data collection are performed on the fabricated test structure, and the collected data is used to build a device model based on three-dimensional integrated circuit technology. Since the data collected after data testing of the test structure includes parameters related to device variation, it is possible to perform customized modeling of device variation caused by three-dimensional integrated circuits, thereby improving the accuracy of circuit simulation and reducing the risk of affecting product yield.

[0065] Optionally, the second determining unit 12 includes: The first determination module is used to determine the lower boundary of the critical dimension of the test structure based on two-dimensional process design rules and three-dimensional process design rules. The second determination module is used to determine the upper boundary of the critical dimensions of the test structure based on computer-aided design technology simulation.

[0066] Optionally, the overall layout of the test structure is determined by both two-dimensional and three-dimensional process information; wherein, the through-silicon via (TSV) size information is determined by the three-dimensional process information, and the transistor size information is determined by the two-dimensional process information.

[0067] Optionally, the data testing and data collection on the completed test structure includes: collecting Itsvx / dtsvy data under different device types and sizes, at different temperatures, and with different device sizes. d -V g Curve, I d- V d The curves are Cgg and Cgc; where dtsvx represents the distance in the X direction between the center of the transistor and the center of the through-silicon via (TSV), dtsvy represents the distance in the Y direction between the center of the transistor and the center of the TSV, and I... d -V g The curve represents the situation with a fixed drain-source voltage V. D Drain-source current I d With gate-source voltage V g Changing curve, I d- V d The curve represents the situation with a fixed gate-source voltage V. G Drain-source current I d The curves show how the drain-source voltage Vd changes, where Cgg represents the capacitance between the gate and the source, and Cgc represents the capacitance between the gate and the drain.

[0068] Optionally, the model building unit 15 includes: The first acquisition module is used to acquire the first model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and gate length at the nominal temperature, the second model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and gate length, the third model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and fin number or nanosheet width, and the fourth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and fin number or nanosheet width. The function creation module is used to add the original parameter function of the device model under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function and the fourth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0069] Optionally, the model building unit 15 further includes: The second acquisition module is used to acquire the fifth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx with gate length and fin number or nanosheet width at the nominal temperature, and the sixth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy with gate length and fin number or nanosheet width. The function establishment module is further used to add the original function of the device model parameters under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function, the fourth model parameter change function, the fifth model parameter change function and the sixth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

[0070] Optionally, the model building unit 15 further includes: The third acquisition module is used to acquire the temperature change function between other temperatures and the nominal temperature; The function establishment module is further used to add the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature to the temperature change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at other temperatures.

[0071] The apparatus in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be repeated here.

[0072] This invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the above-described method for establishing a device model based on three-dimensional integrated technology.

[0073] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for establishing a device model based on three-dimensional integrated circuit technology, characterized in that, The method includes: Based on the product requirements of 3D integrated circuits, determine the 2D and 3D process information; Based on the aforementioned two-dimensional and three-dimensional process information, the key dimensions of the test structure are determined. Design test structures for devices based on three-dimensional integrated circuit technology; The test structure is fabricated using two-dimensional and three-dimensional processes, and data testing and data collection are performed on the fabricated test structure. Using the collected data, a device model based on three-dimensional integrated circuit technology is established.

2. The method according to claim 1, characterized in that, The determination of the key dimensions of the test structure based on the two-dimensional and three-dimensional process information includes: The lower boundary of the critical dimension of the test structure is determined based on two-dimensional and three-dimensional process design rules. The upper boundary of the critical dimensions of the test structure was determined by simulation based on computer-aided design technology.

3. The method according to claim 1, characterized in that, The overall layout of the test structure is determined by both two-dimensional and three-dimensional process information; among which, the through-silicon via (TSV) size information is determined by the three-dimensional process information, and the transistor size information is determined by the two-dimensional process information.

4. The method according to claim 1, characterized in that, The data testing and data collection on the completed test structure includes: collecting Itsvx / dtsvy data under different device types and sizes, at different temperatures, and with different device sizes. d -V g Curve, I d- V d The curves are Cgg and Cgc; where dtsvx represents the distance in the X direction between the center of the transistor and the center of the through-silicon via (TSV), dtsvy represents the distance in the Y direction between the center of the transistor and the center of the TSV, and I... d -V g The curve represents the situation with a fixed drain-source voltage V. D Drain-source current I d With gate-source voltage V g Changing curve, I d- V d The curve represents the situation with a fixed gate-source voltage V. G Drain-source current I d The curves show how the drain-source voltage Vd changes, where Cgg represents the capacitance between the gate and the source, and Cgc represents the capacitance between the gate and the drain.

5. The method according to claim 4, characterized in that, The process of establishing a device model based on three-dimensional integrated circuit technology using the collected data includes: Obtain the first model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx and gate length at the nominal temperature, the second model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy and gate length, the third model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx and fin number or nanosheet width, and the fourth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy and fin number or nanosheet width. The original parameter function of the device model under the two-dimensional process is added to the parameter variation functions of the first model, the second model, the third model, and the fourth model to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

6. The method according to claim 5, characterized in that, The process of establishing a device model based on three-dimensional integrated circuit technology using the collected data also includes: Obtain the fifth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvx with gate length and fin number or nanosheet width at the nominal temperature, and the sixth model parameter variation function reflecting the device performance variation caused by the coupling effect of dtsvy with gate length and fin number or nanosheet width. The original parameter function of the device model under the two-dimensional process is added to the parameter variation functions of the first model, the second model, the third model, the fourth model, the fifth model, and the sixth model to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

7. The method according to claim 5 or 6, characterized in that, The process of establishing a device model based on three-dimensional integrated circuit technology using the collected data also includes: Obtain the temperature change function at other temperatures and the nominal temperature; The customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature is added to the temperature change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at other temperatures.

8. A device for establishing a device model based on three-dimensional integrated circuit technology, characterized in that, The device includes: The first determining unit is used to determine the two-dimensional process information and the three-dimensional process information based on the product requirements of the three-dimensional integrated circuit. The second determining unit is used to determine the key dimensions of the test structure based on the two-dimensional process information and the three-dimensional process information. Design unit, used for designing test structures for devices based on three-dimensional integrated circuit technology; The data testing and collection unit is used to perform two-dimensional and three-dimensional fabrication of the test structure, and to perform data testing and data collection on the completed test structure. The model building unit is used to build a device model based on three-dimensional integrated circuit technology using the data collected by the data testing and collection unit.

9. The apparatus according to claim 8, characterized in that, The second determining unit includes: The first determination module is used to determine the lower boundary of the critical dimension of the test structure based on two-dimensional process design rules and three-dimensional process design rules. The second determination module is used to determine the upper boundary of the critical dimensions of the test structure based on computer-aided design technology simulation.

10. The apparatus according to claim 8, characterized in that, The overall layout of the test structure is determined by both two-dimensional and three-dimensional process information; among which, the through-silicon via (TSV) size information is determined by the three-dimensional process information, and the transistor size information is determined by the two-dimensional process information.

11. The apparatus according to claim 8, characterized in that, The data testing and data collection on the completed test structure includes: collecting Itsvx / dtsvy data under different device types and sizes, at different temperatures, and with different device sizes. d -V g Curve, I d- V d The curves are Cgg and Cgc; where dtsvx represents the distance in the X direction between the center of the transistor and the center of the through-silicon via (TSV), dtsvy represents the distance in the Y direction between the center of the transistor and the center of the TSV, and I... d -V g The curve represents the situation with a fixed drain-source voltage V. D Drain-source current I d With gate-source voltage V g Changing curve, I d- V d The curve represents the situation with a fixed gate-source voltage V. G Drain-source current I d The curves show how the drain-source voltage Vd changes, where Cgg represents the capacitance between the gate and the source, and Cgc represents the capacitance between the gate and the drain.

12. The apparatus according to claim 11, characterized in that, The model building unit includes: The first acquisition module is used to acquire the first model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and gate length at the nominal temperature, the second model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and gate length, the third model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx and fin number or nanosheet width, and the fourth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy and fin number or nanosheet width. The function creation module is used to add the original parameter function of the device model under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function and the fourth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

13. The apparatus according to claim 12, characterized in that, The model building unit also includes: The second acquisition module is used to acquire the fifth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvx with gate length and fin number or nanosheet width at the nominal temperature, and the sixth model parameter change function reflecting the device performance variation caused by the coupling effect of dtsvy with gate length and fin number or nanosheet width. The function establishment module is further used to add the original function of the device model parameters under the two-dimensional process to the first model parameter change function, the second model parameter change function, the third model parameter change function, the fourth model parameter change function, the fifth model parameter change function and the sixth model parameter change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature.

14. The apparatus according to claim 13, characterized in that, The model building unit also includes: The third acquisition module is used to acquire the temperature change function between other temperatures and the nominal temperature; The function establishment module is further used to add the customized parameter function of the device model based on the three-dimensional integrated circuit process at the nominal temperature to the temperature change function to obtain the customized parameter function of the device model based on the three-dimensional integrated circuit process at other temperatures.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 7.

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