A hybrid optimization-based PCB layout compliance method and system

Abstract

This invention discloses a PCB layout compliance method and system based on hybrid optimization, belonging to the field of electronic design automation technology. The method includes: taking the original PCB layout as the initial state, iteratively adjusting the component positions using gradient descent to minimize the total loss function, obtaining a pre-optimized PCB layout; performing violation detection on the pre-optimized PCB layout to identify non-compliant components; calculating the resultant force vector pointing to the feasible region for the non-compliant components based on geometric relationships; performing bounded movement of the non-compliant components based on the resultant force vector to obtain a repaired PCB layout; taking the repaired PCB layout as the initial state, iteratively adjusting the component positions again using gradient descent to minimize the total loss function, obtaining a compliant PCB layout. Through the framework of gradient descent pre-optimization, geometric force repair, and gradient descent re-optimization, a fast-converging, high-precision, and high-fidelity PCB layout compliance is achieved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a PCB layout compliance method and system based on hybrid optimization. Background Technology

[0002] In the field of Electronic Design Automation (EDA), as modern electronic devices develop towards higher performance and higher density, the physical layout design of printed circuit boards (PCBs) has become increasingly complex. Problems such as component overlap, board outline violations, keep-out zone intrusion, and spacing violations are unavoidable during the layout stage. Therefore, PCB layout compliance has become a critical post-processing step in the EDA workflow, aiming to automatically and efficiently eliminate all design rule violations while preserving the original electrical and physical intent of the layout.

[0003] Currently, the mainstream methods for compliant PCB layout mainly include the following:

[0004] 1. Rule-driven rigid push method: After detecting a violation, the minimum translation vector is calculated for each violating component in sequence, and the component is immediately moved to eliminate the current violation until all hard constraints are satisfied. This method has low computational cost, but is sensitive to the order of operations.

[0005] 2. Optimization method based on mathematical programming: This method models violations such as overlapping area and boundary overflow length as objective functions, and uses linear programming, quadratic programming, or gradient descent to solve for the global minimum in one step. This method converges quickly by considering all components simultaneously, but it is prone to getting trapped in local minima in high-density regions.

[0006] 3. Optimization methods based on intelligent search: These methods utilize genetic algorithms, particle swarm optimization, reinforcement learning, etc., to adjust the position of components under the drive of a reward function, while also considering signal integrity or heat dissipation performance. This approach leverages an exploration mechanism to escape local optima and can introduce multi-objective rewards, but requires pre-training or numerous iterations.

[0007] 4. Generative optimization methods based on large models: These methods rely on large language models or graph neural networks to learn the semantic rules and design intent of PCB layout through pre-training, directly generating or optimizing layout schemes. These methods depend on large-scale labeled data for pre-training, resulting in high labeling costs.

[0008] Therefore, all existing technologies have inherent limitations and cannot simultaneously achieve PCB layout compliance with fast convergence, high precision, and high fidelity. Summary of the Invention

[0009] The technical problem to be solved by this invention is that existing methods are unable to simultaneously achieve fast convergence, high accuracy and high fidelity in PCB layout compliance. The purpose is to provide a PCB layout compliance method and system based on hybrid optimization, which solves the above problems.

[0010] This invention is achieved through the following technical solution:

[0011] In a first aspect, the present invention provides a PCB layout compliance method based on hybrid optimization, comprising:

[0012] Obtain the original PCB layout containing design rule violations;

[0013] Using the original PCB layout as the initial state, the component positions are iteratively adjusted using the gradient descent method to minimize the total loss function, resulting in a pre-optimized PCB layout; wherein, the total loss function includes a displacement loss term, a boundary violation loss term, a no-load area loss term, and an overlap loss term;

[0014] The pre-optimized PCB layout is subjected to violation detection to identify movable non-compliant components; the non-compliant components refer to components that extend beyond the board frame boundary, intrude into the no-layout area, or overlap with other components;

[0015] Calculate the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships;

[0016] Based on the resultant thrust vector, the position of the non-compliant component is moved in a bounded manner to obtain the repaired PCB layout.

[0017] Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, thus obtaining a compliant PCB layout.

[0018] Optionally, before calculating the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships, the method further includes:

[0019] If the non-compliant component is a component that extends beyond the board frame boundary, then the coordinates of the non-compliant component will be clipped to within the board frame boundary.

[0020] If the unauthorized component is a component that intrudes into the restricted area, then the unauthorized component is moved to the outside of the restricted area along the outer normal direction of the restricted area boundary;

[0021] If the non-compliant component is an overlapping component with other components, the two overlapping components will be translated away from each other along the center line until the overlap is eliminated.

[0022] Optionally, the bounded movement of the position of the non-compliant component based on the resultant thrust vector includes:

[0023] Based on the resultant thrust vector and the preset movement step size, the position of the non-compliant component is updated, and a bounded random perturbation is applied during the update process.

[0024] Optionally, the step of calculating the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships includes:

[0025] If the non-compliant component is a component that extends beyond the board frame boundary, then a first thrust component pointing inwards towards the board frame is generated;

[0026] If the non-compliant component is a component that intrudes into the restricted area, then a second thrust component is generated in the outward normal direction along the boundary of the restricted area;

[0027] If the non-compliant component is a component that overlaps with other components, then a third thrust component is generated along the line connecting the centers of the two overlapping components in a direction that moves away from each other.

[0028] The first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component are vector synthesized to obtain the resultant thrust vector of the non-compliant component.

[0029] Optionally, after vector synthesis of the first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component to obtain the resultant thrust vector of the non-compliant component, the method further includes:

[0030] If the magnitude of the resultant thrust vector exceeds a preset maximum thrust threshold, the resultant thrust vector is scaled so that its magnitude is equal to the maximum thrust threshold.

[0031] Optionally, the total loss function is as follows:

[0032]

[0033] Where L represents the total loss; This refers to the displacement loss term; The number of components that have undergone displacement; For the boundary violation loss item; This refers to the number of components that extend beyond the board frame boundary. For the overlapping loss term; This represents the number of overlapping component pairs. The loss item is the one associated with the restricted area. This represents the number of components that have intruded into the restricted area.

[0034] Optionally, before obtaining the pre-optimized PCB layout by iteratively adjusting the component positions using gradient descent to minimize the total loss function, taking the original PCB layout as the initial state, the method further includes:

[0035] Replace the board outline boundary in the original PCB layout with its axis-aligned bounding box;

[0036] A normalized coordinate system is established based on the axis-aligned bounding box, and all components in the original PCB layout and the board frame boundary are mapped to the normalized coordinate system.

[0037] The geometric difference between the axis-aligned bounding box and the board frame boundary is defined as the boundary forbidden area, and the native forbidden area in the original PCB layout and the boundary forbidden area are uniformly represented as polygons;

[0038] The position, size, and constraint information of all components in the original PCB layout are organized into a matrix.

[0039] Optionally, after uniformly representing the native keep-out areas and the boundary keep-out areas in the original PCB layout as polygons, the method further includes:

[0040] If any forbidden region is uniformly represented as a concave polygon, then the concave polygon is decomposed into multiple sub-polygons without concave vertices, and the any forbidden region is replaced by a set containing the multiple sub-polygons.

[0041] Optionally, the step of taking the repaired PCB layout as the initial state and iteratively adjusting the component positions again using gradient descent to minimize the total loss function to obtain a compliant PCB layout includes:

[0042] Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, resulting in a re-optimized PCB layout.

[0043] If the evaluation metrics of the re-optimized PCB layout are better than those of the repaired PCB layout, then the re-optimized PCB layout will be output as the compliant PCB layout.

[0044] If the evaluation metric of the repaired PCB layout is better than the evaluation metric of the re-optimized PCB layout, then the repaired PCB layout is output as the compliant PCB layout; the evaluation metric is the value of the total loss function or the number of non-compliant components.

[0045] Secondly, the present invention provides a PCB layout compliance system based on hybrid optimization, comprising:

[0046] The acquisition module is used to acquire the original PCB layout containing design rule violations;

[0047] The pre-optimization module is used to take the original PCB layout as the initial state and iteratively adjust the positions of components using the gradient descent method to minimize the total loss function, thereby obtaining a pre-optimized PCB layout; wherein, the total loss function includes a displacement loss term, a boundary violation loss term, a no-load area loss term, and an overlap loss term;

[0048] The violation detection module is used to detect violations in the pre-optimized PCB layout and identify movable non-compliant components; the non-compliant components refer to components that exceed the board frame boundary, intrude into the no-layout area, or overlap with other components;

[0049] The thrust calculation module is used to calculate the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships;

[0050] The repair module is used to perform a bounded movement of the position of the non-compliant component based on the resultant thrust vector to obtain the repaired PCB layout.

[0051] The re-optimization module is used to take the repaired PCB layout as the initial state and iteratively adjust the component positions again through gradient descent to minimize the total loss function and obtain a compliant PCB layout.

[0052] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0053] This application provides a PCB layout compliance method based on hybrid optimization. Starting with the original PCB layout, the method minimizes the total loss function using gradient descent to coarsely adjust component positions globally, quickly obtaining a pre-optimized PCB layout and significantly reducing the overall level of various violations. For hard geometric conflicts (such as deep overlap and boundary intrusion) that remain after pre-optimization and are difficult to completely eliminate using gradient descent, the method calculates the resultant force pushing the non-compliant components towards the feasible region based on geometric relationships, performing targeted and powerful local corrections to the pre-optimized PCB layout. This helps the optimization process escape local optima traps, resulting in a significantly improved repaired PCB layout. Finally, starting with the high-quality repaired PCB layout, the gradient descent algorithm is executed again for fast and fine local convergence, ultimately outputting a compliant PCB layout. Because the total loss function explicitly includes a displacement loss term, which is continuously optimized during the two gradient descent iterations, the algorithm automatically seeks the minimum displacement path while searching for a zero-violation solution. This allows for rapid PCB layout compliance while maximizing the preservation of the electrical and physical design intent of the original layout (high fidelity). Attached Figure Description

[0054] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0055] Figure 1 A flowchart illustrating a PCB layout compliance method based on hybrid optimization provided in this application embodiment;

[0056] Figure 2 Another flowchart illustrating the PCB layout compliance method based on hybrid optimization provided in this application embodiment;

[0057] Figure 3 The original PCB layout at the top level provided for embodiments of this application;

[0058] Figure 4 The underlying original PCB layout provided for embodiments of this application;

[0059] Figure 5 The top-level pre-optimized PCB layout provided for the embodiments of this application;

[0060] Figure 6 The underlying pre-optimized PCB layout provided for the embodiments of this application;

[0061] Figure 7 The top-level compliant PCB layout provided for the embodiments of this application;

[0062] Figure 8 The underlying compliant PCB layout provided for the embodiments of this application. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0064] Please refer to Figure 1 This is a flowchart illustrating a PCB layout compliance method based on hybrid optimization provided in this application embodiment. The following is a further explanation. Figure 1 The PCB layout compliance method based on hybrid optimization is introduced.

[0065] S1. Obtain the original PCB layout containing design rule violations.

[0066] In practice, the original PCB layout is read from electronic design automation (EDA) tools, standard data files, or memory interfaces. The original PCB layout refers to PCB layout data where component positions are initially determined but not yet fully satisfy all design rules. This includes: the geometric outline of the board frame, the definition of one or more keep-out zones, the identification of multiple components, their location coordinates, physical dimensions, and their layer information. The original PCB layout may contain one or more design rule violations, such as component overlap, components exceeding board frame boundaries, or components encroaching on keep-out zones.

[0067] In one possible embodiment, in order to complete the calculation and updating of constraints such as boundaries, forbidden areas, and overlaps in a unified vector space, the original PCB layout is preprocessed into vectorization before executing S2. The preprocessing into vectorization includes the following steps:

[0068] S1.1 Replace the board outline boundary in the original PCB layout with its axis-aligned bounding box (AABB).

[0069] To geometrically simplify and vectorize the irregular plate frame outline to support efficient boundary constraint calculations, the plate frame boundary is replaced with its axis-aligned bounding box. Specifically, the coordinates of all vertices of the plate frame boundary are traversed, and the minimum value Xmin and maximum value Xmax are extracted from the x-coordinates of all vertices, and the minimum value Ymin and maximum value Ymax are extracted from the y-coordinates of all vertices. Based on the extracted extreme values, a four-dimensional vector B_phys is constructed to represent the axis-aligned bounding box: B_phys=[Xmin,Xmax,Ymin,Ymax].

[0070] When there are multiple board outlines in the original PCB layout, calculate the area of ​​the axis-aligned bounding box corresponding to each board outline boundary, select the board outline boundary corresponding to the axis-aligned bounding box with the largest area as the outer boundary, and use its vector B_phys as the boundary representation of the global layout.

[0071] S1.2. Establish a normalized coordinate system based on axis-aligned bounding boxes, and map all components and board outlines in the original PCB layout to the normalized coordinate system.

[0072] To improve numerical stability and eliminate the influence of different PCB sizes on the optimization process, a normalized scaling factor is calculated based on the four-dimensional vector B_phys of the axis-aligned bounding box: scale = max(Xmax - Xmin, Ymax - Ymin). Using the scaling factor scale and the origin (Xmin, Ymin) of the axis-aligned bounding box, a linear transformation is performed on all physical geometric quantities:

[0073] The center point P=(x, y) of the component is mapped to normalized coordinates P'=((x-Xmin) / scale, (y-Ymin) / scale);

[0074] The component's dimensions S=(w, h) are mapped to the normalized dimensions S'=(w / scale, h / scale);

[0075] The plate frame boundary is mapped to the normalized plate frame boundary B_norm=[0, (Xmax-Xmin) / scale, 0, (Ymax-Ymin) / scale].

[0076] In this embodiment, PCB layouts of any physical size can be mapped to a computational space with uniform scale and stable values. This eliminates the problem of inconsistent physical dimensions caused by significant differences in absolute coordinate values ​​between different designs, providing a standardized input benchmark for all subsequent calculations. This ensures that all subsequent constraint calculations (such as loss functions and gradients) are performed within a uniform and appropriate numerical range, fundamentally avoiding numerical instability issues such as gradient explosion, vanishing gradients, or difficulty in setting optimizer step sizes due to differences in coordinate dimensions, thus guaranteeing the algorithm's wide applicability.

[0077] S1.3 Define the geometric difference between the axis-aligned bounding box and the board frame boundary as the boundary forbidden area, and unify the native forbidden area and the boundary forbidden area in the original PCB layout as polygons.

[0078] In the specific implementation process, the difference between the rectangular region defined by the axis-aligned bounding box and the polygonal region corresponding to the actual plate frame boundary is defined as the boundary forbidden area and included in the forbidden area set. In this way, while simplifying the boundary calculation using the axis-aligned bounding box (AABB), it also takes into account the constraint effect on the real complex plate frame contour (such as those with concave, slotted or non-rectangular outer contours).

[0079] In PCB layout data generated by EDA tools, keep-away areas are mainly described in two ways:

[0080] The first type, multi-segment polyline form, is described by a sequence of line segments containing arc parameters.

[0081] For example: [[x0, y0, angle0], [x1, y1, angle1],..., [x n , y n angle n ]], where (x n ,y n () represents the two-dimensional coordinates of the nth point; angle n This represents the arc angle from the nth point to the (n+1)th point.

[0082] The second type is circular: described by the coordinates of the center and the radius.

[0083] For example: [c x , c y , r];wherein, (c x , c y ) represents the coordinates of the center of the circle, and r represents the radius.

[0084] To achieve vectorized calculation of all forbidden zones, all forbidden zones (newly constructed boundary forbidden zones and native forbidden zones defined in the original PCB layout) need to be uniformly converted into polygon representations, that is, a list of polygon vertices composed of several two-dimensional points.

[0085] For the first type (the forbidden area in the form of a multi-segment polyline), the arc segment is discretized and sampled into several line segments, which are then replaced with a pure polyline polygon vertex sequence.

[0086] For the second type (circular restricted area), the circle is approximated by a regular polygon with a fixed number of sides, generating a vertex set: K. i =[[x0, y0], [x1, y1],..., [x n , y n ]).

[0087] S1.4 Organize the position, size, and constraint information of all components in the original PCB layout into a matrix.

[0088] In the specific implementation process, for each component i in the original PCB layout, its normalized center coordinates (x, y, y) are extracted. i , y i ) and envelope size (width w i and high h i The i-th component is represented as: position vector P i =(x i , y i ) and size vector S i =(w i , h i ).

[0089] P of all N components i Stack them row by row to form an N x 2 matrix: P ∈ R^{N×2}; S of all N components i Stack them row by row to form an N-row, 2-column matrix: S∈R^{N×2}; where R represents the set of real numbers, and R^(N×2) represents the set of all N-row, 2-column real number matrices.

[0090] To distinguish whether components are allowed to move during the optimization process, a fixed mask vector is constructed: F∈{0,1}^N; where {0,1}^N represents a set of binary vectors of length N; F[i]=1 indicates that the i-th component is a fixed component whose position cannot be moved (such as a connector or screw hole), and F[i]=0 indicates that the i-th component is a movable component.

[0091] When component types and minimum spacing constraints exist, a type number vector T_id is generated for each component in the original PCB layout. The minimum spacing constraints between component types are organized into a two-dimensional lookup table matrix D_table and a default spacing parameter d_default. The row and column indices of the two-dimensional lookup table matrix correspond to the component type numbers, and the matrix element values ​​represent the minimum allowable spacing between corresponding component pairs. This is used to quickly obtain the minimum safe spacing between any pair of components in subsequent overlap constraint and mutual repulsion force calculations.

[0092] After completing the unified polygonal representation of the no-catch zone, considering that some polygons may be concave, directly calculating the distance or performing inclusion checks on them can easily lead to numerical instability or low efficiency. In a preferred embodiment, after executing S1.3, the method further includes:

[0093] If any forbidden region is uniformly represented as a concave polygon, then the concave polygon is decomposed into multiple sub-polygons without concave vertices, and any forbidden region is replaced by a set containing multiple sub-polygons.

[0094] In the specific implementation process, all forbidden regions represented as polygons are traversed. For any forbidden region polygon, it is determined whether it is a concave polygon. If it is a concave polygon, a decomposition operation is performed, with the following steps:

[0095] Step a: For the polygon to be decomposed, traverse all its vertices and identify all concave vertices by calculating the cross product of adjacent edge vectors. If there are no concave vertices, the polygon is a convex polygon, and the decomposition is complete.

[0096] Step b: Starting from each concave vertex, emit a ray along its angle bisector (or an approximate direction).

[0097] Step c: Calculate the intersection points of the ray with the non-adjacent sides of the polygon, and use the line connecting the concave vertex and the intersection point as the actual cutting line to divide the polygon to be decomposed into two sub-polygons.

[0098] Step d: Recursively execute steps a-c for each sub-polygon until each sub-polygon does not contain concave vertices, thus obtaining multiple sub-polygons without concave vertices.

[0099] Finally, the original restricted area K will be... iReplace it with a set of multiple polygonal fragments without concave vertices, thereby realizing the segmentation and combination representation of irregular forbidden regions.

[0100] In the embodiments of this application, the concave polygon is decomposed into a series of convex polygons. Convex polygons are recognized as ideal primitives in computational geometry. Their mathematical properties (such as the line connecting any two points being inside the shape) make operations such as distance calculation and inclusion judgment simple, stable and efficient.

[0101] S2. Using the original PCB layout as the initial state, the component positions are iteratively adjusted using the gradient descent method to minimize the total loss function, resulting in a pre-optimized PCB layout.

[0102] In the implementation process, the component positions in the original PCB layout are used as the initial values ​​of the optimization variables. The goal is to minimize the total loss function, and gradient descent is used for iterative optimization. In each iteration, gradient calculation and position updates are performed until a preset termination condition is met. For example, if the decrease in the total loss function over several consecutive iterations is less than a preset decrease, or if the number of iterations reaches a preset number, the iteration stops. The final optimization variables are then decoded into the specific positions of the components, and the pre-optimized PCB layout is output.

[0103] S3. Perform violation detection on the pre-optimized PCB layout and identify movable non-compliant components.

[0104] In the specific implementation process, for each component in the pre-optimized PCB layout, indicators such as boundary violations, intrusion into no-go zones, and component overlap are calculated to filter out a set of non-compliant components that exceed the board boundary, intrude into no-go zones, or overlap with other components. Based on the fixed mask vector obtained through vectorization preprocessing, movable non-compliant components are filtered out from the set of non-compliant components.

[0105] It should be noted that although fixed components do not participate in subsequent position updates, their geometric contours will still be used as part of the constraints to participate in the violation assessment and thrust calculation of other movable components, ensuring the compliance of the overall layout.

[0106] For a two-layer PCB layout with a top and bottom layer, violations within the same layer can be detected independently for components on the top and bottom layers. Optionally, based on design rules, cross-layer constraint violations that need to be satisfied between specific component pairs (such as one on the top layer and one on the bottom layer) can be additionally detected and calculated.

[0107] S4. Calculate the resultant thrust vector pointing to the feasible region for non-compliant components based on geometric relationships.

[0108] In one possible embodiment, to improve the efficiency and stability of subsequent repair operations, a projection operation is performed on the current layout before executing S4, so that the component positions are as close as possible to the feasible region. The steps of the projection operation are as follows:

[0109] If the non-compliant component is a component that extends beyond the board frame boundary, then the coordinates of the non-compliant component will be clipped to within the board frame boundary. If the non-compliant component is a component that intrudes into the no-fly zone, then the non-compliant component will be moved to the outside of the no-fly zone along the outer normal direction of the no-fly zone boundary. If the non-compliant component is a component that overlaps with other components, then the two overlapping components will be translated away from each other along the center line until the overlap is eliminated.

[0110] In the embodiments of this application, the projection operation involves only simple geometric calculations (such as comparison, clipping, and vector extrapolation), with extremely low computational overhead. However, it can significantly reduce or even eliminate a large number of obvious serious violations (such as depth out-of-bounds and complete overlap) in a single traversal, providing a stable starting point closer to the feasible region for subsequent push-based fine repair.

[0111] In one possible embodiment, the specific steps of S4 include:

[0112] If the non-compliant component is a component that extends beyond the board frame boundary, a first thrust component pointing inwards towards the board frame is generated; if the non-compliant component is a component that intrudes into the restricted area, a second thrust component is generated along the outward normal direction of the restricted area boundary; if the non-compliant component is a component that overlaps with other components, a third thrust component is generated along the line connecting the centers of the two overlapping components, moving away from each other; the first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component are vector-synthesized to obtain the resultant thrust vector of the non-compliant component.

[0113] In this embodiment, thrust components are generated along the most effective geometric direction (pointing to the feasible region, along the escape normal, and along the separation line) for different violation types. This ensures that the repair action has a clear purpose and the shortest path, avoiding blind searching and greatly improving the accuracy and efficiency of the repair. To balance the repair intensity of different types of constraints, the first, second, and third thrust components acting on the same violation component are weighted and superimposed based on preset weight coefficients to obtain the resultant thrust vector of the violation component. .

[0114] When components simultaneously violate multiple rules, vector synthesis can collaboratively integrate the repair forces from different constraints. The direction of the synthesized resultant force represents an optimal compromise direction that simultaneously alleviates all conflicts, thus avoiding the repeated oscillations that may be caused by sequential repair and achieving synchronous and coordinated resolution of multiple constraints. Furthermore, gradient descent may get stuck in gradient ambiguity or local flatness due to high-density violation regions. Based on hard geometric rules, a high-confidence resultant force is calculated. This force, as a forced local movement signal, can effectively pull the layout out of the deadlock state that gradient descent cannot handle, opening up a better search space for subsequent gradient descent re-optimization.

[0115] In one possible embodiment, to ensure the stability of the violation repair process and prevent new violations or oscillations caused by excessive single-step movement, the resultant thrust vector of the violating component is obtained. Finally, it also includes an amplitude clipping step:

[0116] If the magnitude of the resultant thrust vector exceeds the preset maximum thrust threshold, the resultant thrust vector is scaled so that its magnitude equals the maximum thrust threshold.

[0117] In the specific implementation process, a maximum thrust threshold Fmax is set, which defines the maximum thrust amplitude allowed to be applied in a single repair operation. The magnitude of the resultant thrust vector is calculated. ,like If F ≤ Fmax, it indicates that the thrust is within a controllable range, and the original resultant thrust vector can be used directly. Perform subsequent location updates. If... If the thrust is too large, the resultant thrust vector is scaled proportionally to keep the original direction of the resultant thrust unchanged, but its magnitude is precisely limited to the maximum thrust threshold to ensure that the movement distance of each position update is controlled and improve the stability of the repair process.

[0118] S5. Based on the resultant thrust vector, the position of the non-compliant component is moved in a bounded manner to obtain the PCB layout after repair.

[0119] In one possible embodiment, the position of the non-compliant component is updated based on the resultant thrust vector and a preset movement step size, and a bounded random perturbation is applied during the update process.

[0120] In the specific implementation process, firstly, based on the resultant thrust vector and the preset movement step size, the position of each non-compliant component is initially updated:

[0121]

[0122] in, This represents the position of the i-th non-compliant component before the update. This represents the position of the i-th non-compliant component after the initial update. The preset movement step size; Let be the resultant thrust vector of the i-th non-compliant component.

[0123] To avoid getting trapped in local optima by moving only along the direction of deterministic thrust, a bounded random perturbation is injected only into the components that "actually move / violate" during the repair process:

[0124]

[0125] in, Let i be the position of the i-th non-compliant component after the final update; This represents the position of the i-th non-compliant component after the initial update. The bounded random perturbation applied to the i-th non-compliant component is a zero-mean random vector (e.g., Gaussian noise or uniform noise), whose amplitude can gradually decay with each update cycle, thereby realizing the "explore first, converge later" strategy.

[0126] In this embodiment, deterministic thrust guidance is combined with bounded random perturbation. The thrust provides a strong directional repair force based on geometric rules, while the perturbation introduces local random exploration. This "main direction-driven + auxiliary random exploration" strategy enables the algorithm to efficiently eliminate known violations and escape local optima that may be caused by deterministic paths, significantly enhancing its global search capability.

[0127] In one possible implementation, to ensure the stability of the update process and avoid layout divergence, the following constraints are introduced:

[0128] Boundary clipping constraint: Clip the position coordinates to the range [0, (Xmax-Xmin) / scale, 0, (Ymax-Ymin) / scale] defined by the normalized board frame boundary, so that the components are always kept inside the board frame.

[0129] Trust region constraint: The location is restricted to the region centered on the historical best location of the i-th non-compliant component and bounded by a preset trust radius, to avoid large-scale drift caused by random search.

[0130] In this embodiment, boundary clipping, as an insurmountable physical hard constraint, strictly ensures that components do not leave the feasible region of the board frame at any intermediate step, fundamentally preventing layout collapse. Trust region constraint, as a key algorithmic soft constraint, strictly limits each movement to the local neighborhood of the historical optimal solution. This effectively prevents gradual component drift or overall layout divergence caused by random disturbances or improper push accumulation. The combination of these two constraints ensures that the entire repair process remains highly stable, controllable, and convergent even when randomness is introduced.

[0131] S6. Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function and obtain a compliant PCB layout.

[0132] In one possible embodiment, S6 includes:

[0133] Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, resulting in a re-optimized PCB layout. If the evaluation metric of the re-optimized PCB layout is better than that of the repaired PCB layout, the re-optimized PCB layout is output as a compliant PCB layout.

[0134] In the specific implementation process, similar to the steps in S2, the positions of components in the repaired PCB layout are used as the initial values ​​of the optimization variables. With the goal of minimizing the total loss function, gradient descent is used for iterative optimization. In each iteration, gradient calculation and position are performed until the preset termination condition is met, then the iteration stops, and the final optimization variables are decoded into the specific positions of all components, and the optimized PCB layout is output.

[0135] Furthermore, evaluation metrics are calculated for the re-optimized PCB layout and the repaired PCB layout, respectively. The evaluation metrics are the value of the total loss function or the number of non-compliant components. If the value of the total loss function of the re-optimized PCB layout is less than the value of the total loss function of the repaired PCB layout, or if the number of non-compliant components in the re-optimized PCB layout is less than the number of non-compliant components in the repaired PCB layout, then the re-optimized PCB layout is output as a compliant PCB layout.

[0136] If the total loss function of the PCB layout is greater than or equal to the total loss function of the PCB layout after repair, or if the number of non-compliant components in the PCB layout after repair is greater than or equal to the number of non-compliant components in the PCB layout after repair, the repaired PCB layout will be output as a compliant PCB layout.

[0137] In this embodiment of the application, the repaired PCB layout and the re-optimized PCB layout are compared, and the better one of the two is output. This is equivalent to providing double insurance for the final output result. It eliminates the risk of the final output quality accidentally decreasing due to the randomness, parameter sensitivity or excessive fine-tuning in the re-optimization stage, and ensures that the final output PCB layout is always the globally optimal or near-optimal solution that the entire algorithm can find.

[0138] In one possible embodiment, if the evaluation metric of the repaired PCB layout is better than that of the re-optimized PCB layout, the steps of violation detection, calculation of resultant thrust vector, bounded movement, and gradient descent optimization are repeated, and the evaluation metrics of the new re-optimized PCB layout and the new repaired PCB layout are compared again. This process is repeated until the evaluation metric of the new re-optimized PCB layout is better than that of the new repaired PCB layout, and the re-optimized PCB layout at this time is output as a compliant PCB layout.

[0139] In the embodiments of this application, for some layouts with extremely serious initial violations or particularly complex structures, a single round of repair may not be sufficient to find a high-quality solution. This iterative mechanism allows the algorithm to make multiple attempts with different focuses (e.g., the thrust weight, perturbation amplitude, etc. can be adjusted in subsequent loops), which greatly increases the probability of finding the global optimal solution.

[0140] In one possible embodiment, the total loss function includes a displacement loss term, a boundary violation loss term, a no-fly zone loss term, and an overlap loss term. The expression for the total loss function is as follows:

[0141]

[0142] Where L represents the total loss; This is the displacement loss term; The number of components that have undergone displacement; For losses due to boundary violations; This refers to the number of components that extend beyond the board frame boundary. This is the overlapping loss term; This represents the number of overlapping component pairs. Losses due to the no-clothing zone; This represents the number of components that have intruded into the restricted area.

[0143] In this embodiment, the loss is adaptively normalized by dividing the loss term by the number of violations, which automatically balances the magnitude of different constraints and avoids the dominance of the entire gradient direction due to a surge in the number of violations of a certain type (e.g., a large amount of overlap in the early stage), causing other constraints (such as displacement control) to be ignored.

[0144] The calculation methods for various loss items are described below.

[0145] (1) Displacement loss item :

[0146] The displacement loss term is used to penalize the total displacement of components caused by their position being adjusted during the compliance process.

[0147] The formula for calculating the displacement loss term is as follows:

[0148]

[0149] in, Represents the current position coordinates of the i-th component; Represents the initial position coordinates of the i-th component; This represents the number of components that have undergone displacement.

[0150] (2) Losses due to boundary violations :

[0151] The boundary violation penalty is used to penalize the degree of violation where the component's envelope profile (including safety clearance) exceeds the normalized board frame boundary.

[0152]

[0153] Where d is a spatial dimension variable, taking the value of x (horizontal direction) or y (vertical direction). Let be the coordinates of the center of the i-th component in dimension d; Let be the length of the i-th component in dimension d; when d = x, Width of the i-th component When d=y, The height of the i-th component .

[0154] For the normalized plate-frame boundary values, when d=x, =[Xmin,Xmax], when d=y =[Ymin,Ymax]. δ1 is the preset boundary safety clearance; The number of components extending beyond the board frame boundary; ReLU() is the linear rectification function. This indicates that the symbol selection needs to be based on the boundary direction.

[0155] (3) Losses in the no-clothing zone :

[0156] The no-discharge zone penalty is used to punish the degree of violation of a component entering the no-discharge zone (or the distance between the component and the no-discharge zone is less than the safety gap).

[0157]

[0158] in, Let be the coordinates of the center point of the i-th component. Let j be the boundary line (i.e., polygon) of the j-th forbidden zone. For point Relative polygons The sign distance; For point The approximate radius of the expansion circle relative to its own boundary; δ2 is the preset safety gap of the no-closing zone. ReLU() is the linear rectification function.

[0159] (4) Overlapping loss term :

[0160] The overlap loss term is used to penalize the degree of overlap between two components (including safety gaps).

[0161]

[0162]

[0163]

[0164] ReLU(·) is a linear rectifier function; The distance between the i-th component and the j-th component along the x-axis (including the safety clearance). The distance between the i-th and j-th components along the y-axis (including the safety clearance). Let be the coordinates of the i-th component; and These are the width and height of the i-th component, respectively; Let J be the coordinates of the j-th component; and δ1 and δ2 represent the width and height of the j-th component, respectively. δ3 is the preset safety gap between components, which can be replaced by a default spacing parameter d_default for a specific component type pair by querying the two-dimensional lookup table matrix D_table generated during the preprocessing stage.

[0165] Please refer to Figure 2 This provides another flowchart illustrating a PCB layout compliance method based on hybrid optimization, as described in this application embodiment. The following is a combined... Figure 2 Further details.

[0166] First, the original PCB layout is obtained and preprocessed for data structuring. For a two-layer PCB layout with a top and bottom layer, the original PCB layout of the top layer is as follows: Figure 3As shown, the original PCB layout at the bottom layer is as follows: Figure 4 As shown. Next, gradient descent pre-optimization is performed on the original PCB layout to obtain a pre-optimized PCB layout. The top-level pre-optimized PCB layout is shown below. Figure 5 As shown, the underlying pre-optimized PCB layout is as follows: Figure 6 As shown. Next, the pre-optimized PCB layout undergoes violation detection. If no violations are found, the process ends; otherwise, violations are corrected based on push. Finally, the corrected PCB layout is further optimized using gradient descent to output a compliant PCB layout. The top-level compliant PCB layout is shown below. Figure 7 As shown, the underlying compliant PCB layout is as follows: Figure 8 As shown.

[0167] In summary, this application provides a PCB layout compliance method based on hybrid optimization. It proposes a hybrid iterative framework of "gradient descent - rule correction - thrust perturbation - re-gradient descent", which can quickly eliminate violations such as overlap, board outline out-of-bounds, and forbidden zone intrusion in the original PCB layout without changing the component electrical network and orientation. It simultaneously encodes multiple hard constraints through a differentiable loss function to quantify and control the displacement of each component relative to its initial position. No pre-training or additional analysis is required, and it can be directly integrated into the existing EDA process to achieve batch automation.

[0168] Based on the same inventive concept, this application also provides a PCB layout compliance system based on hybrid optimization, the system comprising:

[0169] The acquisition module is used to acquire the original PCB layout containing design rule violations;

[0170] The pre-optimization module is used to iteratively adjust the positions of components using gradient descent to minimize the total loss function, taking the original PCB layout as the initial state, and obtain the pre-optimized PCB layout. The total loss function includes displacement loss, boundary violation loss, no-load loss, and overlap loss.

[0171] The violation detection module is used to detect violations in the pre-optimized PCB layout and identify movable non-compliant components; the non-compliant components refer to components that exceed the board frame boundary, intrude into the no-layout area, or overlap with other components;

[0172] The thrust calculation module is used to calculate the resultant thrust vector pointing to the feasible region for non-compliant components based on geometric relationships.

[0173] The repair module is used to perform bounded movement of the position of the non-compliant component based on the resultant thrust vector to obtain the repaired PCB layout.

[0174] The re-optimization module is used to take the repaired PCB layout as the initial state and iteratively adjust the component positions again using the gradient descent method to minimize the total loss function and obtain a compliant PCB layout.

[0175] Optionally, the system also includes a projection operation module, which is used for:

[0176] Before calculating the resultant thrust vector pointing to the feasible region for non-compliant components based on geometric relationships, if the non-compliant component is a component that exceeds the plate frame boundary, then the coordinates of the non-compliant component are clipped to within the plate frame boundary.

[0177] If the non-compliant component is a component that has intruded into the restricted area, then the non-compliant component will be moved to the outside of the restricted area along the outer normal direction of the restricted area boundary;

[0178] If the non-compliant component is an overlapping component with other components, the two overlapping components will be translated along the center line away from each other until the overlap is eliminated.

[0179] Optionally, the repair module is specifically used for:

[0180] Based on the resultant thrust vector and the preset movement step size, the position of the non-compliant component is updated, and a bounded random perturbation is applied during the update process.

[0181] Optionally, the thrust calculation module is specifically used for:

[0182] If the non-compliant component is a component that extends beyond the board frame boundary, then a first thrust component pointing inwards towards the board frame is generated.

[0183] If the non-compliant component is a component that intrudes into the restricted area, a second thrust component is generated in the outward normal direction along the boundary of the restricted area;

[0184] If the non-compliant component is an overlapping component with other components, a third thrust component is generated along the line connecting the centers of the two overlapping components in a direction that moves away from each other.

[0185] Vector synthesis is performed on the first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component to obtain the resultant thrust vector of the non-compliant component.

[0186] Optionally, the thrust calculation module is also used for:

[0187] After vector synthesis of the first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component to obtain the resultant thrust vector of the non-compliant component, if the magnitude of the resultant thrust vector exceeds the preset maximum thrust threshold, the resultant thrust vector is scaled so that the magnitude of the resultant thrust vector is equal to the maximum thrust threshold.

[0188] Optional, the total loss function is as follows:

[0189]

[0190] Where L represents the total loss; This is the displacement loss term; The number of components that have undergone displacement; For losses due to boundary violations; This refers to the number of components that extend beyond the board frame boundary. This is the overlapping loss term; This represents the number of overlapping component pairs. Losses due to the no-clothing zone; This represents the number of components that have intruded into the restricted area.

[0191] Optionally, the system also includes a preprocessing module, which is used for:

[0192] Before obtaining the pre-optimized PCB layout by iteratively adjusting the positions of components using gradient descent to minimize the total loss function, the board outline boundaries in the original PCB layout are replaced with their axis-aligned bounding boxes.

[0193] A normalized coordinate system is established based on axis-aligned bounding boxes, mapping all components and board outlines in the original PCB layout to the normalized coordinate system;

[0194] Define the geometric difference between the axis-aligned bounding box and the board frame boundary as the boundary forbidden area, and unify the native forbidden area and the boundary forbidden area in the original PCB layout as polygons;

[0195] The position, size, and constraint information of all components in the original PCB layout are organized into a matrix.

[0196] Optionally, the preprocessing module is also used to: after uniformly representing the native and boundary forbidden regions in the original PCB layout as polygons, if any forbidden region is uniformly represented as a concave polygon, then decompose the concave polygon into multiple sub-polygons without concave vertices, and replace any forbidden region with a set containing multiple sub-polygons.

[0197] Optionally, the re-optimization module is specifically used for:

[0198] Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, resulting in a re-optimized PCB layout.

[0199] If the evaluation metrics for further optimized PCB layout are better than those for the repaired PCB layout, then the further optimized PCB layout will be output as a compliant PCB layout.

[0200] If the evaluation metrics of the repaired PCB layout are better than those of the optimized PCB layout, then the repaired PCB layout will be output as a compliant PCB layout; the evaluation metrics are the value of the total loss function or the number of non-compliant components.

[0201] It should be noted that each module in the PCB layout compliance system based on hybrid optimization in this embodiment corresponds one-to-one with each step in the PCB layout compliance method based on hybrid optimization in the aforementioned embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned PCB layout compliance method based on hybrid optimization, and will not be repeated here.

[0202] Based on the same inventive concept, this application also provides a computer device, which includes a processor, a memory, and a computer program stored in the memory. The computer program is executed by the processor to implement the aforementioned PCB layout compliance method based on hybrid optimization.

[0203] Based on the same inventive concept, this application also provides a computer storage medium storing a computer program, which is executed by a processor to implement the aforementioned PCB layout compliance method based on hybrid optimization.

[0204] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a device including one or any combination of the above-mentioned memories. The computer may be a variety of computing devices, including smart terminals and servers.

[0205] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0206] As an example, executable instructions may, but do not necessarily, correspond to files in the file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0207] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0208] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0209] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0210] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PCB layout compliance method based on hybrid optimization, characterized in that, include: Obtain the original PCB layout containing design rule violations; Using the original PCB layout as the initial state, the component positions are iteratively adjusted using the gradient descent method to minimize the total loss function, resulting in a pre-optimized PCB layout; wherein, the total loss function includes a displacement loss term, a boundary violation loss term, a no-load area loss term, and an overlap loss term; The pre-optimized PCB layout is subjected to violation detection to identify movable non-compliant components; the non-compliant components refer to components that extend beyond the board frame boundary, intrude into the no-layout area, or overlap with other components; Calculate the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships; Based on the resultant thrust vector, the position of the non-compliant component is moved in a bounded manner to obtain the repaired PCB layout. Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, thus obtaining a compliant PCB layout.

2. The PCB layout compliance method based on hybrid optimization according to claim 1, characterized in that, Before calculating the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships, the method further includes: If the non-compliant component is a component that extends beyond the board frame boundary, then the coordinates of the non-compliant component will be clipped to within the board frame boundary. If the unauthorized component is a component that intrudes into the restricted area, then the unauthorized component is moved to the outside of the restricted area along the outer normal direction of the restricted area boundary; If the non-compliant component is an overlapping component with other components, the two overlapping components will be translated away from each other along the center line until the overlap is eliminated.

3. The PCB layout compliance method based on hybrid optimization according to claim 1, characterized in that, The bounded movement of the position of the non-compliant component based on the resultant thrust vector includes: Based on the resultant thrust vector and the preset movement step size, the position of the non-compliant component is updated, and a bounded random perturbation is applied during the update process.

4. The PCB layout compliance method based on hybrid optimization according to claim 2, characterized in that, The calculation of the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships includes: If the non-compliant component is a component that extends beyond the board frame boundary, then a first thrust component pointing inwards towards the board frame is generated; If the non-compliant component is a component that intrudes into the restricted area, then a second thrust component is generated in the outward normal direction along the boundary of the restricted area; If the non-compliant component is a component that overlaps with other components, then a third thrust component is generated along the line connecting the centers of the two overlapping components in a direction that moves away from each other. The first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component are vector synthesized to obtain the resultant thrust vector of the non-compliant component.

5. The PCB layout compliance method based on hybrid optimization according to claim 4, characterized in that, After vector synthesis of the first thrust component, the second thrust component, and the third thrust component acting on the same non-compliant component to obtain the resultant thrust vector of the non-compliant component, the method further includes: If the magnitude of the resultant thrust vector exceeds a preset maximum thrust threshold, the resultant thrust vector is scaled so that its magnitude is equal to the maximum thrust threshold.

6. The PCB layout compliance method based on hybrid optimization according to claim 1, characterized in that, The total loss function is as follows: ； Where L represents the total loss; This refers to the displacement loss term; The number of components that have undergone displacement; For the boundary violation loss item; This refers to the number of components that extend beyond the board frame boundary. For the overlapping loss term; This represents the number of overlapping component pairs. The loss item is the one associated with the restricted area. This represents the number of components that have intruded into the restricted area.

7. The PCB layout compliance method based on hybrid optimization according to claim 1, characterized in that, Before obtaining the pre-optimized PCB layout by iteratively adjusting the component positions using gradient descent to minimize the total loss function, with the original PCB layout as the initial state, the method further includes: Replace the board outline boundary in the original PCB layout with its axis-aligned bounding box; A normalized coordinate system is established based on the axis-aligned bounding box, and all components in the original PCB layout and the board frame boundary are mapped to the normalized coordinate system. The geometric difference between the axis-aligned bounding box and the board frame boundary is defined as the boundary forbidden area, and the native forbidden area in the original PCB layout and the boundary forbidden area are uniformly represented as polygons; The position, size, and constraint information of all components in the original PCB layout are organized into a matrix.

8. The PCB layout compliance method based on hybrid optimization according to claim 7, characterized in that, After unifying the native keep-out areas and the boundary keep-out areas in the original PCB layout as polygons, the method further includes: If any forbidden region is uniformly represented as a concave polygon, then the concave polygon is decomposed into multiple sub-polygons without concave vertices, and the any forbidden region is replaced by a set containing the multiple sub-polygons.

9. The PCB layout compliance method based on hybrid optimization according to claim 1, characterized in that, The process involves using the repaired PCB layout as the initial state, and then iteratively adjusting the component positions again using gradient descent to minimize the total loss function, resulting in a compliant PCB layout. This includes: Using the repaired PCB layout as the initial state, the component positions are iteratively adjusted again using the gradient descent method to minimize the total loss function, resulting in a re-optimized PCB layout. If the evaluation metrics of the re-optimized PCB layout are better than those of the repaired PCB layout, then the re-optimized PCB layout will be output as the compliant PCB layout. If the evaluation metric of the repaired PCB layout is better than the evaluation metric of the re-optimized PCB layout, then the repaired PCB layout is output as the compliant PCB layout; the evaluation metric is the value of the total loss function or the number of non-compliant components.

10. A PCB layout compliance system based on hybrid optimization, characterized in that, include: The acquisition module is used to acquire the original PCB layout containing design rule violations; The pre-optimization module is used to take the original PCB layout as the initial state and iteratively adjust the positions of components using the gradient descent method to minimize the total loss function, thereby obtaining a pre-optimized PCB layout; wherein, the total loss function includes a displacement loss term, a boundary violation loss term, a no-load area loss term, and an overlap loss term; The violation detection module is used to detect violations in the pre-optimized PCB layout and identify movable non-compliant components; the non-compliant components refer to components that exceed the board frame boundary, intrude into the no-layout area, or overlap with other components; The thrust calculation module is used to calculate the resultant thrust vector pointing to the feasible region for the non-compliant component based on geometric relationships; The repair module is used to perform a bounded movement of the position of the non-compliant component based on the resultant thrust vector to obtain the repaired PCB layout. The re-optimization module is used to take the repaired PCB layout as the initial state and iteratively adjust the component positions again through gradient descent to minimize the total loss function and obtain a compliant PCB layout.

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