Method, system, and storage medium for adjusting processor circuit clock path delay

Abstract

The application provides a processor circuit clock path delay adjustment method, system and storage medium, the method comprises the following steps: constructing a plurality of parallel clock tree branches with increasing delays at a clock root node of a processor circuit; configuring a clock multiplexing unit in front of a clock input interface of an IP core, the clock input side of the clock multiplexing unit is connected to the plurality of parallel clock tree branches, forming clock paths corresponding to different parallel clock tree branches; performing timing test after tape-out, and obtaining timing anomaly identification results of the IP core; determining a target delay, adjusting a selection signal to switch the clock path of the clock multiplexing unit, so that the clock path delay is the same as the target delay. The application can compensate for the silicon and simulation deviation while saving the cost of multi-project wafer scene, can adapt to multi-dimensional environmental changes, and can improve the stability of complex scenes.

Description

Technical Field

[0001] This invention relates to the field of processor integrated circuit design technology, and in particular to a method, system and storage medium for adjusting the clock path delay of a processor circuit. Background Technology

[0002] In processor circuit design, the clock timing performance of the Intellectual Property Core (IP) directly determines the overall functional stability and reliability of the chip. A well-designed clock path is crucial for ensuring that setup and hold timing constraints are met, and its design quality and verification efficiency have a significant impact on chip development cycles and cost control. Currently, IP clock timing design generally relies heavily on early-stage simulation and static timing analysis (STA) results, combined with standard process corners and expected usage scenarios.

[0003] In typical scenarios such as multi-project wafer (MPW) or new IP development, the existing clock timing design and verification process mainly includes three steps:

[0004] First, based on simulation data and STA analysis results, we completed the design work such as IP clock tree construction and logic path optimization; Second, direct chip fabrication and verification; Third, if functional abnormalities or timing issues are found after tape-out, the design will be modified accordingly and tape-out will be repeated.

[0005] While the process is logically clear in theory, its practicality is limited by factors such as tight IP development schedules and limited verification cycles in actual engineering applications. Furthermore, there are inherent deviations between the real working environment of the IP and the simulation model, especially in the case of new architectures, new processes, or first tape-out scenarios.

[0006] Furthermore, in practical engineering, existing technical solutions have obvious shortcomings: First, it is highly dependent on simulation and STA model, and the simplification and assumptions of the model cannot fully cover the process deviations and local non-uniformities of real silicon wafers. Secondly, the risk of hold violations is prominent. Compared with setup violations, hold violations are more hidden and difficult to repair simply, which can easily lead to abnormal chip function or even failure. Third, multiple tape-outs are costly, and in MPW scenarios, tape-out opportunities are limited. Timing issues that lead to re-taps not only increase direct costs but also delay the overall project schedule. Fourth, the IP clock path is not adjustable enough. Once the design is fixed, the finished chip cannot adjust the clock arrival time, and it lacks the ability to remedy the actual behavior of the silicon wafer.

[0007] These defects severely impact the R&D efficiency and yield of processor chips, thus necessitating an optimized clock path delay adjustment scheme to address these technical issues. Summary of the Invention

[0008] This invention provides a method, system, and storage medium for adjusting the clock path delay of a processor circuit, aiming to solve the technical problem of difficulty in adjusting clock delay caused by the lack of adjustability due to simulation testing in existing methods.

[0009] To address the aforementioned technical problems, in a first aspect, the present invention provides a method for adjusting the clock path delay of a processor circuit, comprising the following steps: S101. Construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit. S102. A clock multiplexing unit is configured before the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths by a selection signal. S103. After the processor circuit is fabricated, timing tests are performed, and the timing anomaly identification results of the IP core are obtained. S104. Determine the target delay based on the timing anomaly identification result, adjust the selection signal of the clock multiplexing unit to switch the clock path, so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay.

[0010] Furthermore, in step S101, the delays of the multiple parallel clock tree branches are distributed in an arithmetic progression, wherein the first parallel clock tree branch is the shortest delay path, and each subsequent parallel clock tree branch gradually increases the delay by a fixed amount based on the delay of the previous branch.

[0011] Furthermore, by adjusting at least one of the clock tree structure, buffer levels, or wiring length of the parallel clock tree branches, the delay amounts of the different parallel clock tree branches are made to be distributed in an arithmetic progression.

[0012] Furthermore, in step S102, the selection signal of the clock multiplexer unit is driven and set by at least one of the chip input / output module, top-level control logic, or configuration register.

[0013] Furthermore, in step S103, the timing test includes at least one of functional testing, timing-specific testing, or silicon debugging.

[0014] Furthermore, in step S103, the timing anomaly identification result includes whether the IP core has a hold-time violation and potential functional anomalies related to hold-time.

[0015] Furthermore, in step S104, when the timing anomaly identification result indicates that the IP core has a hold-time violation or potential functional anomaly, the selection signal is adjusted to switch to the clock path corresponding to the parallel clock tree branch with a larger delay.

[0016] In a second aspect, the present invention also provides a system for adjusting the clock path delay of a processor circuit, comprising: A multi-channel clock generation module is used to construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit. The selection control module is used to configure a clock multiplexing unit in front of the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths through a selection signal. The testing module is used to perform timing tests after the processor circuit is fabricated and to obtain the timing anomaly identification results of the IP core. An adjustment module is used to determine the target delay based on the timing anomaly identification result, and adjust the selection signal of the clock multiplexing unit to switch the clock path so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay.

[0017] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a processor circuit clock path delay adjustment program stored in the memory and executable on the processor, wherein when the processor executes the processor circuit clock path delay adjustment program, it implements the steps of the processor circuit clock path delay adjustment method as described in any of the above embodiments.

[0018] Fourthly, the present invention also provides a storage medium storing a processor circuit clock path delay adjustment program, wherein when the processor circuit clock path delay adjustment program is executed by a processor, the processor circuit clock path delay adjustment program implements the steps of the processor circuit clock path delay adjustment method as described in any of the above embodiments.

[0019] The beneficial effects achieved by this invention are that it proposes a method for adjusting the clock path delay of a processor circuit. This method avoids re-wafering caused by hold-time violations by constructing adjustable delay clock branches and configuring selection units. While saving costs in multi-project wafer scenarios, it can compensate for silicon wafer and simulation deviations, and improve the correctness and robustness of IP core functions. At the same time, the adjustment of timing path delay does not require large-scale modification of the internal logic of the IP, has low intrusion into the existing process, can adapt to multi-dimensional environmental changes, and improves the stability of complex scenarios. Attached Figure Description

[0020] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a flowchart of the steps of the processor circuit clock path delay adjustment method provided in the embodiment of the present invention; Figure 2 This is a schematic diagram of a clock multiplexing unit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the processor circuit clock path delay adjustment system provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0021] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0023] Example 1 Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the steps of a processor circuit clock path delay adjustment method provided in an embodiment of the present invention. The processor circuit clock path delay adjustment method includes the following steps: S101. Construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit.

[0024] The core purpose of the S101 is to provide a quantifiable and switchable clock delay basis for subsequent post-silicon timing adjustments, adapt to the timing compensation requirements of IP cores in processor circuits, and solve timing deviation problems caused by process, voltage, temperature (PVT) variations and modeling errors.

[0025] In step S101, the delays of the multiple parallel clock tree branches are distributed in an arithmetic progression, wherein the first parallel clock tree branch is the shortest delay path, and each subsequent parallel clock tree branch gradually increases the delay by a fixed amount based on the delay of the previous branch.

[0026] The core reason for using an arithmetic progression distribution in this invention is to achieve precise and controllable timing adjustments. Processor clock timing repair (especially hold violation repair) requires gradient adjustment of clock arrival times. An arithmetic progression delay allows for predictable and quantifiable changes in timing margins when switching clock paths, avoiding over- or under-adjustment caused by uneven delay gradients. The first path is designed as the shortest delay path to preserve the optimal clock transmission efficiency for the basic timing scenario, meeting the timing baseline requirements for normal processor operation.

[0027] By adjusting at least one of the clock tree structure, buffer levels, or wiring length of the parallel clock tree branches, the delay amounts of the different parallel clock tree branches are made to be distributed in an arithmetic progression.

[0028] During implementation, all three methods can conform to the conventional process technology of processor clock tree design, for example: Adjusting the clock tree structure can change the branch topology, so that the signal transmission path complexity of different branches has a fixed difference, thus forming a fixed delay increment; Adjusting the number of buffer levels is mainly for CMOS buffers commonly used in the processor clock path. The latency of each buffer level is basically fixed. By increasing the number of buffer levels, such as one more buffer level for each subsequent branch than the previous branch, the latency can be precisely increased. Adjusting the wiring length is mainly done during the chip back-end layout and wiring stage. The wiring delay of the same metal layer (such as the M2 and M3 metal layers commonly used in the processor core area) is linearly related to the length. By controlling the difference in wiring length between different branches, equal delay can be achieved.

[0029] During implementation, one or more combinations of methods can be selected based on the processor's area constraints and timing budget to ensure the accuracy of the delay arithmetic distribution and the feasibility of the process.

[0030] S102. A clock multiplexing unit is configured before the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths by means of a selection signal.

[0031] like Figure 2 As shown, Figure 2 This is a schematic diagram of the clock multiplexing unit provided in an embodiment of the present invention. The clock multiplexing unit is a crucial component in this embodiment for enabling flexible clock path selection. Deployed before the IP core clock input interface, the clock multiplexing unit is based on the hierarchical design logic of the processor clock network. This is because the processor clock system is divided into a global clock distribution network and an IP core local clock domain. This configuration ensures that all candidate clock paths pass through a unified switching unit before entering the IP core, avoiding additional interference or delay deviations introduced by the clock signal within the IP core. Simultaneously, it facilitates centralized management of the IP core's clock input without altering the already fixed clock receiving and distribution logic within the IP core, aligning with the conventional process of processor IP core reuse and backend integration.

[0032] The clock multiplexing unit constructs an independent clock path for each branch of the parallel clock tree. Essentially, it achieves signal selection through an internal switch array, while ensuring the signal integrity of each path to avoid introducing new timing jitter when switching clock paths.

[0033] In step S102, the selection signal of the clock multiplexer unit is set by at least one of the following drivers: chip input / output module, top-level control logic, or configuration register. All three driver types are suitable for the needs of different stages of processor development and application, and conform to the conventional design specifications of processor control logic. They can be selected and used as needed during implementation.

[0034] S103. After the processor circuit is fabricated, timing tests are performed, and the timing anomaly identification results of the IP core are obtained.

[0035] Unlike existing technologies, this invention performs timing tests after the processor circuit is fabricated. This is because there are inherent deviations between the actual behavior of silicon wafers and the previous simulation and STA analysis. Relying solely on the previous verification cannot fully cover all timing risks. Therefore, it is necessary to accurately capture the actual timing status of the IP core through post-silicon timing tests.

[0036] In step S103, the timing test includes at least one of functional testing, timing-specific testing, or silicon debugging.

[0037] The three testing methods cover the timing verification requirements after the processor is fabricated from different dimensions and are adapted to different testing scenarios. Functional testing focuses on the implementation of the core functions of the IP core. By inputting preset test vectors, it monitors whether the output results meet the design expectations and indirectly judges whether there are timing anomalies. The timing-specific test is designed for clock timing characteristics. Through a dedicated test circuit, it accurately measures key parameters such as clock arrival time, clock skew, and timing margin, which can directly pinpoint the specific location of timing anomalies. Silicon debugging is the core method for locating problems after tape-out. By observing the waveforms of the clock and data signals inside the IP core in real time through the chip's built-in debugging interface, it can capture instantaneous timing anomalies in dynamic working scenarios.

[0038] In step S103, the timing anomaly identification result includes whether the IP core has a hold-time violation and potential functional anomalies related to hold-time.

[0039] Specifically, the adjustment of the processor circuit clock path delay proposed in this embodiment of the invention mainly targets the adjustment of IP core hold-time violations and related potential functional anomalies. From the perspective of the core priority of processor timing constraints, hold-time violations are more destructive and more covert to the correctness of IP core functions than setup-time violations. This embodiment of the invention identifies hold-time violation anomalies so as to make targeted adjustments in the future.

[0040] S104. Determine the target delay based on the timing anomaly identification result, adjust the selection signal of the clock multiplexing unit to switch the clock path, so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay.

[0041] Step S104 relies on the latency-increasing parallel clock tree branches constructed in S101 and the clock multiplexing unit configured in S102 to precisely switch clock paths, thereby achieving post-silicon timing repair. Specifically, after processor tape-out, the actual timing deviations of the IP cores (such as hold-time violations) are fixed physical characteristics that cannot be completely resolved through software optimization. Since S101 has pre-built clock tree branches with multiple latency gradients, the core of S104 is to determine the amount of latency to be compensated (target latency) based on the degree of anomaly, and then adjust the clock arrival time of the IP cores to match the target latency by switching clock paths, ultimately eliminating timing anomalies. The target latency is calculated based on the test data from S103 (such as the value of insufficient hold-time margin and the magnitude of clock skew).

[0042] In step S104, when the timing anomaly identification result indicates that the IP core has a hold-time violation or potential functional anomaly, the selection signal is adjusted to switch to the clock path corresponding to the parallel clock tree branch with a larger delay.

[0043] The core synchronization unit inside the processor IP core maintains the constraint that the data signal must remain stable within the minimum time window after the clock trigger edge. When a hold-time violation or potential risk occurs, it is essentially because the data signal changes prematurely after the clock trigger edge. In this case, it is necessary to increase the clock path delay to delay the time it takes for the clock signal to reach the IP core synchronization unit, thereby lengthening the stable window of the data signal after the clock trigger edge and compensating for the insufficient hold-time timing margin.

[0044] The engineering feasibility of post-silicon timing path delay adjustment has been achieved in the following three aspects: First, the parallel clock tree branches constructed in step S101 have an arithmetic delay distribution. The delay difference between the path with a larger delay and the current path is fixed and quantifiable. The change in timing margin after switching can be accurately predicted, avoiding over-adjustment or under-adjustment. Secondly, the switching action is achieved by adjusting the selection signal of the clock multiplexer unit. The signal driving method (chip I / O, top-level control logic, configuration register) can be adapted to different scenarios. During the debugging stage, the switching can be manually performed and the effect verified by external devices. During the mass production stage, the optimal path can be locked by the configuration register, which meets the needs of the processor from debugging to mass production. Third, the switch only changes the clock arrival time of the IP core, without involving the internal logic of the IP core (such as the connection relationship between the arithmetic unit and the storage unit) and the data path, and will not introduce new functional risks. At the same time, it avoids the high cost and long cycle problems of traditional repair methods.

[0045] Therefore, the method proposed in this embodiment of the invention can not only solve the hold-time violation of the IP core, but also reduce the risk of timing anomaly recurrence, and ensure the stability and robustness of the IP core and the entire processor circuit.

[0046] The beneficial effects achieved by this invention are that it proposes a method for adjusting the clock path delay of a processor circuit. This method avoids re-wafering caused by hold-time violations by constructing adjustable delay clock branches and configuring selection units. While saving costs in multi-project wafer scenarios, it can compensate for silicon wafer and simulation deviations, and improve the correctness and robustness of IP core functions. At the same time, the adjustment of timing path delay does not require large-scale modification of the internal logic of the IP, has low intrusion into the existing process, can adapt to multi-dimensional environmental changes, and improves the stability of complex scenarios.

[0047] Example 2 This invention also provides a processor circuit clock path delay adjustment system 200, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a processor circuit clock path delay adjustment system provided in an embodiment of the present invention, which includes: The multi-channel clock generation module 201 is used to construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit. The selection control module 202 is used to configure a clock multiplexing unit in front of the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths through a selection signal. The test module 203 is used to perform timing tests after the processor circuit is fabricated and to obtain the timing anomaly identification results of the IP core. The adjustment module 204 is used to determine the target delay based on the timing anomaly identification result, adjust the selection signal of the clock multiplexing unit to switch the clock path, so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay.

[0048] The processor circuit clock path delay adjustment system 200 can implement the steps in the processor circuit clock path delay adjustment method in the above embodiments and achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0049] Example 3 This invention also provides a computer device, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a processor circuit clock path delay adjustment program stored in the memory 302 and executable on the processor 301.

[0050] The processor 301 calls the processor circuit clock path delay adjustment program stored in the memory 302, and executes the steps in the processor circuit clock path delay adjustment method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps: S101. Construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit.

[0051] In step S101, the delays of the multiple parallel clock tree branches are distributed in an arithmetic progression, wherein the first parallel clock tree branch is the shortest delay path, and each subsequent parallel clock tree branch gradually increases the delay by a fixed amount based on the delay of the previous branch.

[0052] By adjusting at least one of the clock tree structure, buffer levels, or wiring length of the parallel clock tree branches, the delay amounts of the different parallel clock tree branches are made to be distributed in an arithmetic progression.

[0053] S102. A clock multiplexing unit is configured before the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths by means of a selection signal.

[0054] In step S102, the selection signal of the clock multiplexer unit is driven and set by at least one of the chip input / output module, top-level control logic, or configuration register.

[0055] S103. After the processor circuit is fabricated, timing tests are performed, and the timing anomaly identification results of the IP core are obtained.

[0056] In step S103, the timing test includes at least one of functional testing, timing-specific testing, or silicon debugging.

[0057] In step S103, the timing anomaly identification result includes whether the IP core has a hold-time violation and potential functional anomalies related to hold-time.

[0058] S104. Determine the target delay based on the timing anomaly identification result, adjust the selection signal of the clock multiplexing unit to switch the clock path, so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay.

[0059] In step S104, when the timing anomaly identification result indicates that the IP core has a hold-time violation or potential functional anomaly, the selection signal is adjusted to switch to the clock path corresponding to the parallel clock tree branch with a larger delay.

[0060] The computer device 300 provided in this embodiment of the invention can implement the steps in the processor circuit clock path delay adjustment method in the above embodiment, and can achieve the same technical effect. Referring to the description in the above embodiment, it will not be repeated here.

[0061] Example 4 This invention also provides a storage medium storing a processor circuit clock path delay adjustment program. When the processor executes the processor circuit clock path delay adjustment program, it implements the various processes and steps in the processor circuit clock path delay adjustment method provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0062] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to adjusting the clock path delay of the processor circuit or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0063] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0064] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0065] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A method for adjusting the clock path delay of a processor circuit, characterized in that, Includes the following steps: S101. Construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit. S102. A clock multiplexing unit is configured before the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths by a selection signal. S103. After the processor circuit is fabricated, timing tests are performed, and the timing anomaly identification results of the IP core are obtained. S104. Determine the target delay based on the timing anomaly identification result, adjust the selection signal of the clock multiplexing unit to switch the clock path, so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay. In step S101, the delays of the multiple parallel clock tree branches are distributed in an arithmetic progression, with the first parallel clock tree branch being the shortest delay path, and each subsequent parallel clock tree branch gradually increasing the delay by a fixed amount based on the delay of the previous branch. By adjusting at least one of the clock tree structure, buffer levels, or wiring length of the parallel clock tree branches, the delay amounts of the different parallel clock tree branches are made to be distributed in an arithmetic progression.

2. The method for adjusting the clock path delay of a processor circuit according to claim 1, characterized in that, In step S102, the selection signal of the clock multiplexer unit is driven and set by at least one of the chip input / output module, top-level control logic, or configuration register.

3. The method for adjusting the clock path delay of a processor circuit according to claim 1, characterized in that, In step S103, the timing test includes at least one of functional testing, timing-specific testing, or silicon debugging.

4. The method for adjusting the clock path delay of a processor circuit according to claim 1, characterized in that, In step S103, the timing anomaly identification result includes whether the IP core has a hold-time violation and potential functional anomalies related to hold-time.

5. The method for adjusting the clock path delay of a processor circuit according to claim 4, characterized in that, In step S104, when the timing anomaly identification result indicates that the IP core has a hold-time violation or potential functional anomaly, the selection signal is adjusted to switch to the clock path corresponding to the parallel clock tree branch with a larger delay.

6. A clock path delay adjustment system for a processor circuit, characterized in that, include: A multi-channel clock generation module is used to construct multiple parallel clock tree branches with increasing delay at the clock root node of the processor circuit. The selection control module is used to configure a clock multiplexing unit in front of the clock input interface of the IP core of the processor circuit. The clock input side of the clock multiplexing unit is connected to multiple branches of the parallel clock tree, and clock paths corresponding to different branches of the parallel clock tree are formed inside the clock multiplexing unit. The clock multiplexing unit is used to switch different clock paths through a selection signal. The testing module is used to perform timing tests after the processor circuit is fabricated and to obtain the timing anomaly identification results of the IP core. An adjustment module is used to determine the target delay based on the timing anomaly identification result, and adjust the selection signal of the clock multiplexing unit to switch the clock path so that the delay of the parallel clock tree branch corresponding to the clock path is the same as the target delay. The multi-channel clock generation module distributes the delays of multiple parallel clock tree branches in an arithmetic progression. The first parallel clock tree branch is the shortest delay path, and each subsequent parallel clock tree branch gradually increases the delay by a fixed amount based on the delay of the previous branch. By adjusting at least one of the clock tree structure, buffer levels, or wiring length of the parallel clock tree branches, the delay amounts of the different parallel clock tree branches are made to be distributed in an arithmetic progression.

7. A computer device, characterized in that, include: The processor includes a memory, a processor, and a processor circuit clock path delay adjustment program stored in the memory and executable on the processor. When the processor executes the processor circuit clock path delay adjustment program, it implements the steps in the processor circuit clock path delay adjustment method as described in any one of claims 1-5.

8. A storage medium, characterized in that, The storage medium stores a program for adjusting the clock path delay of the processor circuit. When the processor executes the program for adjusting the clock path delay of the processor circuit, it implements the steps in the method for adjusting the clock path delay of the processor circuit as described in any one of claims 1-5.

Images