一种LED显示装置的驱动控制系统及其控制方法
By using multiple GPIO ports in the LED display device and binding them one-to-one with the DMA controller, and by utilizing the synchronous trigger signal of the master timer and the coordinated drive of the PWM module, the problems of image tearing and misalignment and display noise flicker when splicing multiple HUB interfaces are solved, and high-stability data transmission is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HUIDU TECH
- Filing Date
- 2026-05-07
- Publication Date
- 2026-07-17
AI Technical Summary
In the prior art, when multiple DMA controllers control multiple GPIO ports respectively, the data signal clock becomes skewed, resulting in image tearing and misalignment at the screen seams, as well as the data signal and clock signal becoming out of sync, causing display noise and flicker.
A parallel architecture is adopted, in which multiple GPIO ports are bound one-to-one with multiple DMA controllers. All DMA controllers are triggered simultaneously by a master timer's synchronous trigger signal. Combined with the clock signal synchronous drive of the PWM module, it is ensured that data transfer and clock signals are kept in phase synchronization at the hardware level.
It achieves nanosecond-level synchronization of data signals output from multiple GPIO ports, eliminating image tearing and misalignment, improving data transmission stability, and avoiding display noise and flicker.
Smart Images
Figure CN122135658B_ABST