Method for manufacturing a semiconductor integrated device and semiconductor integrated device
By simultaneously forming the pre-drilled holes and shallow trenches during the etching process, the problem of the difference in etching depth between the IPS and BCD processes for the pre-drilled holes was solved, resulting in a reduction in process steps and costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG ELECTRONICS (SHAOXING) CORP
- Filing Date
- 2026-05-06
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the difference in the etching depth of the plug holes between IPS and BCD processes makes them impossible to merge, increasing the number of process steps and manufacturing costs.
The first etching process simultaneously forms the plug pre-reserved hole and shallow trench. The second etching process deepens the shallow trench while forming the gate trench. The third etching process simultaneously forms the plug hole, reducing independent etching steps and combining the formation of the plug hole.
This technology enables the simultaneous formation of plug holes, reduces process steps, shortens the production cycle, and lowers manufacturing costs.
Smart Images
Figure CN122138453B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor integrated device and the semiconductor integrated device itself. Background Technology
[0002] The IPS (Intelligent Power Switch) process integrates BCD (Bipolar-CMOS-DMOS) and SGT (Shield Gate Trench) processes. In the SGT process, to form a vertical conductive channel electrically connected to the source region and to short-circuit the source region to eliminate parasitic BJT (Bipolar Junction Transistor) effects, the source conductive plug needs to penetrate the interlayer dielectric layer and continue downwards, penetrating the source region and reaching deep into the body region. In contrast, other conductive plugs (CTs), such as those in the BCD process, only need to penetrate the interlayer dielectric layer to form an ohmic contact with the active region of the device. Therefore, the etching process for forming the plug hole has a very limited etching depth on the substrate, typically only etching to a depth of about 0.03 μm or less into the silicon substrate.
[0003] Because the etching depth of the through-holes in SGT devices differs significantly from that of other through-holes, the processes cannot be combined, meaning they cannot be completed simultaneously in the same etching process. Separate etching processes not only increase the number of process steps, extending the production cycle, but also require additional photomasks, leading to increased manufacturing costs. Summary of the Invention
[0004] In view of the above, this application provides a method for fabricating a semiconductor integrated device and a semiconductor integrated device to solve at least one problem existing in the background art.
[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor integrated device, comprising:
[0006] A semiconductor material layer is provided, the semiconductor material layer having a first device region and a second device region;
[0007] Perform a first etching process to simultaneously form a first plug pre-reserved hole and a first shallow trench. The first plug pre-reserved hole is located at the preset formation position of the source conductive plug in the first device area, and the first shallow trench is located at the preset formation position of the deep trench isolation structure in the second device area.
[0008] A second etching process is performed to simultaneously form a gate trench and a first deep trench. The gate trench is located at a preset formation position of the gate trench in the first device region. The first deep trench is located at the same position as the first shallow trench, and the first deep trench is formed by increasing the depth of the first shallow trench using the second etching process.
[0009] A first dielectric layer is formed on the semiconductor material layer, the first dielectric layer covering the gate trench and the inner wall of the first deep trench and filling the first plug pre-reserved hole;
[0010] A gate structure is formed in the gate trench, a deep trench isolation structure is formed in the first deep trench, and a body region is formed in the semiconductor material layer next to the gate trench, and a source region is formed in the body region. The first plug pre-reserved hole penetrates the source region and extends into the body region.
[0011] A second dielectric layer is formed on the semiconductor material layer;
[0012] A third etching process is performed to simultaneously form a first plug hole and a second plug hole. The first plug hole is located in the same position as the first plug reserved hole. The first plug hole is formed by etching through the second dielectric layer and removing the portion of the first dielectric layer located in the first plug reserved hole using the third etching process. The second plug hole is located in the second device region.
[0013] In conjunction with the first aspect of this application, in an optional embodiment, the opening area of the first plug pre-drilled hole is smaller than the opening area of the first shallow trench; the depth of the first plug pre-drilled hole is smaller than the depth of the first shallow trench.
[0014] In conjunction with the first aspect of this application, in an optional embodiment, the ratio of the line width of the first plug pre-drilled hole to the line width of the first shallow groove is 0.1 to 0.2.
[0015] In conjunction with the first aspect of this application, in an optional embodiment, the opening area of the gate trench is smaller than the opening area of the first shallow trench; and the depth of the gate trench is smaller than the depth difference between the first deep trench and the first shallow trench.
[0016] In conjunction with the first aspect of this application, in an optional embodiment, the ratio of the linewidth of the gate trench to the linewidth of the first shallow trench is 0.5 to 0.7.
[0017] In conjunction with the first aspect of this application, in an optional embodiment, the first device region is a device region for performing SGT process;
[0018] Forming a gate structure within the gate trench includes: forming a shielding gate, a control gate, a third dielectric layer that isolates the shielding gate and the control gate, and a gate dielectric layer that isolates the control gate and the semiconductor material layer within the gate trench;
[0019] The first dielectric layer is used to isolate the shielding gate and the semiconductor material layer.
[0020] In conjunction with the first aspect of this application, in an optional embodiment, the second device region is a device region for performing a BCD process;
[0021] Before forming a second dielectric layer on the semiconductor material layer, the method further includes: forming an LDMOS device in the second device region;
[0022] The LDMOS device includes a well region located within the semiconductor material layer, wherein the depth of the first deep trench is greater than the depth of the well region.
[0023] In conjunction with the first aspect of this application, in an optional embodiment, the second plug hole includes a plurality of holes for communicating with the source, drain and gate of the LDMOS device, and the plurality of holes included in the second plug hole are formed synchronously with the first plug hole.
[0024] In conjunction with the first aspect of this application, in an optional embodiment, the method further includes: simultaneously filling the first plug hole and the second plug hole with conductive material.
[0025] Secondly, embodiments of this application provide a semiconductor integrated device, which is prepared using the semiconductor integrated device preparation method described in any one of the first aspects.
[0026] Compared with the prior art, this application has the following beneficial effects: The semiconductor integrated device fabrication method and semiconductor integrated device provided in the embodiments of this application simultaneously form a first plug pre-reserved hole and a first shallow trench using a first etching process, and deepen the first shallow trench to form a first deep trench using a second etching process while forming a gate trench. Thus, it is used to form a deep trench isolation structure. The first deep trench (DTI) of the isolation layer is formed through two etching steps. The first etching step can be regarded as the preliminary etching step of the first deep trench. In this embodiment, the preliminary etching step of the first deep trench is used to complete the etching of the reserved hole of the source conductive plug (i.e., the first plug reserved hole), which provides a basis for the simultaneous etching of the first plug hole and the second plug hole in the third etching step. During the formation of the first dielectric layer, the first plug reserved hole is filled, which can protect the first plug reserved hole and prevent the subsequent processes from damaging it. On the other hand, it can facilitate the smooth exposure of the first plug reserved hole after the third etching step etches through the second dielectric layer. Finally, the first plug hole and the second plug hole are formed simultaneously using the third etching step, which combines the two types of plug holes that originally needed to be etched independently by different photomasks into a simultaneous formation, reducing process steps, shortening the production cycle, saving photomasks and reducing manufacturing costs.
[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0029] Figure 1 A schematic flowchart illustrating the fabrication method of the semiconductor integrated device provided in this application embodiment;
[0030] Figure 2 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after the semiconductor material layer has been provided;
[0031] Figure 3 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after performing the first etching process;
[0032] Figure 4 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after performing the second etching process;
[0033] Figure 5 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after the formation of the first dielectric layer;
[0034] Figure 6 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after forming the gate structure and deep trench isolation structure;
[0035] Figure 7 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after forming each doped region and the second gate structure;
[0036] Figure 8 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after the formation of the second dielectric layer;
[0037] Figure 9 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after performing the third etching process;
[0038] Figure 10 A schematic cross-sectional view of the semiconductor integrated device fabrication method provided in this application after the formation of conductive plugs and wiring layers;
[0039] Figure 11 This is a schematic cross-sectional view of the semiconductor integrated device fabrication method after the formation of the second dielectric layer in the related technology;
[0040] Figure 12 This is a schematic cross-sectional view of the semiconductor integrated device fabrication method after the first through-hole etching process is performed;
[0041] Figure 13 This is a schematic cross-sectional view of the semiconductor integrated device fabrication method after performing the second insertion hole etching process.
[0042] Explanation of reference numerals in the attached figures:
[0043] 110 - Semiconductor material layer; 1001 - First device region; 1002 - Second device region; 111 - First surface; 112 - Second surface; 1210 - First plug pre-drilled hole; 1300 - First shallow trench; 130 - First deep trench; 131 - Deep trench dielectric layer; 132 - Deep trench filling material layer; 140 - Gate trench; 141 - Isolation dielectric layer; 142 - Shielding gate; 143 - Third dielectric layer; 144 - Gate dielectric layer; 145 - Control gate; 150 - First dielectric layer; 161-Trap region; 162-Drift region; 163-Second source region; 164-Second drain region; 170-Second gate structure; 171-Second gate; 181-Body region; 182-Source region; 190-Second dielectric layer; 121-First plug hole; 122-Second plug hole; 201-Source conductive plug; 202-Second conductive plug; 211-First source electrode pattern; 221-Second source electrode pattern; 222-Second drain electrode pattern; 223-Second gate electrode pattern. Detailed Implementation
[0044] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.
[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0046] In the accompanying drawings, for clarity, the dimensions of the structures and their relative dimensions may be exaggerated. The same reference numerals denote the same structural features throughout.
[0047] When structures are referred to as being "on," "adjacent to," "connected to," or "coupled to" other structures, they may be directly on, adjacent to, connected to, or coupled to other structures, or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other structures, there are no intervening structures. Although the terms first, second, third, etc., may be used to describe structures or parts, these terms are only used to distinguish one structure or part from another. Therefore, without departing from the teachings of this application, the first structure or part discussed below may be referred to as the second structure or part. And the discussion of the second structure or part does not imply that the first structure or part necessarily exists in this application.
[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated feature but do not exclude the presence or addition of one or more other features. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0050] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0051] This application provides a method for fabricating a semiconductor integrated device. Please refer to [link / reference]. Figure 1 The method includes:
[0052] S01, provides a semiconductor material layer, the semiconductor material layer having a first device region and a second device region;
[0053] S02, perform the first etching process to simultaneously form the first plug pre-reserved hole and the first shallow trench. The first plug pre-reserved hole is located at the preset formation position of the source conductive plug in the first device area, and the first shallow trench is located at the preset formation position of the deep trench isolation structure in the second device area.
[0054] S03, perform the second etching process to simultaneously form the gate trench and the first deep trench. The gate trench is located at the preset formation position of the gate trench in the first device region. The first deep trench is at the same position as the first shallow trench, and the first deep trench is formed by increasing the depth of the first shallow trench using the second etching process.
[0055] S04, a first dielectric layer is formed on the semiconductor material layer, the first dielectric layer covers the gate trench and the inner wall of the first deep trench and fills the first plug pre-reserved hole;
[0056] S05, a gate structure is formed in the gate trench, a deep trench isolation structure is formed in the first deep trench, and a body region is formed in the semiconductor material layer next to the gate trench, and a source region is formed in the body region. The first plug pre-reserved hole penetrates the source region and extends into the body region.
[0057] S06, a second dielectric layer is formed on the semiconductor material layer;
[0058] S07, perform the third etching process to simultaneously form the first plug hole and the second plug hole. The first plug hole is in the same position as the first plug reserved hole. The first plug hole is formed by etching through the second dielectric layer and removing the portion of the first dielectric layer located in the first plug reserved hole using the third etching process. The second plug hole is located in the second device region.
[0059] Understandably, in this embodiment, the first etching process simultaneously forms the first plug pre-reserved hole and the first shallow trench. The second etching process deepens the first shallow trench while forming the gate trench to form the first deep trench. Thus, the first deep trench used to form the deep trench isolation structure is formed through two etching processes. The first etching process can be considered as the preliminary etching process for the first deep trench. This embodiment utilizes this preliminary etching process for the first deep trench to complete the etching of the source conductive plug pre-reserved hole (i.e., the first plug pre-reserved hole), facilitating the simultaneous etching of the first plug hole and the second plug hole in the subsequent third etching process. The first insertion hole is filled during the formation of the first dielectric layer. This protects the first insertion hole from damage during subsequent processes and facilitates its exposure after the third etching process penetrates the second dielectric layer. Finally, the first and second insertion holes are formed simultaneously using the third etching process. This combines the two types of insertion holes, which originally required separate etching using different photomasks, into a single process, reducing process steps, shortening the production cycle, saving photomasks, and lowering manufacturing costs.
[0060] Below, we will combine Figures 2 to 10 The schematic diagram of the cross-sectional structure of the semiconductor integrated device shown in the fabrication process provides a further detailed description of the embodiments and beneficial effects of this application.
[0061] First, please refer to Figure 2 A semiconductor material layer 110 is provided, the semiconductor material layer 110 having a first device region 1001 and a second device region 1002.
[0062] The semiconductor material layer 110 can be an epitaxial layer (EPI layer) formed by epitaxial growth on a growth substrate. Although the growth substrate is not shown in the figure, it can be understood that the growth substrate is located below the epitaxial layer. The epitaxial layer and the growth substrate have the same conductivity type; for example, the growth substrate is an N-type substrate, and the epitaxial layer is an N EPI layer. Of course, this application is not limited to this. Any semiconductor material layer that can provide a basis for the formation of subsequent device structures should be understood as the semiconductor material layer defined in this application. Therefore, the semiconductor material layer 110 may sometimes be referred to as a substrate, or the semiconductor material layer 110 and the growth substrate may be referred to together as a substrate. The first conductivity type is not limited to N-type; the embodiments of this application do not exclude the case where it is P-type.
[0063] The semiconductor material layer 110 includes a first surface 111 and a second surface 112 that are opposite to each other. Depending on the formation location of the device structure, the first surface 111 and the second surface 112 can also be referred to as the upper surface and the lower surface, or the top surface and the bottom surface, respectively.
[0064] Ignoring the flatness of the first surface 111 and the second surface 112, the direction perpendicular to the first surface 111 and the second surface 112 of the semiconductor material layer 110 is defined as the thickness direction. The thickness direction is also the stacking direction for subsequent deposition of various structural layers on the semiconductor material layer 110, or the height direction of the semiconductor device; for structures formed by downward processes such as trenches or doped regions, this direction can be called the depth direction. The plane containing the first surface 111 and / or the second surface 112 of the semiconductor material layer 110 is perpendicular to the thickness direction.
[0065] The semiconductor material layer 110 includes a first device region 1001 and a second device region 1002. In some specific applications, the first device region 1001 is a device region for performing SGT (Surface Mount Technology) processes, and the second device region 1002 is a device region for performing BCD (Browser-Chip-Device) processes.
[0066] The material of the semiconductor material layer 110 can be selected according to the actual device requirements, such as common semiconductor materials like silicon (Si), and this application does not make specific limitations in this regard.
[0067] Next, please refer to Figure 3 Perform the first etching process to simultaneously form the first plug pre-drilled hole 1210 and the first shallow trench 1300.
[0068] The first etching process can be considered as the preliminary etching process (or Zero ET) of the first deep trench. In some specific embodiments, an LDMOS (Lateral Double-diffused MOS) device will subsequently be formed in the second device region 1002. The LDMOS device includes a well region 161 located within the semiconductor material layer 110 (see reference). Figure 7 ).like Figure 7 As shown, the depth of the first deep trench 130 is greater than the depth of the well region 161, thereby completely isolating the active region of the LDMOS device from other devices.
[0069] Considering that the depth of the DTI alone is insufficient to block the well region 161, a preliminary etching process is first performed at the preset formation location of the DTI, and then a second etching process is performed at the same location, so that the depth of the first deep trench 130 is formed by the superposition of the two etching processes, in order to meet the depth requirements of the DTI in the LDMOS device.
[0070] As an optional specific implementation, the opening area of the first plug pre-drilled hole 1210 is smaller than the opening area of the first shallow groove 1300; the depth of the first plug pre-drilled hole 1210 is smaller than the depth of the first shallow groove 1300.
[0071] Alternatively, the ratio of the line width of the first plug pre-drilled hole 1210 to the line width of the first shallow groove 1300 is 0.1 to 0.2.
[0072] The depth of the first plug pre-drilled hole 1210 is 0.3 μm or more. Thus, the plug hole (first plug hole) of the subsequently formed SGT device extends more than 0.3 μm from the first surface 111 of the semiconductor material layer 110 into the interior of the semiconductor material layer 110.
[0073] Next, please refer to Figure 4 A second etching process is performed to simultaneously form the gate trench 140 and the first deep trench 130.
[0074] Within the same first device region 1001, there can be multiple gate trenches 140; two are shown as an example in the figure. The first plug pre-reserved hole 1210 is located between two adjacent gate trenches 140, and the first plug pre-reserved hole 1210 is spaced apart from any gate trench 140.
[0075] The first deep trench 130 is located at the same position as the first shallow trench 1300. By continuing to etch downwards at the position of the first shallow trench 1300, the depth of the first shallow trench 1300 is increased, and finally the first deep trench 130 is obtained.
[0076] As an optional specific implementation, the opening area of the gate trench 140 is smaller than the opening area of the first shallow trench 1300. The depth of the gate trench 140 is smaller than the depth difference between the first deep trench 130 and the first shallow trench 1300.
[0077] Further optionally, the ratio of the linewidth of the gate trench 140 to the linewidth of the first shallow trench 1300 is 0.5 to 0.7.
[0078] In some embodiments, the mask opening pattern corresponding to the first deep trench 130 in the second etching process is the same as the mask opening pattern corresponding to the first shallow trench 1300 in the first etching process. Therefore, the opening area of the gate trench 140 is also smaller than the opening area of the corresponding first deep trench 130. The ratio of the linewidth of the gate trench 140 to the linewidth of the first deep trench 130 is also 0.5 to 0.7.
[0079] In other embodiments, the mask opening pattern corresponding to the first deep trench 130 in the second etching step may also be different from the mask opening pattern corresponding to the first shallow trench 1300 in the first etching step; for example, the former may be located within the boundary range of the latter. Therefore, the area of the mask opening pattern corresponding to the first deep trench 130 in the second etching step is smaller than the area of the mask opening pattern corresponding to the first shallow trench 1300 in the first etching step. However, the opening area of the gate trench 140 is still smaller than the opening area of the corresponding first deep trench 130. The ratio of the linewidth of the gate trench 140 to the linewidth of the first deep trench 130 can still be in the range of 0.5 to 0.7.
[0080] Next, please refer to Figure 5 A first dielectric layer 150 is formed on the semiconductor material layer 110. The first dielectric layer 150 covers the inner walls of the gate trench 140 and the first deep trench 130 and fills the first plug pre-drilled hole 1210.
[0081] The first dielectric layer 150 can also be referred to as an insulating layer, and its material is, for example, silicon oxide. In some specific applications, the first dielectric layer 150 can be a field oxide layer (FOX). The thickness of the first dielectric layer 150 is about 3000 Å, which is sufficient to fill the first plug pre-drilled hole 1210.
[0082] As an optional specific implementation, the first device region 1001 is a device region for performing the SGT process; the first dielectric layer 150 is used to isolate the semiconductor material layer 110 and the shielding gate to be formed subsequently.
[0083] Next, please refer to Figure 6 A gate structure is formed within the gate trench 140, and a deep trench isolation structure is formed within the first deep trench 130.
[0084] The formation processes of the gate structure and the deep trench isolation structure will be described separately below. However, it should be understood that the order in which they are described does not constitute a special restriction on the order in which these structures are formed. The specific process sequence can be determined according to actual needs.
[0085] For the gate structure, in some specific applications, forming the gate structure may include: forming a shielding gate 142, a control gate 145, a third dielectric layer 143 that isolates the shielding gate 142 and the control gate 145, and a gate dielectric layer 144 that isolates the control gate 145 and the semiconductor material layer 110 within the gate trench 140.
[0086] Specifically, after forming the first dielectric layer 150, a shielding gate material, such as polysilicon, can be deposited within the gate trench 140. Next, a portion of the shielding gate material is removed to form a control gate receiving trench, with the remaining shielding gate material forming the shielding gate 142. Understandably, the control gate receiving trench is located within the gate trench 140, specifically, in the upper half of the gate trench 140. Next, a third dielectric layer 143 can be formed within the control gate receiving trench. The third dielectric layer 143 serves as an inter-gate oxide (IPO) layer isolating the shielding gate 142 and the control gate 145. The material of the third dielectric layer 143 is, for example, silicon oxide. Next, excess material of the third dielectric layer 143 is removed, and then a gate dielectric layer 144 is formed. The gate dielectric layer 144 serves as an insulator between the control gate 145 and the inner wall of the gate trench 140. The material of the gate dielectric layer 144 is, for example, silicon dioxide. Finally, the control gate 145 is filled. The control gate 145 is made of polysilicon, specifically N-type polysilicon. In the final gate structure, the portion of the first dielectric layer 150 located within the gate trench 140 serves as an isolation dielectric layer 141 to isolate the shield gate 142 and the semiconductor material layer 110.
[0087] In some specific applications, forming a deep trench isolation structure may include: after forming a first dielectric layer 150, depositing a deep trench filling material layer 132 in the first deep trench 130, the material of which is, for example, deposited polysilicon; and the portion of the first dielectric layer 150 located in the first deep trench 130 will serve as the deep trench dielectric layer 131.
[0088] As an optional implementation, the deep trench filling material layer 132 and the shielding gate material used to form the shielding gate 142 are formed in the same deposition process. Specifically, during the process of depositing the shielding gate material in the gate trench 140, the shielding gate material is also filled into the first deep trench 130. During the subsequent removal of part of the shielding gate material and the formation of the third dielectric layer 143, the gate dielectric layer 144, and the control gate 145, the first deep trench 130 can be in a shielded and protected state, so that the corresponding process is not performed in the first deep trench 130, but the filled shielding gate material continues to remain to form the deep trench filling material layer 132.
[0089] Next, please refer to Figure 7 A body region 181 is formed in the semiconductor material layer 110 adjacent to the gate trench 140, and a source region 182 is formed in the body region 181.
[0090] Body region 181 is, for example, P-type, and can also be called P body region. Source region 182 is, for example, N-type, and specifically N+ region.
[0091] In actual fabrication, the body region 181 and the source region 182 can be formed by ion implantation. The ion implantation window forming the body region 181 and the source region 182 can surround the first plug pre-reserved hole 1210. Although the first plug pre-reserved hole 1210 is filled with the first dielectric layer 150, ions will be implanted from around the first plug pre-reserved hole 1210 into the semiconductor material layer 110. However, during the annealing and bonding process after implantation, the ions will diffuse to the area below the first plug pre-reserved hole 1210, so the body region 181 formed in the end can also include the portion located below the first plug pre-reserved hole 1210.
[0092] like Figure 7 As shown, after the body region 181 and the source region 182 are formed, the first plug pre-drilled hole 1210 penetrates the source region 182 and extends into the body region 181. In this way, the source region 182 and the body region 181 are in direct contact with the outer wall of the first plug pre-drilled hole 1210, thereby making direct contact with the source conductive plug that will be formed subsequently.
[0093] It should be noted that, although Figure 6 and Figure 7 The diagram shows the formation of the gate structure and deep trench isolation structure first, followed by the formation of the body region 181 and the source region 182. However, this application is not limited to this, and those skilled in the art can adjust the formation order of each structure according to actual needs.
[0094] Please continue to refer to this. Figure 7 The method may further include: forming an LDMOS device in the second device region 1002.
[0095] LDMOS devices can be surrounded by deep trench isolation structures to isolate the active regions of LDMOS devices from the active regions of other devices.
[0096] The LDMOS device includes a well region 161 located within a semiconductor material layer 110, the depth of which is less than the depth of the first deep trench 130. The well region 161 is, for example, a P-type region, and may also be referred to as a PW (P Well) region.
[0097] The LDMOS device also includes a drift region 162, a second source region 163, and a second drain region 164 located within the semiconductor material layer 110, and a second gate structure 170 located on the semiconductor material layer 110. The drift region 162 is, for example, N-type, and may also be referred to as an N-drift region. The drift region 162 may be located within the well region 161, but this application is not limited thereto. The second source region 163 and the second drain region 164 are both, for example, N-type, and specifically N+ regions. The second source region 163 is located within the well region 161; the second drain region 164 is located within the drift region 162.
[0098] It should be understood that, in order to distinguish them from the source and drain structures of SGT devices, the source and drain regions in LDMOS devices are referred to as the second source region 163 and the second drain region 164, respectively. Similarly, the gate structure in LDMOS devices is referred to as the second gate structure 170, mainly to distinguish it from the gate structure in SGT devices. For the sake of simplicity, the second source region 163, the second drain region 164, the second gate structure 170, and the second gate 171 may sometimes be directly referred to as the source, drain, gate structure, and gate of the LDMOS device.
[0099] In actual fabrication, the well region 161, drift region 162, second source region 163, and second drain region 164 can be formed by ion implantation. The depths of the well region 161, drift region 162, second source region 163, and second drain region 164 are all less than the depth of the first deep trench 130.
[0100] The second gate structure 170 includes a second gate 171 located on the semiconductor material layer 110, and a second gate dielectric layer located between the second gate 171 and the semiconductor material layer 110. Furthermore, the second gate structure 170 also includes sidewall structures located on the sidewalls of the second gate 171. The material of the second gate 171 is, for example, polysilicon. The material of the second gate dielectric layer and / or the sidewall structure is, for example, silicon oxide.
[0101] It should be understood that although this article first introduces the formation of the body region 181 and the source region 182, and then introduces the formation of the LDMOS device, the order of introduction does not constitute a special restriction on the order of formation of these structures. The specific process sequence can be determined according to actual needs.
[0102] Next, please refer to Figure 8 A second dielectric layer 190 is formed on the semiconductor material layer 110.
[0103] The second dielectric layer 190 can also be referred to as an interlayer dielectric layer (ILD). The material of the second dielectric layer 190 is, for example, silicon oxide. The material of the second dielectric layer 190 can be the same as that of the first dielectric layer 150.
[0104] Next, please refer to Figure 9 The third etching process is performed to simultaneously form the first plug hole 121 and the second plug hole 122.
[0105] The first plug hole 121 is located at the same position as the first plug reserved hole 1210. During the third etching process, the second dielectric layer 190 at this location is gradually etched until it is etched through, exposing the first dielectric layer 150 filling the first plug reserved hole 1210. The etching continues downward, and the first dielectric layer 150 filling the first plug reserved hole 1210 is removed, thereby obtaining the first plug hole 121 that not only penetrates the second dielectric layer 190, but also extends into the semiconductor material layer 110, specifically penetrating the source region 182 and extending into the body region 181.
[0106] The second plug hole 122 located in the second device region 1002 penetrates the second dielectric layer 190. The second plug hole 122 generally refers to a plug hole located in the second device region 1002 used to conduct electricity out of the device within the second device region 1002; therefore, the second plug hole 122 may represent multiple plug holes. In some embodiments, the second plug hole 122 includes a hole communicating with the source of an LDMOS device (hereinafter referred to as the second source plug hole), and / or a hole communicating with the drain of an LDMOS device (hereinafter referred to as the second drain plug hole). The second source plug hole and the second drain plug hole respectively expose the semiconductor material layer 110, and specifically expose the second source region 163 and the second drain region 164, respectively. Because the third etching process has a high etching selectivity for the second dielectric layer 190 and the semiconductor material layer 110, the etching depth of the third etching process on the semiconductor material layer 110 is very limited. In a specific example where the semiconductor material layer 110 is made of silicon, the second source plug and the second drain plug extend from the first surface 111 of the semiconductor material layer 110 to a depth not exceeding 0.03 μm into the interior of the semiconductor material layer 110. Furthermore, as... Figure 9 As shown, the second gate plug 122 may also include a hole communicating with the gate of the LDMOS device (hereinafter referred to as the second gate plug hole), which exposes the gate of the LDMOS device (i.e., the second gate 171). Similarly, because the third etching process has a high etching selectivity for the materials of the second dielectric layer 190 and the second gate 171, the etching depth of the third etching process for the second gate 171 is also very limited.
[0107] As an optional specific implementation, the second plug hole 122 includes a plurality of holes for communicating with the source, drain, and gate of the LDMOS device, respectively. Thus, each plug hole of the LDMOS device—the second source plug hole, the second drain plug hole, and the second gate plug hole—is formed simultaneously in the third etching process.
[0108] In addition, for the first device region 1001, besides forming the first insertion hole 121 through the third etching process, insertion holes for conducting electricity to other electrodes of the device in the first device region 1001 can also be formed simultaneously. Those skilled in the art can make reasonable choices according to actual needs.
[0109] Next, please refer to Figure 10 Conductive material is simultaneously filled into the first plug hole 121 and the second plug hole 122. In this way, a source conductive plug 201 located in the first device region 1001 and a second conductive plug 202 located in the second device region 1002 are formed, respectively.
[0110] As previously described, the second conductive plug 202 includes one or more of the following: a second source conductive plug, a second drain conductive plug, and a second gate conductive plug. Furthermore, in this step, other electrode conductive plugs of the device within the first device region 1001 may also be formed simultaneously, such as the shielding gate conductive plug and control gate conductive plug of the SGT device.
[0111] In actual fabrication, the conductive filling material can specifically include the deposition of a bottom metal thin film and the deposition of a metal material layer. The material of the bottom metal thin film can include Ti and / or TiN; exemplarily, the bottom metal thin film may include a composite stack of Ti and TiN. The bottom metal thin film can also be referred to as an adhesion layer, and the deposition of the bottom metal thin film can also be referred to as adhesion layer deposition (Glue DEP). The metal material can include W; exemplarily, the metal material is specifically W.
[0112] Next, please continue to refer to... Figure 10 A wiring layer is formed on the second dielectric layer 190.
[0113] The wiring layer may include a first source electrode pattern 211 that is conductively connected to the source conductive plug 201, and may also include a second source electrode pattern 221, a second drain electrode pattern 222, and a second gate electrode pattern 223 that are conductively connected to each of the second conductive plugs 202 located in the second device region 1002.
[0114] In actual fabrication, forming a wiring layer can specifically include: depositing a conductive metal layer; and etching the conductive metal layer to form the desired electrode pattern.
[0115] Thus, the fabrication of conductive plugs for semiconductor integrated devices was completed.
[0116] In contrast, related technologies require a two-step etching process to form the first insertion hole 121 and the second insertion hole 122, respectively. Please refer to... Figures 11 to 13 ,in Figure 11 The steps shown are the same as Figure 8Correspondingly, in related technologies, after forming an SGT structure in the first device region 1001 and an LDMOS structure in the second device region 1002, a second dielectric layer 190 is formed on the semiconductor material layer 110. Next, as... Figure 12 As shown, a first plug hole etching process is performed. Specifically, this etching process includes two stages: etching the second dielectric layer 190 and etching the semiconductor material layer 110, ultimately forming a first plug hole 121 that penetrates the second dielectric layer 190 and extends through the source region 182 into the body region 181. Next, as... Figure 13 As shown, the second through-hole etching process is performed. This process etches through the second dielectric layer 190, thereby exposing the silicon material. Understandably, both the first and second through-hole etching processes require corresponding photomasks and photolithography processes, which undoubtedly results in longer production cycles and higher manufacturing costs.
[0117] The semiconductor integrated device fabrication method provided in this application, by utilizing the preliminary etching process for forming the first deep trench 130 of the DTI, forms the first plug pre-reserved via 1210, thereby providing a basis for the simultaneous etching of the first plug via 121 and the second plug via 122 in the subsequent third etching process; by using the second etching process to deepen the etching of the first shallow trench 1300 formed in the preliminary etching process to form the first deep trench 130 while forming the gate trench 140, the method greatly saves process steps, especially photolithography. The depth of the first deep trench 130 is equal to the sum of the etching depths of the two etching processes, ensuring that the depth of the DTI is sufficient to block the well region. During the formation of the first dielectric layer 150, the thickness of the first dielectric layer 150 is sufficient to fill the first plug pre-reserved hole 1210. This protects the first plug pre-reserved hole 1210 from damage caused by subsequent processes. Furthermore, it facilitates the successful exposure of the first plug pre-reserved hole 1210 after the subsequent third etching process penetrates the second dielectric layer 190. Ultimately, this embodiment reduces the number of etching steps specifically for the first plug hole 1210 in terms of process flow, correspondingly reducing the number of photomasks. In addition, this embodiment also has the advantage of being compatible with BCD self-aligned silicide processes.
[0118] Based on this, this application also provides a semiconductor integrated device, which is prepared by the semiconductor integrated device preparation method provided in any of the above embodiments.
[0119] It should be noted that the semiconductor integrated device embodiments and the semiconductor integrated device fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.
[0120] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.
Claims
1. A method for fabricating a semiconductor integrated device, characterized in that, include: A semiconductor material layer is provided, the semiconductor material layer having a first device region and a second device region; Perform a first etching process to simultaneously form a first plug pre-reserved hole and a first shallow trench. The first plug pre-reserved hole is located at the preset formation position of the source conductive plug in the first device area, and the first shallow trench is located at the preset formation position of the deep trench isolation structure in the second device area. A second etching process is performed to simultaneously form a gate trench and a first deep trench. The gate trench is located at a preset formation position of the gate trench in the first device region. The first deep trench is located at the same position as the first shallow trench, and the first deep trench is formed by increasing the depth of the first shallow trench using the second etching process. A first dielectric layer is formed on the semiconductor material layer, the first dielectric layer covering the gate trench and the inner wall of the first deep trench and filling the first plug pre-reserved hole; A gate structure is formed in the gate trench, a deep trench isolation structure is formed in the first deep trench, and a body region is formed in the semiconductor material layer next to the gate trench, and a source region is formed in the body region. The first plug pre-reserved hole penetrates the source region and extends into the body region. A second dielectric layer is formed on the semiconductor material layer; A third etching process is performed to simultaneously form a first plug hole and a second plug hole. The first plug hole is located in the same position as the first plug reserved hole. The first plug hole is formed by etching through the second dielectric layer and removing the portion of the first dielectric layer located in the first plug reserved hole using the third etching process. The second plug hole is located in the second device region.
2. The method for fabricating a semiconductor integrated device according to claim 1, characterized in that, The opening area of the first plug pre-drilled hole is smaller than the opening area of the first shallow groove; the depth of the first plug pre-drilled hole is smaller than the depth of the first shallow groove.
3. The method for fabricating a semiconductor integrated device according to claim 2, characterized in that, The ratio of the line width of the first plug pre-drilled hole to the line width of the first shallow groove is 0.1 to 0.
2.
4. The method for fabricating a semiconductor integrated device according to claim 1, characterized in that, The opening area of the gate trench is smaller than the opening area of the first shallow trench; the depth of the gate trench is smaller than the depth difference between the first deep trench and the first shallow trench.
5. The method for fabricating a semiconductor integrated device according to claim 4, characterized in that, The ratio of the linewidth of the gate trench to the linewidth of the first shallow trench is 0.5 to 0.
7.
6. The method for fabricating a semiconductor integrated device according to claim 1, characterized in that, The first device region is a device region used to perform SGT process; Forming a gate structure within the gate trench includes: forming a shielding gate, a control gate, a third dielectric layer that isolates the shielding gate and the control gate, and a gate dielectric layer that isolates the control gate and the semiconductor material layer within the gate trench; The first dielectric layer is used to isolate the shielding gate and the semiconductor material layer.
7. The method for fabricating a semiconductor integrated device according to claim 1, characterized in that, The second device region is the device region used to perform the BCD process; Before forming a second dielectric layer on the semiconductor material layer, the method further includes: forming an LDMOS device in the second device region; The LDMOS device includes a well region located within the semiconductor material layer, wherein the depth of the first deep trench is greater than the depth of the well region.
8. The method for fabricating a semiconductor integrated device according to claim 7, characterized in that, The second plug hole includes a plurality of holes for communicating with the source, drain and gate of the LDMOS device, and the plurality of holes included in the second plug hole are formed synchronously with the first plug hole.
9. The method for fabricating a semiconductor integrated device according to claim 1, characterized in that, The method further includes: simultaneously filling the first plug hole and the second plug hole with conductive material.
10. A semiconductor integrated device, characterized in that, It is prepared by the method of any one of claims 1 to 9 for the preparation of semiconductor integrated devices.