Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a substrate, a driving circuit layer, a planarization layer, and a first electrode layer. The planarization layer includes multiple planar sub-layers stacked along the thickness direction of the display panel. The multiple planar sub-layers share an overlapping via. The connection signal lines in the first electrode layer are electrically connected to the power signal lines in the driving circuit layer through the overlapping vias and extend from inside the overlapping vias along the sidewalls of the overlapping vias to outside the overlapping vias. By staggering the multiple planar sub-layers in the thickness direction, multiple stepped surfaces with increasing height along the first direction are formed on the sidewalls of the overlapping vias. This reduces the height abrupt changes and slope near the overlapping vias, reduces the risk of excessive etching or breakage of the connection signal lines near the overlapping vias, improves the connection reliability between the connection signal lines and the power signal lines, and thus improves the yield and product stability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of organic light-emitting display technology, inkjet printing (IJP) has been gradually introduced into the manufacturing process of large-size display panels to meet the requirements of display uniformity and process yield. Compared with the traditional fine metal mask (FMM) process, inkjet printing places higher demands on the flatness of the display area of ​​the display panel. It is usually necessary to increase the thickness of the flattening layer to improve the uniformity of the light-emitting layer and related functional layers, thereby improving the display effect and the overall process stability.

[0003] In existing display panel structures, the planarization layer is typically formed by stacking multiple layers of planarization materials to meet the flatness requirements of inkjet printing processes. Due to the relatively large overall thickness of the planarization layer, and the need for openings within it to connect overlapping traces to the underlying power lines, a significant local height variation occurs near these openings, resulting in a steep ramp structure at the opening edges. During subsequent film deposition and etching of the overlapping traces, this ramp structure makes it difficult to maintain uniform etching in this area, easily leading to uneven etching or localized over-etching. This can cause the overlapping traces to break near the openings, affecting the reliability of their connection to the underlying power lines. Summary of the Invention

[0004] This application provides a display panel and display device to improve the uniformity of film formation and etching of connection signal lines at the sidewalls of overlapping vias, reduce the risk of over-etching or breakage of connection signal lines, improve the connection reliability between connection signal lines and power signal lines, and thereby improve the connection reliability and yield of the display panel.

[0005] To achieve the above objectives, the technical solutions provided in this application are as follows:

[0006] This application provides a display panel, including: Base; A driving circuit layer is disposed on one side of the substrate and includes power signal lines; A planarization layer, disposed on the side of the driving circuit layer away from the substrate, includes multiple planar sub-layers stacked along the thickness direction of the display panel, the multiple planar sub-layers sharing an overlap via; and A first electrode layer is disposed on the side of the flat layer away from the driving circuit layer, and includes a connection signal line. The connection signal line is electrically connected to the power signal line through the overlapping via and extends from inside the overlapping via along the side wall of the overlapping via to outside the overlapping via. The plurality of flat sub-layers are staggered in the view along the thickness direction of the display panel so that the sidewall of the overlapping via has a plurality of stepped surfaces. The height of the plurality of stepped surfaces increases in a first direction, which is the direction from the center of the overlapping via to the sidewall of the overlapping via.

[0007] Optionally, in one embodiment, each of the flat sub-layers includes a flat sub-section and a stepped sub-section connected to the flat sub-section, the stepped sub-section being disposed on the side of the flat sub-section near the center of the overlapping through-hole, and there is a step difference between the stepped sub-section and the flat sub-section; In this configuration, from a perspective along the thickness direction of the display panel, the flat sub-sections of the plurality of flat sub-layers are staggered, the stepped sub-sections of the plurality of flat sub-layers are staggered, and in two adjacent flat sub-layers, the stepped sub-section of one flat sub-layer overlaps with the flat sub-section of the other flat sub-layer.

[0008] Optionally, in one embodiment, the staggered arrangement order of the flat sub-parts of the plurality of flat sub-layers in the first direction, and the staggered arrangement order of the stepped sub-parts of the plurality of flat sub-layers in the first direction, are the same as the stacking order of the plurality of flat sub-layers in the direction from the substrate to the flat layer.

[0009] Optionally, in one embodiment, the plurality of flat sublayers include: A first flat sublayer, wherein the stepped portion of the first flat sublayer has a first stepped surface; The second flat sublayer is disposed on the side of the first flat sublayer away from the driving circuit layer, and the stepped portion of the second flat sublayer is located on the stepped portion and the flat portion of the first flat sublayer, and has a second stepped surface; The third flat sublayer is disposed on the side of the second flat sublayer away from the first flat sublayer. The stepped portion of the third flat sublayer is located on the stepped portion and the flat portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the flat portion of the second flat sublayer and has a fourth stepped surface.

[0010] Optionally, in one embodiment, the staggered arrangement order of the flat sub-parts of the plurality of flat sub-layers in the first direction, and the staggered arrangement order of the stepped sub-parts of the plurality of flat sub-layers in the first direction, are different from the stacking order of the plurality of flat sub-layers in the direction from the substrate to the flat layer.

[0011] Optionally, in one embodiment, the plurality of flat sublayers includes a first flat sublayer, a second flat sublayer, and a third flat sublayer; The first flat sublayer, the second flat sublayer, and the third flat sublayer are stacked sequentially in the direction from the substrate to the flat layer, and the first flat sublayer, the third flat sublayer, and the second flat sublayer are staggered sequentially in the first direction.

[0012] Optionally, in one embodiment, the stepped portion of the first flat sublayer has a first stepped surface; The stepped portion of the second flat sublayer is located on the stepped portion and the flat portion of the first flat sublayer, and the flat portion of the second flat sublayer is located on the flat portion of the first flat sublayer; The stepped portion of the third flat sublayer includes a first portion and a second portion connected together. The first portion is located on the stepped portion of the second flat sublayer and has a second stepped surface. The second portion is located on the stepped portion and the flat portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the flat portion of the second flat sublayer and has a fourth stepped surface.

[0013] Optionally, in one embodiment, the stepped portion of the first flat sublayer has a first stepped surface; The stepped portion and the flat portion of the second flat sublayer are both located on the flat portion of the first flat sublayer; The stepped portion of the third flat sublayer includes a first portion and a second portion connected together. The first portion is located on the stepped portion and the flat portion of the first flat sublayer and has a second stepped surface. The second portion is located on the flat portion of the first flat sublayer and the stepped portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the stepped portion and the flat portion of the second flat sublayer and has a fourth stepped surface.

[0014] Optionally, in one embodiment, the heights of the first step surface, the second step surface, the third step surface, and the fourth step surface increase in the first direction.

[0015] Optionally, in one embodiment, the height of the second step surface has a first difference with the height of the first step surface, the height of the third step surface has a second difference with the height of the second step surface, and the height of the fourth step surface has a third difference with the height of the third step surface; Wherein, the third difference is greater than the second difference, and the second difference is greater than the first difference.

[0016] Optionally, in one embodiment, the stepped portion is provided with a plurality of grooves, the plurality of grooves being arranged around the center of the overlapping through hole; In this configuration, on the reference plane, the trenches of two adjacent flat sublayers are staggered, and the size of the trench of one of the flat sublayers on the side away from the substrate is smaller than the size of the trench of the other flat sublayer on the side closer to the substrate; the reference plane is parallel to the light-emitting surface of the display panel.

[0017] Optionally, in one embodiment, the plurality of flat sublayers include a first flat sublayer, a second flat sublayer, and a third flat sublayer, wherein the first flat sublayer, the second flat sublayer, and the third flat sublayer are stacked sequentially in the direction from the substrate to the flat layer; Wherein, on the reference plane, along the first direction, the second flat sublayer is recessed relative to the first flat sublayer, and the third flat sublayer is recessed relative to the second flat sublayer.

[0018] Optionally, in one embodiment, the display panel includes a display area and a non-display area located on at least one side of the display area; The flat layer includes a flat portion and a ramp portion disposed on at least one side of the flat portion. The ramp portion is located within the non-display area, and the thickness of the ramp portion is less than or equal to the thickness of the flat portion. The first electrode layer has multiple vent holes, which penetrate the first electrode layer along the thickness direction of the display panel, and the distance between the vent holes and the surface of the ramp portion away from the flat portion is greater than or equal to 50 micrometers.

[0019] Optionally, in one embodiment, at least some of the plurality of vents are arranged along a predetermined path surrounding the display area; The preset path includes an arc-shaped path, which is located at a corner of the preset path, and at least some of the exhaust holes are sequentially arranged along the arc-shaped path.

[0020] Optionally, in one embodiment, the plurality of vent holes include a first vent hole and a second vent hole arranged adjacent to each other, wherein the size of the first vent hole is greater than or equal to the size of the second vent hole.

[0021] This application also provides a display device, which includes any of the display panels described above.

[0022] The beneficial effects of the embodiments of this application are as follows: This application provides a display panel and a display device; the display panel includes a substrate, a driving circuit layer, a planarization layer, and a first electrode layer; the planarization layer includes a plurality of planar sub-layers stacked along the thickness direction of the display panel, the plurality of planar sub-layers having a common overlapping via, the connection signal line in the first electrode layer being electrically connected to the power signal line in the driving circuit layer through the overlapping via, and extending from inside the overlapping via along the sidewall of the overlapping via to outside the overlapping via; by making the plurality of planar sub-layers staggered in the thickness direction, a plurality of stepped surfaces with increasing height along the first direction are formed on the sidewall of the overlapping via, thereby reducing the height abrupt change and slope near the overlapping via, reducing the risk of excessive etching or breakage of the connection signal line near the overlapping via, improving the connection reliability between the connection signal line and the power signal line, thereby improving the yield and product stability of the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application; Figure 2 This is a partial cross-sectional schematic diagram of the display panel provided in an embodiment of this application; Figure 3 This is a schematic diagram of a first partial cross-section of a planarization layer provided in an embodiment of this application; Figure 4 This is a schematic diagram of a second partial cross-section of the planarization layer provided in an embodiment of this application; Figure 5 This is a schematic diagram of a third partial cross-section of the planarization layer provided in an embodiment of this application; Figure 6 This is a schematic diagram of a first partial top view of the flat layer provided in an embodiment of this application; Figure 7 Provided for the embodiments of this application Figure 6 Schematic diagram of the cross section at point AA'; Figure 8 This is a schematic diagram of a second partial top view of the flat layer provided in an embodiment of this application; Figure 9 This is a partial top view of the display panel provided in an embodiment of this application; Figure 10 This is a schematic diagram of a first partial top view of the first electrode layer provided in an embodiment of this application. Figure 11 Provided for the embodiments of this application Figure 10 Enlarged view of point B in the middle; Figure 12 This is a schematic diagram of a second partial top view of the first electrode layer provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiment of this application.

[0025] Explanation of reference numerals in the attached figures: 1-Display panel; 100-Display area; 200-Non-display area; 10-Substrate; 20-Driving circuit layer; 201-Thin film transistor; 21-Semiconductor layer; 22-First gate insulating layer; 23-First metal layer; 24-Second gate insulating layer; 25-Second metal layer; 26-Interlayer insulating layer; 27-First source / drain metal layer; 271-Power signal line; 28-Second source / drain metal layer; 281-Bridging electrode; 30-Planar layer; 301-Planar portion; 302-Climbing portion; 303-Overlapping via; 304-Stepped surface; 305-Rounded corner; 31-Planar sublayer; 311-Stepped sublayer; 3111-Trench; 312- Flat sub-section; 313-First flat sub-layer; 314-Second flat sub-layer; 315-Third flat sub-layer; 3151-First part; 3152-Second part; 3041-First step surface; 3042-Second step surface; 3043-Third step surface; 3044-Fourth step surface; 40-First electrode layer; 41-Connecting signal line; 42-Exhaust hole; 421-Rounded chamfer; 422-First exhaust hole; 423-Second exhaust hole; 43-Preset path; 431-Arc path; D1-First spacing; H1-First difference; H2-Second difference; H3-Third difference; 2-Display device; 210-Middle frame; X-First direction. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working mode of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections or detachable connections; mechanical connections or electrical connections or connections that allow communication; direct connections or indirect connections through an intermediate medium; and connections within two components or interactions between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] The following disclosure provides many different embodiments for implementing different structures of this application. To simplify the disclosure of this application, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0030] Please combine Figure 1 and Figure 2 This embodiment provides a display panel 1, which can be an organic light-emitting diode (OLED) display panel 1. The display panel 1 includes a substrate 10, a driving circuit layer 20, a planarization layer 30, a pixel definition layer, a light-emitting device layer, and an encapsulation layer stacked together.

[0031] The substrate 10 includes a first substrate, a buffer layer, and a second substrate stacked sequentially. Both the first substrate and the second substrate can be rigid substrates or flexible substrates. The buffer layer is disposed between the first substrate and the second substrate to alleviate the thermal stress difference between the substrates, block impurity diffusion, and improve the growth interface quality of the upper thin film, thereby improving the reliability of the substrate.

[0032] The driving circuit layer 20 is disposed on one side of the substrate 10. The driving circuit layer 20 is used to provide driving electrical signals to the light-emitting device layer to control the switching state and light emission brightness of the light-emitting device, thereby realizing the image display and color adjustment functions of the display panel 1. The driving circuit layer 20 may include multiple thin film transistors 201 for independent driving of each light-emitting unit. The thin film transistors 201 may be etch-block type, back trench etch type, or classified into bottom gate thin film transistors 201, top gate thin film transistors 201, etc. according to the position of the gate and the active layer. This embodiment does not limit this.

[0033] Specifically, the driving circuit layer 20 may include a semiconductor layer 21, a first gate insulating layer 22, a first metal layer 23, a second gate insulating layer 24, a second metal layer 25, an interlayer insulating layer 26, a first source / drain metal layer 27, and a second source / drain metal layer 28 stacked on the substrate 10.

[0034] The first metal layer 23 includes a first gate for regulating the first electric field of the semiconductor layer 21; the second metal layer 25 includes a second gate for regulating the second electric field of the semiconductor layer 21; compared with a single-gate structure, a multi-gate structure can more finely adjust the distribution state of channel carriers, thereby reducing leakage current, improving subthreshold characteristics, and enhancing the overall stability of the thin-film transistor 201; the first source-drain metal layer 27 includes a source and a drain spaced apart, which are used to realize the current input and output of the thin-film transistor 201, respectively; the second source-drain metal layer 28 includes a bridging electrode 281, which is used to realize cross-layer electrical connection between different conductive structures in the driving circuit layer 20. For example, it can be used to electrically couple the electrode structure in the first source-drain metal layer 27 to the power signal line 271, connection signal line 41, or other functional wires arranged above or to the side, thereby realizing reliable transmission of signals or power between different layers without increasing wiring complexity.

[0035] The planarization layer 30 is disposed on the side of the driving circuit layer 20 away from the substrate 10. The planarization layer 30 is used to planarize the surfaces of the driving circuit layer 20 and the substrate 10 to eliminate the surface height difference caused by the superposition of multiple metal structures, thereby providing a relatively flat film formation base for subsequent film layers.

[0036] The pixel definition layer is located on the side of the driving circuit layer 20 away from the substrate 10, and is used to define the light-emitting area of ​​each pixel. The pixel definition layer has multiple pixel openings, and by setting light-emitting functional structures with different light-emitting colors, such as red, green and blue light-emitting units, in different pixel openings, the display panel 1 can achieve the display effect of full-color images.

[0037] The light-emitting device layer includes a first electrode layer 40, a light-emitting layer, and a second electrode layer stacked together. The first electrode layer 40 is disposed between the pixel definition layer and the driving circuit layer 20. The first electrode layer 40 includes a plurality of anodes spaced apart. A pixel opening is aligned with a certain anode, and at least a portion of the anode surface is exposed in the pixel opening to facilitate subsequent deposition of the light-emitting layer and formation of electrical contacts. The light-emitting layer is disposed on the first electrode layer 40 and includes a plurality of light-emitting parts corresponding one-to-one with the plurality of anodes. Each light-emitting part is located in the corresponding pixel opening and is electrically connected to the drain of the thin-film transistor 201 through the anode, thereby realizing independent driving and brightness control of each light-emitting part. The second electrode layer can be a cathode layer, and the entire second electrode layer is laid on the side of the light-emitting layer away from the first electrode layer 40.

[0038] Specifically, the anode is electrically connected to the thin-film transistor 201. The thin-film transistor 201 controls the current flow to the anode by adjusting the gate signal. The anode provides positive charge to drive the light-emitting part. The organic material in the light-emitting part emits light by recombination under the action of the positive charge of the anode and the negative charge of the cathode layer.

[0039] The encapsulation layer is located on the side of the light-emitting device layer away from the pixel definition layer. The encapsulation layer is used to encapsulate the light-emitting device layer to prevent the first electrode layer 40, the light-emitting layer and the cathode layer in the light-emitting device layer from coming into contact with water and oxygen in the air, thereby shortening the service life of the display panel 1. The encapsulation layer may include a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer stacked on the pixel definition layer. The materials of the first inorganic encapsulation layer and the second inorganic encapsulation layer include, but are not limited to, silicon nitride, silicon oxide or silicon oxynitride. The material of the first organic encapsulation layer includes, but is not limited to, polyacrylate.

[0040] In one embodiment, the first source / drain electrode layer further includes a power signal line 271 for transmitting a low-potential power signal. To enable potential access to the cathode of the light-emitting device, the first electrode layer 40 also includes a connection signal line 41 that is insulated from the anode. One end of the connection signal line 41 is electrically connected to the power signal line 271, and the other end of the connection signal line 41 is electrically connected to the second electrode layer. Thus, the low-potential power signal can be transmitted to the cathode layer via the conductive path formed by the power signal line 271 and the connection signal line 41, thereby ensuring a reliable supply of cathode potential.

[0041] Specifically, the planarization layer 30 includes multiple planar sub-layers 31 stacked along the thickness direction of the display panel 1, and the multiple planar sub-layers 31 are provided with overlapping vias 303. The connection signal line 41 is electrically connected to the power signal line 271 through the overlapping via 303, and extends outward from inside the overlapping via 303 along the sidewall of the overlapping via 303 to outside the overlapping via 303. The outside of the overlapping via 303 is the surface of the planarization layer 30 away from the substrate 10. In the view along the thickness direction of the display panel 1, the multiple planar sub-layers 31 are staggered at the sidewall of the overlapping via 303, so that the sidewall of the overlapping via 303 forms multiple stepped surfaces 304. The height of the multiple stepped surfaces 304 increases gradually in the first direction X, where the first direction X is the direction from the center of the overlapping via 303 to the sidewall of the overlapping via 303.

[0042] Furthermore, the plurality of flat sublayers 31 include a first flat sublayer 313, a second flat sublayer 314, and a third flat sublayer 315 stacked together. The first flat sublayer 313 covers the first source / drain metal layer 27. The second source / drain metal layer 28 is disposed on the side of the first flat sublayer 313 away from the first source / drain metal layer 27. The second flat sublayer 314 is disposed on the side of the second source / drain metal layer 28 away from the first flat sublayer 313. The third flat sublayer 315 is disposed on the side of the second flat sublayer 314 away from the second source / drain metal layer 28. The connection signal line 41 is electrically connected to the power signal line 271 through the bridging electrode 281.

[0043] Understandably, by staggering multiple flat sub-layers 31 stacked along the thickness direction of the display panel 1 at the sidewall of the overlapping via 303, the local height abrupt change caused by the overall thickness of the flat layer 30 at the overlapping via 303 is decomposed into a gradual height transition structure composed of multiple stepped surfaces 304. This makes the film thickness change of the first electrode layer 40 more gradual during the film formation process at the overlapping via 303, which is beneficial to improving the coverage continuity of the metal film at the edge of the overlapping via 303. At the same time, during the etching process of the first electrode layer 40, due to the reduction of local film thickness differences, the etching rate tends to be uniform, thereby effectively reducing the risk of metal fracture caused by uneven etching or local over-etching.

[0044] Furthermore, the stepped sidewall structure formed by the staggered arrangement of multiple flat sublayers 31 can improve the structural integrity of the connection signal line 41 near the overlapping via 303, ensuring the stability and reliability of the electrical connection between the connection signal line 41 and the power signal line 271, thereby improving the consistency of the cathode potential supply. This helps to reduce problems such as uneven brightness, flickering or local failure that occur in the display panel 1 during long-term use, thereby improving the process yield and product stability of the display panel 1.

[0045] In one embodiment, each flat sublayer 31 includes a flat sub-part 312 and a stepped sub-part 311 connected to the flat sub-part 312. The stepped sub-part 311 is disposed on the side of the flat sub-part 312 near the center of the overlapping via 303, and there is a step difference between the stepped sub-part 311 and the flat sub-part 312. In the view along the thickness direction of the display panel 1, the flat sub-parts 312 of the multiple flat sublayers 31 are staggered, the stepped sub-parts 311 of the multiple flat sublayers 31 are staggered, and in two adjacent flat sublayers 31, the stepped sub-part 311 of one flat sublayer 31 overlaps with the flat sub-part 312 of the other flat sublayer 31. This makes the sidewall of the overlapping via 303 present a stepped structure composed of multiple staggered stepped surfaces 304, reducing the height change amplitude of the sidewall of the overlapping via 303 and improving the slope angle of the sidewall of the overlapping via 303.

[0046] Furthermore, in the first direction X, on the side near the center of the overlapping through-hole 303, the stepped portion 311 of the flat sub-layer 31 extends downward relative to its corresponding flat portion 312, so that the termination positions of different flat sub-layers 31 at the sidewall of the overlapping through-hole 303 are staggered; thus, adjacent flat sub-layers 31 are sequentially connected through the overlapping relationship of "stepped portion 311 - flat portion 312", so that the height change of the sidewall of the overlapping through-hole 303 is no longer concentrated at a single position, but is distributed along the first direction X to multiple steps with small height differences.

[0047] Specifically, the slope angle of each step sub-layer 311 is greater than or equal to 35 degrees and less than or equal to 55 degrees, thereby ensuring a smooth and stable step transition between multiple flat sub-layers 31, which is beneficial to the uniform coverage and stress release of subsequent membrane layers.

[0048] It is understandable that by introducing a combination structure of flat sub-section 312 and step sub-section 311 in each flat sub-layer 31, and by making the step sub-section 311 and flat sub-section 312 of adjacent flat sub-layers 31 overlap, a gentle slope structure composed of multiple steps with small height differences can be formed at the side wall of the overlapping through-hole 303.

[0049] Compared to the steep ramp structure formed by a single planar layer 30 or multiple planar layers 30 in the prior art, the stepped sidewall structure significantly reduces the equivalent slope at the edge of the overlapping via 303. This allows the first electrode layer 40 to gradually cover each stepped portion 311 and the planar portion 312 as it extends outward from the inside of the overlapping via 303, thereby improving the continuity and stability of the film layer 40 at the overlapping via 303. During the etching process of the first electrode layer 40, because the film thickness variation of the first electrode layer 40 at each stepped portion 311 is more uniform, it is less likely to form etching concentration points in local areas during the etching process. This reduces the risk of over-etching or breakage of the connection signal line 41 at the edge of the overlapping via 303, further improving the reliability of the electrical connection between the connection signal line 41 and the power signal line 271.

[0050] In one embodiment, the staggered arrangement order of the flat sub-parts 312 of the plurality of flat sub-layers 31 in the first direction X, and the staggered arrangement order of the stepped sub-parts 311 of the plurality of flat sub-layers 31 in the first direction X, are the same as the stacking order of the plurality of flat sub-layers 31 in the direction from the substrate 10 to the flat layer 30. This results in the flat sub-layers 31 located on the side closer to the substrate 10 forming a stepped structure relatively close to the center of the overlapping via 303 at the sidewall of the overlapping via 303, while the flat sub-layers 31 located on the side away from the substrate 10 forming a stepped structure relatively away from the center of the overlapping via 303 at the sidewall of the overlapping via 303.

[0051] Specifically, in the first direction X, the flat sublayer 31 disposed near the substrate 10 has its stepped portion 311 extending first toward the center of the overlapping via 303; as the flat sublayers 31 are stacked layer by layer along the thickness direction of the display panel 1, the stepped portions 311 of the subsequently disposed flat sublayers 31 are staggered outward in the first direction X, so that multiple flat sublayers 31 form a stepped structure that rises step by step from the inside to the outside at the sidewall of the overlapping via 303.

[0052] It is understandable that by ensuring that the staggered order of the flat sub-section 312 and the stepped sub-section 311 in the first direction X is consistent with the stacking order of the flat sub-layer 31 in the thickness direction, it is possible to ensure that the stepped structure at the sidewall of the overlapping through-hole 303 presents a regular and continuous height increase relationship in space, thus avoiding the situation of stepped height disorder or local reverse abrupt change.

[0053] Please combine Figure 1 and Figure 3In one embodiment, a first flat sublayer 313, a second flat sublayer 314, and a third flat sublayer 315 are stacked sequentially in the direction from the base 10 to the flat layer 30. The first flat sublayer 313 has a step portion 311 with a first step surface 3041. The second flat sublayer 314 has a step portion 311 located on the step portions 311 and flat portions 312 of the first flat sublayer 313 and has a second step surface 3042. The third flat sublayer 315 has a step portion 311 located on the step portions 311 and flat portions 312 of the second flat sublayer 314 and has a third step surface 3043. The third flat sublayer 315 has a flat portion 312 located on the flat portion 312 of the second flat sublayer 314 and has a fourth step surface 3044, thereby forming a multi-level stepped structure with progressively increasing height along the first direction X at the sidewall of the overlapping through-hole 303.

[0054] Specifically, the first step surface 3041 is formed by the top surface of the step portion 311 of the first flat sublayer 313; the second step surface 3042 is formed by superimposing the step portion 311 of the second flat sublayer 314 with the step portion 311 and the flat portion 312 of the first flat sublayer 313; the third step surface 3043 is formed by superimposing the step portion 311 of the third flat sublayer 315 with the step portion 311 and the flat portion 312 of the second flat sublayer 314, and the flat portion 312 of the first flat sublayer 313; the fourth step surface 3044 is formed by superimposing the flat portion 312 of the third flat sublayer 315 with the flat portion 312 of the second flat sublayer 314, and the flat portion 312 of the first flat sublayer 313; it should be noted that the top surface of the step portion 311 refers to the surface of the step portion 311 away from the substrate 10.

[0055] Furthermore, in the first direction X, the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 are distributed sequentially, so that the sidewall of the overlapping through hole 303 no longer presents a single steep height change, but achieves a gradual rise in transitional morphology through multiple step surfaces 304 of different heights; wherein, the height of the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 increases in the first direction X, so that the sidewall of the overlapping through hole 303 forms a gradually rising step structure in the first direction X.

[0056] Understandably, by staggering the step portions 311 and flat portions 312 of the first flat sublayer 313, the second flat sublayer 314, and the third flat sublayer 315, and forming a multi-level stepped surface 304 at the sidewall of the overlapping via 303, the height difference originally concentrated at the edge of the overlapping via 303 can be dispersed to multiple stepped surfaces 304, thereby reducing the slope variation at a single location. At the same time, under the multi-level stepped structure, when the first electrode layer 40 extends outward from the inside of the overlapping via 303 and covers the stepped surface 304, its film layer can be laid up step by step along each stepped surface 304, thereby avoiding the problem of film thinning or discontinuity at the edge of the overlapping via 303 due to excessively steep slope, and improving the film formation continuity and thickness uniformity of the first electrode layer 40.

[0057] It should be noted that, in this embodiment, the stepped transition structure can be fabricated using halftone masking technology. Specifically, when forming each flat sublayer 31, a corresponding halftone mask can be used for single exposure and etching. Halftone masking technology can directly form a preset stepped thickness distribution within a single layer of material.

[0058] Please combine Figure 1 and Figure 4 In one embodiment, the staggered arrangement order of the flat sub-parts 312 of the plurality of flat sub-layers 31 in the first direction X, and the staggered arrangement order of the stepped sub-parts 311 of the plurality of flat sub-layers 31 in the first direction X, are different from the stacking order of the plurality of flat sub-layers 31 in the direction from the substrate 10 to the flat layer 30, thereby causing the stepped structure at the sidewall of the overlapping via 303 to be staggered and superimposed in the thickness direction of the display panel 1, further forming a gentler stepped gradient.

[0059] Furthermore, the stepped portion 311 of the later-stacked flat sublayer 31 may be located closer to the center of the overlapping through hole 303 than the flat portion 312 of the previous flat sublayer 31, or closer to the outer side of the overlapping through hole 303 than the stepped portion 311 of the previous flat sublayer 31. This results in multiple stepped portions 311 forming an interlaced superposition relationship at the sidewall of the overlapping through hole 303, so that the height change of the sidewall of the overlapping through hole 303 no longer simply presents a stepped structure of "expanding outward layer by layer".

[0060] Specifically, the first flattening sublayer 313, the second flattening sublayer 314, and the third flattening sublayer 315 are stacked sequentially in the direction from the substrate 10 to the flattening layer 30, and the first flattening sublayer 313, the third flattening sublayer 315, and the second flattening sublayer 314 are staggered sequentially in the first direction X.

[0061] In the first direction X, the stepped portion 311 of the first flat sublayer 313 is located near the center of the overlapping through hole 303, while the stepped portion 311 of the third flat sublayer 315 is offset outward relative to the stepped portion 311 of the first flat sublayer 313, and the stepped portion 311 of the second flat sublayer 314 is further offset outward relative to the stepped portion 311 of the third flat sublayer 315, forming an alternating layout of "first flat sublayer 313, third flat sublayer 315 and second flat sublayer 314". This makes the height change of the sidewall of the overlapping through hole 303 no longer present a unidirectional progressive step, but is alternately distributed between different flat sublayers 31, thereby forming a smoother and more continuous transition morphology.

[0062] Understandably, because the staggered order of multiple flat sub-layers 31 is different from the stacking order, the height variation at the sidewall of the overlapping via 303 can be alternately distributed among the multiple flat sub-layers 31, thereby effectively dispersing the height abrupt change in a single direction. When the first electrode layer 40 is formed at the overlapping via 303, it can gradually extend along the staggered step morphology, avoiding the formation of an excessively steep local slope at a certain position, thereby reducing the risk of film thinning or breakage.

[0063] Meanwhile, during the etching process of the first electrode layer 40, the local difference in etching rate is alleviated because the sidewall morphology of the overlapping via 303 is more gentle and the step distribution is more uniform. This further reduces the probability of over-etching or breakage of the first electrode layer 40 near the overlapping via 303, thereby improving the process yield and electrical connection reliability of the display panel 1.

[0064] In one embodiment, the stepped portion 311 of the first flat sublayer 313 has a first stepped surface 3041; the stepped portion 311 of the second flat sublayer 314 is located on the stepped portion 311 and the flat portion 312 of the first flat sublayer 313, and the flat portion 312 of the second flat sublayer 314 is located on the flat portion 312 of the first flat sublayer 313; the stepped portion 311 of the third flat sublayer 315 includes a first portion 3151 and a second portion 3152 connected to each other, the first portion 3151 being located on... The second flat sublayer 314 has a step portion 311 on the step portion 311 and a flat portion 312 on the second flat sublayer 314, and has a third step surface 3043; the third flat sublayer 315 has a flat portion 312 on the flat portion 312 of the second flat sublayer 314, and has a fourth step surface 3044, thereby forming a multi-level step structure with progressively increasing height along the first direction X at the sidewall of the overlapping through hole 303.

[0065] Specifically, the first step surface 3041 is formed by the top surface of the step portion 311 of the first flat sublayer 313; the second step surface 3042 is formed by superimposing the first portion 3151 of the step portion 311 of the third flat sublayer 315 with the step portion 311 of the second flat sublayer 314, the step portion 311 of the first flat sublayer 313 and the flat portion 312; the third step surface 3043 is formed by superimposing the second portion 3152 of the step portion 311 of the third flat sublayer 315 with the step portion 311 and the flat portion 312 of the second flat sublayer 314, and the flat portion 312 of the first flat sublayer 313; the fourth step surface 3044 is formed by superimposing the flat portion 312 of the third flat sublayer 315 with the flat portion 312 of the second flat sublayer 314 and the flat portion 312 of the first flat sublayer 313.

[0066] In the first direction X, the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 are distributed sequentially, so that the sidewall of the overlapping through hole 303 no longer presents a single steep height change, but achieves a gradual rise in transitional morphology through multiple step surfaces 304 of different heights; wherein, the height of the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 increases in the first direction X, so that the sidewall of the overlapping through hole 303 forms a gradually rising step structure in the first direction X.

[0067] Understandably, the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 are all formed by the stacking relationship between the step sub-parts 311 and the adjacent flat sub-parts 312 of different flat sub-layers 31, thereby forming a multi-level step structure at the sidewall of the overlapping via 303. This makes the height of the sidewall of the overlapping via 303 gradually increase in the first direction X, thereby providing a smoother height transition for the subsequent film formation of the first electrode layer 40, reducing the risk of breakage or thinning of the first electrode layer 40 at the overlapping via 303, and improving connection reliability and process yield.

[0068] Please combine Figure 1 and Figure 5In one embodiment, the stepped portion 311 of the first flat sublayer 313 has a first stepped surface 3041; the stepped portion 311 and the flat portion 312 of the second flat sublayer 314 are both located on the flat portion 312 of the first flat sublayer 313; the stepped portion 311 of the third flat sublayer 315 includes a first portion 3151 and a second portion 3152 connected to each other, the first portion 3151 is located on the stepped portion 311 and the flat portion 312 of the first flat sublayer 313, and has The second step surface 3042; the second part 3152 is located on the flat sub-part 312 of the first flat sub-layer 313 and the step sub-part 311 of the second flat sub-layer 314, and has a third step surface 3043; the flat sub-part 312 of the third flat sub-layer 315 is located on the step sub-part 311 and the flat sub-part 312 of the second flat sub-layer 314, and has a fourth step surface 3044, thereby forming a multi-level step structure with progressively increasing height along the first direction X at the sidewall of the overlapping through hole 303.

[0069] Specifically, the first step surface 3041 is formed by the top surface of the step portion 311 of the first flat sublayer 313; the second step surface 3042 is formed by superimposing the first portion 3151 of the step portion 311 of the third flat sublayer 315 with the step portion 311 and the flat portion 312 of the first flat sublayer 313; the third step surface 3043 is formed by superimposing the second portion 3152 of the step portion 311 of the third flat sublayer 315 with the step portion 311 of the second flat sublayer 314 and the flat portion 312 of the first flat sublayer 313; and the fourth step surface 3044 is formed by superimposing the flat portion 312 of the third flat sublayer 315 with the step portion 311 and the flat portion 312 of the second flat sublayer 314 and the flat portion 312 of the first flat sublayer 313.

[0070] In the first direction X, the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 are distributed sequentially, so that the sidewall of the overlapping through hole 303 no longer presents a single steep height change, but achieves a gradual rise in transitional morphology through multiple step surfaces 304 of different heights; wherein, the height of the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 increases in the first direction X, so that the sidewall of the overlapping through hole 303 forms a gradually rising step structure in the first direction X.

[0071] Understandably, the first step surface 3041, the second step surface 3042, the third step surface 3043, and the fourth step surface 3044 are all formed by the stacking relationship between the step sub-parts 311 and the adjacent flat sub-parts 312 of different flat sub-layers 31, thereby forming a multi-level step structure at the sidewall of the overlapping via 303. This makes the height of the sidewall of the overlapping via 303 gradually increase in the first direction X, thereby providing a smoother height transition for the subsequent film formation of the first electrode layer 40, reducing the risk of breakage or thinning of the first electrode layer 40 at the overlapping via 303, and improving connection reliability and process yield.

[0072] In one embodiment, there is a first difference H1 between the height of the second step surface 3042 and the height of the first step surface 3041, a second difference H2 between the height of the third step surface 3043 and the height of the second step surface 3042, and a third difference H3 between the height of the fourth step surface 3044 and the height of the third step surface 3043; wherein the first difference H1 is greater than the second difference H2, the second difference H2 is greater than the third difference H3, thereby causing the height difference between adjacent step surfaces 304 to decrease along the first direction X.

[0073] Specifically, on the path of the connecting signal line 41 extending from inside the overlapping via 303 along the side wall of the overlapping via 303 to outside the overlapping via 303, the height difference between adjacent step surfaces 304 gradually decreases along the first direction X, making the height transition of the flat layer 30 smoother. This results in a gradient change in the stress distribution of the connecting signal line 41 on the extension path, reducing stress concentration at the highest step surface 304 of the connecting signal line 41, thereby reducing its breakage risk and further improving connection reliability and process yield.

[0074] Please combine Figure 1 , Figure 6 and Figure 7 In one embodiment, the stepped sub-section 311 has a plurality of grooves 3111, which are arranged around the center of the overlapping via 303. On the reference plane, the grooves 3111 of two adjacent flat sub-layers 31 are staggered, and the size of the groove 3111 of one flat sub-layer 31 on the side away from the substrate 10 is smaller than the size of the groove 3111 of the other flat sub-layer 31 on the side closer to the substrate 10. The reference plane is parallel to the light-emitting surface of the display panel 1, so that the plurality of flat sub-layers 31 form a gradient structure with spatial misalignment near the overlapping via 303, so as to decompose the originally abrupt height difference into a plurality of local height transitions that change step by step along the first direction X, thereby reducing the slope angle of the flat layer 30 at the edge of the overlapping via 303.

[0075] Furthermore, the first flat sublayer 313 is disposed on the drive circuit layer 20; the stepped portion 311 of the second flat sublayer 314 is located on the stepped portion 311 and the flat portion 312 of the first flat sublayer 313; the stepped portion 311 of the third flat sublayer 315 is located on the stepped portion 311 and the flat portion 312 of the second flat sublayer 314; wherein, on the reference plane, along the first direction X, the second flat sublayer 314 is recessed relative to the first flat sublayer 313, and the third flat sublayer 315 is recessed relative to the second flat sublayer 314, thereby forming a stepped contraction arrangement of the grooves 3111 of the multiple flat sublayers 31 on the reference plane.

[0076] It should be noted that, in this embodiment, the stepped transition structure can be achieved using grayscale masking technology. Specifically, by exposing and etching each flat sublayer 31 using masks with corresponding grayscale patterns, a stepped structure with continuously varying thickness can be directly formed in each sublayer. Since grayscale masking technology does not require halftone masks, it simplifies the complexity of mask design, fabrication, and process control, which helps reduce manufacturing costs and improve process compatibility.

[0077] Specifically, each flat sub-layer 31 has a stepped portion 311 with a groove 3111, and the orthographic projections of the grooves 3111 of different flat sub-layers 31 on the reference plane are staggered. Along the direction away from the base 10, the dimensions (such as depth and width) of the grooves 3111 decrease layer by layer. Thus, in two adjacent flat sub-layers 31, the groove 3111 of one flat sub-layer 31 located closer to the base 10 can partially accommodate the material of the other flat sub-layer 31 located away from the base 10. This effectively disperses and transforms the originally abrupt height change of the flat layer 30 at the edge of the overlapping via 303 into a gentle, gradual transition across multiple grooves 3111, thereby reducing the sidewall slope angle of the overlapping via 303. The orthographic projection shape of the groove 3111 on the reference plane may include, but is not limited to, a rectangle, a trapezoid, a rounded rectangle, a wave shape, or a combination thereof. The cross-sectional shape of the groove 3111 may be "V", "U", or stepped.

[0078] Understandably, the first flat sublayer 313 has the largest and most densely distributed trenches 3111, the second flat sublayer 314 has relatively smaller trenches 3111, and the third flat sublayer 315 has even smaller trenches 3111. This results in a trench 3111 structure that is coarse to fine and large to small at the sidewall of the overlapping via 303, thereby enabling fine control of the slope of the sidewall of the flat layer 30. This allows the connecting signal line 41 to obtain a gentler slope transition at the beginning of the slope, reducing the uneven film thickness and stress concentration of the connecting signal line 41 caused by the abrupt change in the slope of the sidewall of the overlapping via 303. This reduces the probability of the connecting signal line 41 breaking in the slope area and improves the connection reliability between the connecting signal line 41 and the power signal line 271.

[0079] It should be noted that the step portion 311 of the second flat sublayer 314 is located on the step portion 311 and the flat portion 312 of the first flat sublayer 313; the step portion 311 of the third flat sublayer 315 is located on the step portion 311 and the flat portion 312 of the second flat sublayer 314 for illustrative purposes only, and multiple flat sublayers 31 may also adopt different stacking configurations.

[0080] For example: Please refer to Figure 8 In another embodiment, the stepped portion 311 of the second flat sublayer 314 may be disposed above the flat portion 312 of the first flat sublayer 313, while the stepped portion 311 of the third flat sublayer 315 is disposed above the flat portion 312 of the second flat sublayer 314. By controlling the inward shrinkage of each flat sublayer 31 in the reference plane, a stepped structure with stepped transition characteristics can be formed, thereby achieving similar technical effects.

[0081] It should also be emphasized that the key dimensional parameters (such as depth, width and distribution spacing) of the trenches 3111 formed by grayscale masking technology can be independently designed and precisely controlled. By controlling the size and arrangement of the trenches 3111, the equivalent thickness and surface morphology gradient of the corresponding flat sub-layer 31 step sub-section 31 can be flexibly adjusted, thereby realizing the active design of the sidewall slope angle of the overlapping via 303 to adapt to the different requirements of different products for step difference and reliability.

[0082] Please combine Figure 1 , Figure 2 , Figure 9 and Figure 10In one embodiment, the display panel 1 includes a display area 100 and a non-display area 200 located on at least one side of the display area 100; the planarization layer 30 includes a planar portion 301 and a ramp portion 302 disposed on at least one side of the planar portion 301, the ramp portion 302 being located within the non-display area 200, and the thickness of the ramp portion 302 being less than or equal to the thickness of the planar portion 301; wherein, a plurality of vent holes 42 are provided on the first electrode layer 40, the vent holes 42 penetrating the first electrode layer 40 along the thickness direction of the display panel 1, and there is a first distance D1 between the vent holes 42 and the surface of the ramp portion 302 away from the planar portion 301, the first distance D1 being greater than or equal to 50 micrometers, thereby ensuring that there is sufficient distance between the vent holes 42 of the first electrode layer 40 and the ramp portion 302 of the planarization layer 30, reducing the interference of the ramp portion 302 on the film formation and etching process of the first electrode layer 40, and improving the structural integrity and connection reliability of the first electrode layer 40 near the vent holes 42.

[0083] It should be noted that the planarization layer 30 can be formed of optical acrylic, polyimide, and / or similar resin materials. Therefore, it easily absorbs moisture or residual solvents from the environment during the manufacturing process and use. If these cannot be discharged in time, they can easily accumulate near the light-emitting device layer or the cathode layer, thereby damaging the light-emitting layer or the cathode layer and affecting the electrical performance and lifespan of the device. By providing vent holes 42 on the first electrode layer 40, an effective release channel can be provided for the gas in the planarization layer 30, allowing moisture or volatile gases to be discharged in time before entering the light-emitting device layer, thereby reducing the potential risk of damage to the light-emitting layer or the cathode layer.

[0084] It is understandable that by setting the vent hole 42 at a position at least 50 micrometers away from the side surface of the ramp portion 302 away from the flat portion 301, the first electrode layer 40 corresponding to the area where the vent hole 42 is located is formed on the relatively gentle flat portion 301 with a small thickness variation. This avoids the vent hole 42 directly crossing or covering the height abrupt structure formed by the ramp portion 302, reducing the problem of uneven film thickness or over-etching caused by excessive local slope during film formation and etching around the vent hole 42. At the same time, while ensuring the effective realization of the venting function, it also provides sufficient process buffer space for the first electrode layer 40 around the vent hole 42, reducing stress concentration and the generation of structural weak points, thereby improving the stability of the first electrode layer 40 structure, as well as the reliability and process yield of the display panel 1.

[0085] Please combine Figure 1 , Figure 2 , Figure 9 , Figure 10 and Figure 11In one embodiment, the opening of the vent hole 42 includes at least one rounded chamfer 421, thereby giving the edge of the vent hole 42 opening a smooth transition shape, reducing the presence of sharp corners or acute angles, and reducing the degree of geometric abrupt change at the edge of the vent hole 42.

[0086] Specifically, the radius of the chamfer 421 is greater than 5 micrometers, so that the first electrode layer 40 forms a continuously changing edge profile at the edge of the vent hole 42, avoiding abrupt corner structures at the vent hole position, which helps to improve the structural stability of the first electrode layer 40 around the vent hole 42.

[0087] It is understandable that the vent hole 42 is formed on the first electrode layer 40, and the edge of the vent hole 42 forms the termination boundary of the first electrode layer 40. If the termination boundary is sharp or acute, problems such as local uneven film thickness, over-etching, and stress concentration are easily introduced at the edge of the vent hole during the film formation and etching process of the first electrode layer 40, which can then become the starting point of cracks or defects. By setting a rounded chamfer 421 at the opening of the vent hole 42 and limiting the chamfer radius to greater than 5 micrometers, the transition of the first electrode layer 40 at the edge of the vent hole 42 is made smoother, thereby effectively dispersing the mechanical stress at the edge of the vent hole, reducing the risk of the first electrode layer 40 breaking, peeling, or developing microcracks at the location of the vent hole 42, and further improving the structural integrity of the first electrode layer 40 and the process yield and reliability of the display panel 1.

[0088] Furthermore, the edge of the ramp portion 302 near the first electrode layer 40 is configured to have a rounded chamfer 421, so that the ramp portion 302 presents a continuous and smooth curve transition in the planar profile, thereby avoiding the formation of right angle or sharp corner structure and reducing the degree of geometric abrupt change at the edge of the ramp portion 302.

[0089] It should be noted that during the etching process of the first electrode layer 40, the flow, retention, and renewal state of the etching solution on the film surface are closely related to the geometry of the ramp portion 302. When the edge of the ramp portion 302 near the first electrode layer 40 is right-angled or sharp-angled, the etching solution is prone to local accumulation and retention at the sharp-angle location, which relatively increases the actual action time and intensity of the etching solution in that area. This makes the first electrode layer 40 at the sharp-angle location more prone to over-etching compared to other areas. Understandably, due to the smaller radius of curvature at the sharp-angle location, the etching solution is not easily drained quickly, easily forming a local etching solution enrichment area. This leads to a non-uniform etching rate during the etching process, increasing the film thickness reduction of the first electrode layer 40 at the sharp-angle location, and even causing local fractures or uncontrolled morphology.

[0090] Specifically, the radius of the arc corner 305 is greater than 200 micrometers, thereby creating a continuous and gentle curvature transition at the edge of the ramp portion 302 on a larger scale. This reduces stress concentration at the edge of the ramp portion 302 and minimizes defects such as local over-etching, film cracks, or fractures that may occur during film formation and etching. Simultaneously, the arc corner 305 improves the spread of photoresist and the flow of etching solution at the edge of the ramp portion 302, resulting in more uniform film formation and more stable etching of the first electrode layer 40 at the edge of the ramp portion 302. This enhances the integrity and reliability of the first electrode layer 40 structure, reduces the probability of fracture defects, and ultimately improves the process yield and product reliability of the display panel 1.

[0091] In one embodiment, among the plurality of vent holes 42, at least some of the vent holes 42 are arranged along a preset path 43 surrounding the display area 100; wherein, the preset path 43 includes an arc path 431, the arc path 431 is located at the corner of the preset path 43, and at least some of the vent holes 42 are arranged sequentially along the arc path 431.

[0092] It should be noted that, since the first electrode layer 40 usually presents a continuous thin film structure spanning the edge of the vent hole 42, it is extremely sensitive to geometric continuity and curvature changes during film formation, annealing and subsequent etching. If the vent hole 42 is arranged along a straight or sharp-angled path, the edge of the vent hole 42 will form an abrupt broken line profile or sharp-angle profile at the corner of the preset path 43, which will cause the radius of curvature of the first electrode layer 40 at the corresponding position to decrease sharply, thereby generating an obvious stress concentration effect in the film layer.

[0093] Furthermore, in stress concentration areas, the first electrode layer 40 is more prone to local film thickness unevenness or decreased adhesion during film formation. During etching, because the etching rate is sensitive to local morphology and stress state, it is easy to cause defects such as over-etching, etching residue or edge burrs, thereby increasing the risk of the first electrode layer 40 breaking, microcracks or abnormal electrical performance.

[0094] It is understood that this embodiment introduces an arc-shaped path 431 at the corner of the preset path 43, and arranges at least some of the exhaust holes 42 continuously along the preset path 43, so that the overall outline of the exhaust holes 42 presents a smooth transition curve in the corner area, thereby effectively increasing the equivalent radius of curvature of the first electrode layer 40 at the corner and reducing the degree of geometric abrupt change. As a result, the stress distribution of the first electrode layer 40 at the location of the exhaust holes 42 is more uniform, the film formation stability and etching consistency are improved, and the process yield and long-term reliability of the display panel 1 are further improved.

[0095] Please combine Figure 1 , Figure 2 , Figure 9 , Figure 10 and Figure 12 In one embodiment, the plurality of vent holes 42 include a first vent hole 422 and a second vent hole 423 arranged adjacent to each other. The size of the first vent hole 422 is greater than or equal to the size of the second vent hole 423, so that the vent holes 42 arranged along the preset path 43 form a size gradient from large to small at the corner.

[0096] Specifically, a first vent 422 is provided on the arc path 431 near the long side of the planarization layer 30, and a second vent 423 is provided at the arc corner 305 of the arc path 431 in the direction pointing towards the short side of the planarization layer 30, so that the size of the vent 42 gradually decreases along the arc path 431 from the long side of the planarization layer 30 to the short side of the planarization layer 30.

[0097] It should be noted that in the display panel 1, the long side of the planarization layer 30 is relatively long compared to the straight section, and the extension direction of the first electrode layer 40 corresponding to the long side of the planarization layer 30 is relatively uniform, resulting in a relatively uniform stress distribution. However, at the arc corner 305 where the long side of the planarization layer 30 transitions to the short side, the extension direction of the first electrode layer 40 changes continuously, the local curvature increases, and the stress is more likely to concentrate at the edge of the exhaust hole 42.

[0098] Understandably, by setting a larger first vent hole 422 near the long side of the planarization layer 30, and a smaller second vent hole 423 at the arc corner 305 in the direction pointing towards the short side of the planarization layer 30, the trans-hole size and geometric change of the first electrode layer 40 gradually adjust as it transitions from the long side to the corner. This achieves gradual stress release and avoids the formation of a new stress concentration point at the arc corner 305. Consequently, the stress distribution of the first electrode layer 40 at the location of the vent hole 42 is smoother, improving the film thickness consistency and structural stability during the film formation process. Furthermore, the probability of defects occurring at the edge of the vent hole 42 is significantly reduced during etching and encapsulation processes.

[0099] Please combine Figures 1 to 13 This embodiment also provides a display device 2, which includes the display panel 1 in any of the above embodiments; wherein, the display device 2 may further include a middle frame 210, which is integrated with the display panel 1 to provide support, fixation and protection for the display panel 1.

[0100] It is understood that the display panel 1 has been described in detail in the above embodiments and will not be described again here; in particular, since the display device 2 adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated here.

[0101] In specific applications, the display device 2 can be at least one of the following devices with display functions: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, mobile medical device, camera, game console, digital camera, car navigation system, electronic billboard, ATM or wearable device.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0103] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: Base; A driving circuit layer is disposed on one side of the substrate and includes power signal lines; A planarization layer is disposed on the side of the driving circuit layer away from the substrate, and includes a plurality of planar sub-layers stacked along the thickness direction of the display panel, wherein the plurality of planar sub-layers are provided with an overlap via. as well as A first electrode layer is disposed on the side of the flat layer away from the driving circuit layer, and includes a connection signal line. The connection signal line is electrically connected to the power signal line through the overlapping via and extends from inside the overlapping via along the side wall of the overlapping via to outside the overlapping via. The plurality of flat sub-layers are staggered in the view along the thickness direction of the display panel so that the sidewall of the overlapping via has a plurality of stepped surfaces. The height of the plurality of stepped surfaces increases in a first direction, which is the direction from the center of the overlapping via to the sidewall of the overlapping via.

2. The display panel according to claim 1, characterized in that, Each of the flat sub-layers includes a flat sub-section and a stepped sub-section connected to the flat sub-section, the stepped sub-section being disposed on the side of the flat sub-section near the center of the overlapping through-hole, and there is a step difference between the stepped sub-section and the flat sub-section; In this configuration, from a perspective along the thickness direction of the display panel, the flat sub-sections of the plurality of flat sub-layers are staggered, the stepped sub-sections of the plurality of flat sub-layers are staggered, and in two adjacent flat sub-layers, the stepped sub-section of one flat sub-layer overlaps with the flat sub-section of the other flat sub-layer.

3. The display panel according to claim 2, characterized in that, The staggered arrangement order of the flat sub-parts of the plurality of flat sub-layers in the first direction, and the staggered arrangement order of the stepped sub-parts of the plurality of flat sub-layers in the first direction, are the same as the stacking order of the plurality of flat sub-layers in the direction from the substrate to the flat layer.

4. The display panel according to claim 3, characterized in that, The plurality of flat sublayers include: A first flat sublayer, wherein the stepped portion of the first flat sublayer has a first stepped surface; The second flat sublayer is disposed on the side of the first flat sublayer away from the driving circuit layer, and the stepped portion of the second flat sublayer is located on the stepped portion and the flat portion of the first flat sublayer, and has a second stepped surface; A third flat sublayer is disposed on the side of the second flat sublayer away from the first flat sublayer. The stepped portion of the third flat sublayer is located on the stepped portion and the flat portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the flat portion of the second flat sublayer and has a fourth stepped surface. The heights of the first step surface, the second step surface, the third step surface, and the fourth step surface increase in the first direction.

5. The display panel according to claim 2, characterized in that, The staggered arrangement order of the flat sub-parts of the plurality of flat sub-layers in the first direction, and the staggered arrangement order of the stepped sub-parts of the plurality of flat sub-layers in the first direction, are different from the stacking order of the plurality of flat sub-layers in the direction from the base to the flat layer.

6. The display panel according to claim 5, characterized in that, The plurality of flat sublayers includes a first flat sublayer, a second flat sublayer, and a third flat sublayer; The first flat sublayer, the second flat sublayer, and the third flat sublayer are stacked sequentially in the direction from the substrate to the flat layer, and the first flat sublayer, the third flat sublayer, and the second flat sublayer are staggered sequentially in the first direction.

7. The display panel according to claim 6, characterized in that, The stepped portion of the first flat sublayer has a first stepped surface; The stepped portion of the second flat sublayer is located on the stepped portion and the flat portion of the first flat sublayer, and the flat portion of the second flat sublayer is located on the flat portion of the first flat sublayer; The stepped portion of the third flat sublayer includes a first portion and a second portion connected together. The first portion is located on the stepped portion of the second flat sublayer and has a second stepped surface. The second portion is located on the stepped portion and the flat portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the flat portion of the second flat sublayer and has a fourth stepped surface.

8. The display panel according to claim 6, characterized in that, The stepped portion of the first flat sublayer has a first stepped surface; The stepped portion and the flat portion of the second flat sublayer are both located on the flat portion of the first flat sublayer; The stepped portion of the third flat sublayer includes a first portion and a second portion connected together. The first portion is located on the stepped portion and the flat portion of the first flat sublayer and has a second stepped surface. The second portion is located on the flat portion of the first flat sublayer and the stepped portion of the second flat sublayer and has a third stepped surface. The flat portion of the third flat sublayer is located on the stepped portion and the flat portion of the second flat sublayer and has a fourth stepped surface.

9. The display panel according to claim 8, characterized in that, The heights of the first step surface, the second step surface, the third step surface, and the fourth step surface increase in the first direction.

10. The display panel according to claim 9, characterized in that, The height of the second step surface has a first difference from the height of the first step surface, the height of the third step surface has a second difference from the height of the second step surface, and the height of the fourth step surface has a third difference from the height of the third step surface. Wherein, the first difference is greater than the second difference, and the second difference is greater than the third difference.

11. The display panel according to claim 2, characterized in that, The stepped section is provided with multiple grooves, which are arranged around the center of the overlapping through hole; In this configuration, on the reference plane, the trenches of two adjacent flat sublayers are staggered, and the size of the trench of one of the flat sublayers on the side away from the substrate is smaller than the size of the trench of the other flat sublayer on the side closer to the substrate; the reference plane is parallel to the light-emitting surface of the display panel.

12. The display panel according to claim 11, characterized in that, The plurality of flat sublayers include a first flat sublayer, a second flat sublayer, and a third flat sublayer, wherein the first flat sublayer, the second flat sublayer, and the third flat sublayer are stacked sequentially in the direction from the substrate to the flat layer; Wherein, on the reference plane, along the first direction, the second flat sublayer is recessed relative to the first flat sublayer, and the third flat sublayer is recessed relative to the second flat sublayer.

13. The display panel according to any one of claims 1 to 12, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area; The flat layer includes a flat portion and a ramp portion disposed on at least one side of the flat portion. The ramp portion is located within the non-display area, and the thickness of the ramp portion is less than or equal to the thickness of the flat portion. The first electrode layer has multiple vent holes, which penetrate the first electrode layer along the thickness direction of the display panel, and the distance between the vent holes and the surface of the ramp portion away from the flat portion is greater than or equal to 50 micrometers.

14. The display panel according to claim 13, characterized in that, Of the plurality of vents, at least some of the vents are arranged along a predetermined path surrounding the display area; The preset path includes an arc-shaped path, which is located at a corner of the preset path, and at least some of the exhaust holes are sequentially arranged along the arc-shaped path.

15. The display panel according to claim 14, characterized in that, The plurality of vent holes include a first vent hole and a second vent hole arranged adjacent to each other, wherein the size of the first vent hole is greater than or equal to the size of the second vent hole.

16. A display device, characterized in that, Includes the display panel as claimed in any one of claims 1 to 15.

Images