Failure analysis sample of image sensor and preparation method thereof, and analysis method of failure of image sensor

Abstract

This invention provides a failure analysis sample for an image sensor and its preparation method, as well as a method for analyzing image sensor failures, belonging to the field of image sensors. The method for preparing the failure analysis sample includes providing a bonding wafer, which includes a cover plate structure and an image sensor wafer; forming bonding pillars in the cover plate structure, the bonding pillars penetrating the cover plate structure and connecting to pads, and forming bonding bumps on the surface of the cover plate structure; obtaining the failed chip therein; and sequentially performing surface mounting, signal connection, and molding processing on the diced failed chip to complete the preparation of the failure chip analysis sample. This invention, by adding a cover plate structure for signal extraction, effectively protects the pixel structure of the failed chip sample, preventing secondary damage caused by silicon shavings during sample preparation and physical contact with the pixel area surface during packaging, thus reducing secondary failures caused by sample preparation in subsequent failure analysis.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a failure analysis sample of an image sensor and its preparation method, as well as a failure analysis method for image sensors. Background Technology

[0002] Generally speaking, chip failure is inevitable during the research, development, production, and use of chips. As people's requirements for product quality and reliability continue to increase, failure analysis is becoming increasingly important. Through chip failure analysis, chip designers can find problems such as design defects, mismatches in process parameters, or improper design and operation.

[0003] Image sensors (CMOS Image Sensors, CIS) that require analysis of defective chips after CP testing necessitate sending the wafer to a dicing station for dicing, then mounting it onto a PCB board, wire bonding to extract signals, and finally covering it with a glass cover to complete the sample preparation. However, the wafer dicing process generates silicon shavings and metal circuit debris. During dicing and rinsing, these debris can easily damage the circuitry and pixel structure on the wafer surface, introducing new circuit and image failure factors. This makes it difficult to accurately pinpoint the true cause of failure during CP testing in subsequent FA failure analysis.

[0004] Furthermore, during the wafer dicing and packaging process, chip placement and manual handling at the chip handling station can easily come into contact with the surface of the pixel structure area. For example, physical contamination in the placement nozzle can easily damage the pixel structure, leading to the creation of chip failure samples and introducing new failure modes such as dead pixels and dead lines. In subsequent FIB analysis, the glass cover needs to be removed before performing failure analysis on the chip. Removing the glass cover can easily generate glass fragments, which can damage the circuitry and introduce new causes of failure.

[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a failed chip analysis sample and its preparation method, as well as a failed chip analysis method, to solve the problem that new failure causes will arise during the failure analysis of failed chips after they have been manufactured.

[0007] To address the aforementioned technical problems, this invention provides a method for preparing a failure analysis sample for an image sensor, comprising:

[0008] A bonding wafer is provided, the bonding wafer including a cover plate structure and an image sensor wafer, the upper wafer of the bonding wafer being the cover plate structure, the lower wafer being the image sensor wafer, the surface of the image sensor wafer having pads for signal detection, and the cover plate structure being made of a transparent material;

[0009] A bonding post is formed in the cover plate structure, the bonding post penetrates the cover plate structure and connects to the pad, and bonding bumps are formed on the surface of the cover plate structure;

[0010] After the bonding pillars are connected to the pads, the bonded wafer is diced into several chips, and the failed chips are obtained.

[0011] After being cut, the failed chips are sequentially subjected to surface mounting, signal connection, and encapsulation to complete the sample preparation for analysis of the failed chips.

[0012] Preferably, the step of forming a bonding post in the cover plate structure, the bonding post penetrating the cover plate structure and connecting to the pad, and forming bonding bumps on the surfaces of the pad and the cover plate structure respectively includes:

[0013] Drill holes in the cover plate structure corresponding to the pad positions, and form through holes that penetrate the cover plate structure.

[0014] Metal is deposited in the through-hole to form a bonding pillar, the bonding pillar at least partially protruding from the cover plate structure, the bonding pillar forming bonding bumps on the surface of the cover plate structure;

[0015] The cover plate structure is pressed together with the wafer to connect the bonding pillars to the pads.

[0016] Preferably, drilling holes in the cover plate structure corresponding to the pad positions includes:

[0017] A mask is provided on the surface of the cover plate structure, the mask having light-transmitting holes;

[0018] Based on the coordinates of the chip marked as a failure during wafer CP inspection, the position coordinates of the pads of the failure chip are obtained;

[0019] Based on the position coordinates of the pads, the light-transmitting holes are correlated with the positions of the pads;

[0020] Laser drilling was used to drill holes in the cover plate structure at the positions corresponding to the light-transmitting holes.

[0021] Preferably, the metal deposited in the through-hole is a copper-nickel alloy.

[0022] Preferably, the bonding bumps extend 20 micrometers beyond the surface of the cover plate structure.

[0023] Preferably, the cover plate structure is connected to the wafer using thermo-press bonding technology to connect the bonding pillars to the pads.

[0024] Preferably, the step of sequentially performing surface mounting, signal connection, and encapsulation processes on the cut failed chips to obtain failed chip analysis samples includes:

[0025] The failed chip was attached to the PCB board;

[0026] After the failed chip is mounted, wire bonding is used to connect the bonding bumps led out from the bonding posts to the PCB board through bonding wires, so as to connect the pads to the PCB board signals.

[0027] After the bonding posts are connected to the PCB board, the connection between the bonding leads and the PCB board is encapsulated to protect the bonding leads and expose the area where the pixel structure of the failed chip is located.

[0028] Preferably, the cover plate structure is made of glass or a transparent resin material.

[0029] Based on the same inventive concept, the present invention also provides a failure analysis sample for an image sensor, comprising:

[0030] The failed chip has pads on its surface for signal detection;

[0031] A cover plate structure covers the side of the failed chip that has solder pads, and the cover plate structure is made of a transparent material;

[0032] A bonding post penetrates the cover plate structure and connects to the pad, and forms a bonding bump on the surface of the cover plate structure;

[0033] The PCB board is connected to the other side of the failed chip; and

[0034] The bonding leads are connected to the bonding bumps and the PCB board respectively to connect the pads and the PCB board signals.

[0035] Preferably, the failure analysis sample of the image sensor further includes a molding die cover plate, which is connected to the cover plate structure and the PCB board respectively, and exposes the area where the pixel structure of the failed chip is located. The molding die cover plate is configured to protect the bonding wires.

[0036] Preferably, the failed chip is bonded to the cover plate structure using thermo-press bonding technology to connect the bonding post to the pad.

[0037] Preferably, the bonding post is made of a copper-nickel alloy.

[0038] Based on the same inventive concept, this invention also provides a method for analyzing image sensor failure, comprising:

[0039] Provide failure analysis samples of the image sensor as described above;

[0040] The plastic encapsulation mold cover is removed by heating, and the bonding bumps leading out of the bonding pillars on the cover structure are reconnected using FIB technology to perform failure analysis on the failed chip. The cover structure is made of transparent material.

[0041] Compared with the prior art, the image sensor failure analysis sample preparation method of the present invention has the following advantages:

[0042] This invention involves forming bonding pillars on the surface of a cover plate structure made of transparent material and connecting these pillars to the pads of the failed chip, thereby bringing the signal from the failed chip to the surface of the cover plate structure. When analyzing the failed chip, covering the chip surface with the cover plate structure effectively protects the pixel structure of the failed chip sample, preventing secondary damage caused by silicon shavings during sample preparation and physical contact with the pixel structure area during packaging, thus reducing secondary failures caused by sample preparation in subsequent failure analysis.

[0043] The failure chip analysis sample and failure chip analysis method provided by this invention belong to the same inventive concept as the failure analysis sample preparation method of the image sensor provided by this invention. Therefore, the failure chip analysis sample and failure chip analysis method provided by this invention have at least all the advantages of the failure analysis sample preparation method of the image sensor provided by this invention, preventing secondary damage caused by silicon chips during the sample preparation process and physical contact with the surface of the pixel structure during the packaging process, and reducing secondary failures caused by sample preparation in subsequent failure analysis. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the test results obtained from CP testing on a wafer;

[0045] Figure 2 It is an electronic scan image of a chip surface with defects;

[0046] Figure 3 This is a schematic diagram illustrating the positional relationship between the glass cover and the chip in existing technology;

[0047] Figure 4 This is a flowchart of a method for preparing a failure analysis sample for an image sensor according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the structure after drilling holes in the cover plate structure in one embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the process after metal deposition in a through-hole, according to one embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of a wafer being cut into chips according to an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of the connection between the pad and the bonding post in one embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the structure in one embodiment of the present invention, showing the bonding post and the PCB board connected by bonding leads;

[0053] Figure 10 This is a schematic diagram of the chip structure after molding in one embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of a cover plate structure using FIB interconnection in one embodiment of the present invention.

[0055] In the picture,

[0056] 10 - COB substrate; 20 - Glass cover;

[0057] 30 - CIS chip; 40 - Connecting cable;

[0058] 50 - Molding mold; 100 - Cover plate structure;

[0059] 110 - Through hole; 120 - Laser equipment;

[0060] 130 - Bonding post; 200 - Image sensor wafer;

[0061] 210 - Pads; 220 - Pixel structure;

[0062] 230 - Cutting wheel; 240 - Bonding wire;

[0063] 250 - Molding mold cover plate; 300 - PCB board;

[0064] 400 - Failed chip. Detailed Implementation

[0065] To make the objectives, advantages, and features of the present invention clearer, the following further elaborates in detail on the failure analysis sample of the image sensor proposed by the present invention, its preparation method, and the analysis method for image sensor failures in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in extremely simplified forms and use non-precise scales, solely for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used commonly between different drawings to represent the same or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0066] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0067] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0068] As shown Figures 1 to 3 in the figure, by performing CP detection on the CIS wafer (hereinafter referred to as "wafer"), the detection results as shown Figure 1 in the figure can be obtained. From Figure 1As can be seen, the area indicated by arrow b is green, meaning the CIS chip 30 located there is a valid chip. The area indicated by arrow a is red, meaning the CIS chip 30 located there is a failed chip. The failed chips will be analyzed next to determine the cause of the failure, providing data for subsequent improvements to the chip manufacturing process and design. Figure 3 A schematic diagram showing the positional relationship between the glass cover and the chip in a failed chip sample fabricated using existing technology. Figure 3 As can be seen, chip 30 is mounted onto COB substrate 10 (i.e., PCB board). To protect the connection line 40, a molding die 50 is formed on both sides of the connection line 40 through molding. A glass cover 20 is provided on the surface of the molding die 50. During the packaging process after wafer dicing, when the chip is mounted onto COB substrate 10, manual handling at the wafer handling station can easily come into contact with the surface of the pixel structure area. For example, if there is physical contamination in the placement nozzle, it can easily cause damage to the pixel structure. Making chip failure samples will introduce new failure modes such as dead pixels and dead lines. During the failure analysis of chip 30, the molding die 50 is removed by heating, and the glass cover 20 is also removed at the same time. Since the glass cover 20 needs to be removed during chip dicing, silicon chips and metal circuit debris are generated during wafer dicing. During dicing and rinsing, these debris can easily damage the circuit and pixel structure on the surface of the wafer, forming... Figure 2 The white dot indicated by arrow c represents a factor that can cause new circuit and image failures, making it difficult to accurately pinpoint the true cause of failure during CP testing in subsequent FA failure analysis. During subsequent FIB analysis, removing the glass cover 20 can easily generate glass fragments, which can damage the circuit and create new causes of failure.

[0069] The core idea of ​​this invention is to provide a method for preparing a failure analysis sample for an image sensor, so that when the image sensor is manufactured and failure analysis is performed, new causes of failure are avoided.

[0070] To achieve the above-mentioned goals, this invention provides a method for preparing samples for failure analysis of image sensors, referring to... Figures 4 to 11 This invention discloses a specific embodiment of a method for preparing failure analysis samples for an image sensor. The method includes the following steps S1 to S4.

[0071] Step S1: Provide a bonding wafer, the bonding wafer including a cover plate structure 100 and an image sensor wafer 200, the upper part of the bonding wafer is the cover plate structure 100, the lower part of the wafer is the image sensor wafer 200, the surface of the image sensor wafer 200 has pads for signal detection, and the cover plate structure 100 is made of a transparent material.

[0072] Specifically, refer to Figure 4 , Figures 5 to 8 As shown, a wafer is provided, the wafer being as follows: Figure 7 The image sensor disc 200 shown is a CIS wafer. The explanation will continue using a CIS wafer as an example. A cover plate structure 100 covers the surface of the wafer. After wafer dicing, it includes a failed chip 400 and a valid chip. In this embodiment, the failed chip 400 is the chip to be analyzed. The surface of the failed chip 400 has pads 210 for signal detection and pixel structures 220. The cover plate structure 100 is made of glass or a transparent resin material, such as acrylic. In this embodiment, a glass sheet is preferred as the cover plate structure 100. In this embodiment, a 12-inch wafer is used as an example; preferably, the size of the glass sheet is equal to the size of the wafer. There are no specific requirements for the thickness of the glass sheet, as long as it can protect the wafer and prevent debris generated during dicing and washing from damaging the circuitry and pixel structures 220 on the wafer surface. The following explanation will use a glass sheet as the cover plate structure 100.

[0073] Step S2: A bonding post 130 is formed in the cover plate structure 100. The bonding post 130 penetrates the cover plate structure 100 and connects to the pad. A bonding bump (not shown in the figure) is formed on the surface of the cover plate structure 100.

[0074] Specifically, refer to Figures 4 to 7 As shown, forming bonding pillars 130 on the surface of the glass sheet includes:

[0075] First, a hole is drilled in the cover plate structure 100 corresponding to the position of pad 210, and the formed through hole 110 penetrates the glass sheet. As one embodiment, drilling the hole in the glass sheet corresponding to the position of pad 210 includes: first, setting a mask (not shown in the figure) on the surface of the glass sheet, the mask having a light-transmitting hole; then, obtaining the position coordinates of the pad 210 of the failed chip 400 based on the coordinates of the failed chip 400 marked in the wafer CP inspection; second, aligning the light-transmitting hole with the position of the pad 210 based on the position coordinates of the pad 210; finally, drilling the hole in the glass sheet corresponding to the position of pad 210 using a laser drilling device 120, forming the through hole 110, and the formed through hole 110 penetrates the cover plate structure 100. In another embodiment, the laser device 120 can be fixed above the glass plate, and then the position coordinates of the pad 210 can be obtained based on the coordinates of the failed chip 400 marked in the wafer CP inspection. The cover plate structure 100 can be rotated so that the glass plate at the corresponding position of the pad 210 can be opened to open the laser device 120 for drilling.

[0076] It should be noted that in this step, regardless of the method used, as long as a hole can be drilled in the glass plate at the corresponding position of the pad 210, it is not limited to the embodiments listed above.

[0077] Next, metal is deposited in the via 110 to form bonding pillars 130, which at least partially protrude from the glass sheet, forming bonding bumps on the surface of the glass sheet. The metal deposited in the via 110 can be copper, a metal alloy, etc. In this embodiment, a copper-nickel alloy is preferably deposited. To achieve the connection of the bonding pillars 130, the bonding pillars 130 at least partially protrude from the glass sheet. Considering subsequent process steps, such as molding, preferably, the bonding bumps extend 20 micrometers beyond the surface of the glass sheet.

[0078] Finally, the glass sheet is pressed together with the wafer to connect the bonding post 130 to the pad 210. The glass sheet is connected to the wafer using thermoforming bonding technology to connect the bonding post 130 to the pad 210.

[0079] Step S3: After the bonding post 130 is connected to the pad, the bonding wafer is cut into several chips, and the failed chip 400 is obtained.

[0080] Specifically, refer to Figure 4 and Figure 7 As shown, after the bonding post 130 is connected to the pad 210, the wafer is diced along the edge using a dicing wheel 230. Figure 7 In the direction indicated by arrow d, the wafer is cut into several chips, and the failed chip 400 is obtained.

[0081] Step S4: After cutting, the failed chip 400 is sequentially subjected to surface mounting, signal connection and plastic encapsulation to complete the sample preparation for analysis of the failed chip.

[0082] Specifically, refer to Figure 4 , Figures 8 to 11 As shown, the cut-up failed chip 400 was sequentially subjected to surface mounting, signal connection, and encapsulation processes to obtain failed chip analysis samples, including:

[0083] First, the failed chip 400 is mounted onto the PCB board 300.

[0084] Next, after the failed chip 400 is mounted, the bonding bumps led out from the bonding post 130 are connected to the PCB board 300 by bonding wire 240 using wire bonding method, so as to connect the pad 210 with the signal of the PCB board 300.

[0085] Then, after the bonding post 130 is connected to the PCB board 300, the connection point between the bonding lead 240 and the PCB board 300 is encapsulated to protect the bonding lead 240 and expose the area where the pixel structure 220 of the failed chip 400 is located. A molding die cover 250 is used to protect the bonding post 130, the bonding lead 240, and the connection point between the bonding lead 240 and the PCB board 300. However, the molding die cover 250 does not encapsulate the cover structure 100 located at the corresponding position of the pixel structure 220.

[0086] After encapsulation, using the FIB method, signals on the glass slide can be arbitrarily interconnected via FIB, i.e., as... Figure 11 The connection structure is shown by arrow f. Then, the failed chip 400 is analyzed.

[0087] In this embodiment, by adding a glass plate for signal extraction, the pixel structure 220 of the failed chip 400 sample is effectively protected, reducing the probability of secondary circuit damage from 5% to 0% compared to previous sample preparation methods. A redesigned molding die cover 250 provides structural protection for the bonding leads 240 of the transport chip before FIB. By adopting the structure of this embodiment, the defect rate of pixel structure 220 damage during subsequent RDL circuit modifications after FIB is reduced from 1.5% to 0%.

[0088] This embodiment forms bonding pillars 130 on the surface of a glass sheet and connects the bonding pillars 130 to the pads 210 of the failed chip 400, thereby bringing the signal of the failed chip 400 to the surface of the glass sheet. When analyzing the failed chip, covering the chip surface with a glass sheet effectively protects the pixel structure of the failed chip sample, preventing secondary damage caused by silicon shavings during sample preparation and physical contact with the pixel structure 220 during packaging, thus reducing secondary failures caused by sample preparation in subsequent failure analysis.

[0089] To achieve the above ideas, participants Figure 9 and Figure 10As shown, this embodiment also discloses a failure analysis sample of an image sensor, including: a failure chip 400 with pads 210 on its surface for signal detection; a cover structure 100 covering the side of the failure chip 400 with pads, the cover structure 100 being made of a transparent material; a bonding post 130 penetrating the cover structure 100 and connecting to the pads 210, and forming bonding bumps on the surface of the cover structure 100; the failure chip 400 and the cover structure 100 being bonded by thermoforming bonding technology to connect the bonding post 130 to the pads 210; the bonding post 130 being made of a copper-nickel alloy; a PCB board 300 connected to the other side of the failure chip 400; and bonding leads 240 connected to the bonding bumps and the PCB board 300 respectively to enable signal communication between the pads 210 and the PCB board 300.

[0090] Furthermore, participants Figure 10 As shown, the failure analysis sample of the image sensor also includes a molding die cover 250, which is connected to the cover structure 100 and the PCB board 300 respectively, and exposes the area where the pixel structure 220 of the failed chip is located. The molding die cover 250 is configured to protect the bonding wires 240.

[0091] To achieve the above idea, this embodiment also discloses a method for analyzing image sensor failure, including:

[0092] Provide failure analysis samples of the image sensor as described above;

[0093] The molding die cover 250 is removed by heating. The bonding bumps leading from the bonding posts 130 on the cover structure 100 are then reconnected using FIB (Focused Ion Beam) technology to perform failure analysis on the failed chip 400. The cover structure 100 is made of a transparent material. The FIB technology is a focused ion beam technique.

[0094] The failed chip analysis sample provided in this embodiment can utilize FIB technology to perform RDL interconnections between different signals led out from the cover plate structure 100, enabling circuit failure analysis. FIB technology is used to fabricate a redistribution layer (RDL) on a non-traditional semiconductor substrate such as a glass sheet. RDL is a technique used to redistribute fine-pitch pads within a chip to wider-pitch pads, facilitating connections with other components or circuit boards. FIB technology allows for the creation of tiny, precise conductive paths on the glass sheet, enabling connections between different signals. During circuit failure analysis, engineers need to access specific nodes within the chip to monitor signals or apply voltages, operations that are typically difficult to perform directly after chip packaging. The RDL created using FIB technology provides external access to these internal nodes, allowing engineers to more easily perform various tests and measurements, thereby accurately identifying the causes of circuit failures.

[0095] The failed chip analysis sample provided in this embodiment can also have multiple pads 210 on the surface of the cover plate structure 100 to lead out the same signal. These pads can be distributed in different positions to facilitate contact by the probes (pins) of the test equipment, and can also be used as pins for subsequent tests. While pinning, the underlying CIS wafer is not damaged, and the chip circuit is not damaged due to excessively deep pinning during CP testing.

[0096] The failed chip analysis sample and the method for failed chip analysis provided in this embodiment belong to the same inventive concept as the image sensor failed analysis sample preparation method provided in this embodiment. Therefore, the failed chip analysis sample and the method for failed chip analysis provided in this embodiment have at least all the advantages of the image sensor failed analysis sample preparation method provided in this embodiment. They prevent secondary damage caused by silicon chips during the sample preparation process and by physical contact with the surface of the pixel structure 220 during the packaging process, thereby reducing secondary failures caused by sample preparation in subsequent failure analysis.

[0097] In summary, the above embodiments have provided detailed descriptions of different configurations of failure analysis samples and preparation methods for image sensors, as well as failure analysis methods for image sensors. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A failure analysis sample for an image sensor, characterized in that, include: The failed chip has pads on its surface for signal detection; A cover plate structure covers the side of the failed chip that has solder pads, and the cover plate structure is made of a transparent material; A bonding post penetrates the cover plate structure and connects to the pad, and forms a bonding bump on the surface of the cover plate structure; The PCB board is connected to the other side of the failed chip; and The bonding leads are connected to the bonding bumps and the PCB board respectively to connect the pads and the PCB board signals.

2. The failure analysis sample of the image sensor according to claim 1, characterized in that, The failure analysis sample of the image sensor also includes a molding die cover plate, which is connected to the cover plate structure and the PCB board respectively, and exposes the area where the pixel structure of the failed chip is located. The molding die cover plate is configured to protect the bonding wires.

3. The failure analysis sample of the image sensor according to claim 1, characterized in that, The failed chip is bonded to the cover plate structure using thermo-press bonding technology to connect the bonding post to the pad.

4. The failure analysis sample of the image sensor according to claim 1, characterized in that, The bonding pillars are made of a copper-nickel alloy.

5. A method for preparing a failure analysis sample for an image sensor as described in any one of claims 1-4, characterized in that, include: A bonding wafer is provided, the bonding wafer including a cover plate structure and an image sensor wafer, the upper wafer of the bonding wafer being the cover plate structure, the lower wafer being the image sensor wafer, the surface of the image sensor wafer having pads for signal detection, and the cover plate structure being made of a transparent material; A bonding post is formed in the cover plate structure, the bonding post penetrates the cover plate structure and connects to the pad, and bonding bumps are formed on the surface of the cover plate structure; After the bonding pillars are connected to the pads, the bonded wafer is diced into several chips, and the failed chips are obtained. as well as After being cut, the failed chips are sequentially subjected to surface mounting, signal connection, and encapsulation to complete the sample preparation for analysis of the failed chips.

6. The method for preparing a failure analysis sample for an image sensor according to claim 5, characterized in that, The step of forming bonding pillars in the cover plate structure, wherein the bonding pillars penetrate the cover plate structure and connect to the pads, and forming bonding bumps on the surfaces of the pads and the cover plate structure respectively includes: Drill holes in the cover plate structure corresponding to the pad positions, and form through holes that penetrate the cover plate structure. Metal is deposited in the through-hole to form a bonding pillar, the bonding pillar at least partially protruding from the cover plate structure, the bonding pillar forming bonding bumps on the surface of the cover plate structure; The cover plate structure is pressed together with the wafer to connect the bonding pillars to the pads.

7. The method for preparing a failure analysis sample for an image sensor according to claim 6, characterized in that, Drilling holes in the cover plate structure corresponding to the pad locations includes: A mask is provided on the surface of the cover plate structure, the mask having light-transmitting holes; Based on the coordinates of the chip marked as a failure during wafer CP inspection, the position coordinates of the pads of the failure chip are obtained; Based on the position coordinates of the pads, the light-transmitting holes are correlated with the positions of the pads; Laser drilling was used to drill holes in the cover plate structure at the positions corresponding to the light-transmitting holes.

8. The method for preparing a failure analysis sample for an image sensor according to claim 6, characterized in that, The cover plate structure is connected to the wafer using thermo-press bonding technology to connect the bonding pillars to the pads.

9. The method for preparing a failure analysis sample for an image sensor according to claim 5, characterized in that, The process of sequentially mounting, signal connecting, and encapsulating the cut-out failed chips to obtain failed chip analysis samples includes: The failed chip was attached to the PCB board; After the failed chip is mounted, wire bonding is used to connect the bonding bumps led out from the bonding posts to the PCB board through bonding wires, so as to connect the pads to the PCB board signals. After the bonding posts are connected to the PCB board, the connection between the bonding leads and the PCB board is encapsulated to protect the bonding leads and expose the area where the pixel structure of the failed chip is located.

10. A method for analyzing image sensor failure, characterized in that, include: Provide a failure analysis sample of an image sensor as described in any one of claims 1-4; The bonding bumps leading out of the bonding pillars on the cover plate structure are reconnected using FIB technology to perform failure analysis on the failed chip. The cover plate structure is made of transparent material.

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