Marking methods for exposure patterns in wafer manufacturing

CN122138676APending Publication Date: 2026-06-02SHANGHAI IND U TECH RES INST
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI IND U TECH RES INST
Filing Date
2025-01-09
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

In the wafer manufacturing process, the high repetition of exposure patterns makes it difficult to detect anomalies. Existing technologies cannot quickly and accurately locate the location of anomalies, affecting production efficiency and product quality.

Method used

Patterns containing positional information are embedded during wafer manufacturing. By creating spacer stripes or markers in the exposed pattern, these patterns are ensured to remain in the chip after wafer dicing. These patterns are used to indicate the position of the original exposed pattern.

Benefits of technology

It enables precise marking and rapid traceability of chips on wafers, simplifies the anomaly investigation process, improves production efficiency and product quality, and is suitable for complex manufacturing and packaging environments.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122138676A_ABST
    Figure CN122138676A_ABST
Patent Text Reader

Abstract

This application relates to a marking method for exposure patterns in wafer fabrication. The method includes acquiring an exposure pattern used in wafer fabrication and determining usable locations within the exposure pattern for embedding position information. Subsequently, patterns including position information are formed on these usable locations; these patterns can be spaced stripes or marker dots. After wafer dicing, the pattern containing position information is partially or entirely retained in the diced chip, thereby enabling precise tracking of the chip's original position on the wafer. This application provides three embodiments, including spaced stripes, marker dots, and selectively formed independently on opposite sides of a chip's functional area. This application also proposes creating patterns including position information during the packaging process, forming the patterns on a packaging material layer. Using the method of this application, pattern information can be quickly determined, and its specific location on the wafer can be traced, thereby facilitating rapid localization of possible process flow segments.
Need to check novelty before this filing date? Find Prior Art