Cache policy test method and device, electronic equipment and computer readable storage medium

Abstract

The present application relates to solid state disk testing technology, provide a kind of cache strategy test method, device, electronic equipment and computer readable storage medium, applied to electronic equipment, the method comprises: first clear original data in solid state disk again to solid state disk write new data until write is completed;According to each preset time length in a plurality of preset time lengths set in advance, in each time start read operation, first wait corresponding preset time length after again issue multiple read requests randomly read new data when read operation, and record the logical address and read delay of each read request issued in each read operation;According to the logical address and read delay of all read requests issued in each read operation, generate the read delay distribution graph of each read operation;The read delay distribution graph of all read operations is analyzed, and the current release strategy in cache strategy is determined.The present application can improve test efficiency and avoid test influence solid state disk life when testing cache release strategy.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive testing technology, and more specifically, to a caching strategy testing method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] With the continuous development of NAND Flash technology, the storage density of flash media types has been continuously increasing, from SLC (Single-Level Cell, where a cell is the smallest physical unit for data storage), MLC (Multi-Level Cell), TLC (Triple-Level Cell), QLC (Quad-Level Cell), to PLC (Penta-Level Cell), with storage densities ranging from 1 bit / cell to 5 bits / cell, respectively. As storage density increases, the performance and lifespan of solid-state drives based on NAND Flash continue to decrease.

[0003] Flash memory is erased in blocks and managed through an erase-program model. Non-SLC (MLC / TLC / QLC, etc.) blocks can be converted into lower-density flash memory blocks through hardware or software. For example, current consumer-grade SSDs commonly use TLC flash memory, and manufacturers typically simulate a certain number of TLC blocks as SLC blocks as data cache to improve drive performance. When the host writes data to the SSD, the drive controller first writes the data to the cache. When idle, it moves the data in the cache to the non-cache area, and then releases the cache area to restore optimal performance.

[0004] Caching strategies are crucial for optimizing the read and write performance of solid-state drives (SSDs). However, manufacturers typically do not directly provide SSD caching strategies. Existing technologies determine the release strategy by performing multiple writes to the SSD and observing the speed changes after these writes. However, this method of determining the release strategy is inefficient and severely impacts the lifespan of the SSD. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, electronic device, and computer-readable storage medium for testing caching strategies.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a caching strategy testing method applied to an electronic device, wherein the electronic device is communicatively connected to a solid-state drive, the method comprising:

[0008] First, clear the existing data in the solid-state drive, then write new data to the solid-state drive until the writing is complete;

[0009] Each time a read operation is initiated, the system waits for the corresponding preset duration before issuing multiple read requests to randomly read the new data, and records the logical address and read latency of each read request issued in each read operation.

[0010] Based on the logical addresses and read latency of all read requests issued for each read operation, generate a read latency distribution map for each read operation;

[0011] Analyze the read latency distribution of all read operations to determine the current release strategy in the cache policy.

[0012] In an optional implementation, the step of generating a read latency distribution map for each read operation based on the logical addresses and read latency of all read requests issued for each read operation includes:

[0013] For any read operation, the read latency of all read requests is sorted in ascending order of their logical addresses to obtain the read latency sequence of the read operation.

[0014] Using the logical address as the x-axis and the read latency as the y-axis, a read latency distribution map of the read operation is generated based on the read latency sequence of the read operation, and finally the read latency distribution map of each read operation is obtained.

[0015] In an optional implementation, the step of analyzing the read latency distribution of all read operations to determine the current release strategy in the cache strategy includes:

[0016] Analyze the read latency distribution of all read operations to determine the release start time, release wait time, and release end time. The release start time is the time when the new data begins to be released from the cache to the non-cache. The release wait time is the time from when the new data is written to the release start time. The release end time is the time when all the new data is released from the cache to the non-cache.

[0017] The release rate is calculated based on the release start time, the release end time, and the amount of new data.

[0018] The release waiting time and the release rate are used as the current release strategy.

[0019] In an optional implementation, the read latency distribution map for each read operation is plotted with the logical address as the x-axis and the read latency as the y-axis. The step of analyzing the read latency distribution maps of all read operations to determine the release start time, release waiting time, and release end time includes:

[0020] For each two consecutive read operations, the target line segments corresponding to the same preset logical address range in the read latency distribution diagram are compared one by one. If the read latency of the target line segment in the previous read latency distribution diagram is less than the read latency of the target line segment in the subsequent read latency distribution diagram, then the start time of the subsequent read operation is taken as the release start time.

[0021] The release waiting time is determined based on the release start time and the new data write end time.

[0022] Each reference delay distribution map is determined from the read delay distribution map of all the read operations, and each reference delay distribution map contains only multiple line segments that are parallel to the x-axis and are cyclically distributed;

[0023] The release end time is determined based on the reference delay distribution map of the earliest read operation.

[0024] In an optional implementation, after the step of analyzing the read latency distribution map of all read operations and determining the current release strategy in the cache strategy, the following is included:

[0025] Obtain a reference release strategy. Both the reference release strategy and the current release strategy include a release wait time and a release rate. When determining the reference release strategy, the amount of data written is different from the amount of data in the new data.

[0026] If the difference between the release waiting time and the release rate of the reference release strategy and the current release strategy are both within the set range, then the caching strategy of the solid-state drive is determined to be a fixed release strategy; otherwise, the caching strategy of the solid-state drive is determined to be a non-fixed release strategy.

[0027] In an optional implementation, the method further includes:

[0028] Data is written sequentially to the solid-state drive;

[0029] When the data writing is complete, multiple read requests are issued to randomly read the written data, and the logical address to be read and the read latency of each read request are recorded.

[0030] Based on the logical addresses and read latency of all the read requests, a read latency distribution map is generated for this read latency, with the logical address as the x-axis and the read latency as the y-axis.

[0031] If the current read latency distribution graph contains both a first line segment and multiple cyclically distributed second line segments, then the size of the logical space between the starting logical address and the ending logical address corresponding to the first line segment is determined as the cache size. Here, the first line segment and each of the second line segments are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any of the second line segments.

[0032] In an optional implementation, the method further includes:

[0033] The same amount of data is written sequentially to different logical spaces of the solid-state drive twice in succession;

[0034] Multiple read requests are sent to the logical space to read data randomly, and the logical address and read latency of each read request are recorded.

[0035] Determine whether the data written in the next instance is in the cache based on the logical address and read latency of all the read requests issued in the next instance;

[0036] If the data written in the last instance is in the cache, then the cache configuration of the caching strategy is determined to be a non-fixed size configuration; otherwise, the cache configuration of the caching strategy is determined to be a fixed size configuration.

[0037] In an optional implementation, the step of determining whether the data written in the next transaction is in the cache based on the logical address and read latency of all the subsequent read requests includes:

[0038] Based on the logical addresses and read latency of all the read requests issued in the next iteration, a read latency distribution map for the next iteration is generated. The read latency distribution map for the next iteration is plotted with logical address as the x-axis and read latency as the y-axis.

[0039] If the subsequent read latency distribution graph contains both a first line segment and multiple cyclically distributed second line segments, and both the first line segment and each of the second line segments are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any of the second line segments, then it is determined that the data written in the subsequent transaction is in the cache area; otherwise, it is determined that the data written in the subsequent transaction is not in the cache area.

[0040] Secondly, the present invention provides a caching strategy testing device applied to an electronic device, wherein the electronic device is communicatively connected to a solid-state drive, and the device includes:

[0041] The write module is used to first clear the existing data in the solid-state drive and then write new data to the solid-state drive until the writing is complete.

[0042] The reading module is used to sequentially wait for the corresponding preset duration before issuing multiple read requests to randomly read the new data each time a read operation is started, according to each of the preset durations. The module also records the logical address and read latency of each read request issued in each read operation.

[0043] The generation module is used to generate a read latency distribution map for each read operation based on the logical address and read latency of all read requests issued for each read operation.

[0044] The determination module is used to analyze the read latency distribution map of all read operations and determine the current release strategy in the cache strategy.

[0045] Thirdly, the present invention provides an electronic device including a processor and a memory, the memory being used to store a program, and the processor being used to implement the caching strategy testing method as described in any of the foregoing embodiments when executing the program.

[0046] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the caching strategy testing method as described in any of the foregoing embodiments.

[0047] Compared with the prior art, the present invention has the following beneficial effects: The present invention uses a write-once-read-many approach, and utilizes the logical address of the read request and the read latency generated by each read operation to generate a read latency distribution map. By analyzing the read latency distribution map, the release strategy in the cache strategy of the solid-state drive is determined, which avoids the problems of long test time, low test efficiency and serious impact on the lifespan of the solid-state drive caused by writing data to the solid-state drive multiple times. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is an example diagram illustrating an application scenario provided in this embodiment.

[0050] Figure 2 This is a block diagram of the electronic device provided in this embodiment.

[0051] Figure 3 This is an example diagram showing the read latency distribution of data inside and outside the cache area provided in this embodiment.

[0052] Figure 4 This embodiment provides a flowchart for determining the release strategy in the cache strategy testing method. Figure 1 .

[0053] Figure 5 This is an example diagram of the read delay distribution for determining the release start time provided in this embodiment.

[0054] Figure 6 This is an example diagram of the read delay distribution for determining the release end time provided in this embodiment.

[0055] Figure 7 This embodiment provides a flowchart for determining the release strategy in the cache strategy testing method. Figure 2 .

[0056] Figure 8 This is a flowchart illustrating the process of determining the cache size in the caching strategy testing method provided in this embodiment.

[0057] Figure 9 This is an example diagram of the read latency distribution for determining the cache size provided in this embodiment.

[0058] Figure 10 This is a flowchart illustrating the process of determining whether the cache size is fixed in the caching strategy testing method provided in this embodiment.

[0059] Figure 11 This is a block diagram of the caching strategy testing device provided in this embodiment.

[0060] Icons: 10-Electronic device; 11-Processor; 12-Memory; 13-Bus; 20-Solid state drive; 100-Cache strategy test device; 110-Write module; 120-Read module; 130-Generate module; 140-Determine module. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0062] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0063] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0064] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0065] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0066] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0067] Due to the erase-then-write storage characteristic of solid-state drives (SSDs), frequent data writes to them during testing have two main drawbacks. First, they consume a significant amount of testing time, reducing efficiency. Second, frequent data writes severely impact the lifespan of the SSD. For example, a 1TB SSD using TLC media typically has a lifespan of around 600TBW (Terabytes Written, meaning the manufacturer guarantees 600TB of data can be written within the warranty period; exceeding this limit voids the warranty). QLC media, on the other hand, has a lifespan of only around 200TBW. Writing several times the SSD's capacity during testing will rapidly deplete its lifespan.

[0068] In addition, the cache size of some solid-state drives is not fixed. For example, the initial cache is set to X GB. When the cache is full after the first write, if new data is written after a period of time, only a small part of the cache may be released or no cache may be released at all. In order to ensure performance, the hard drive controller will re-emulate a portion of TLC blocks into Y GB SLC for use as cache. If the test is conducted in the existing way of writing data multiple times, the wrong conclusion will be drawn that the cache space has been completely released.

[0069] In view of this, this embodiment provides a caching strategy testing method, apparatus, electronic device, and computer-readable storage medium, which can reduce the number of data writes during the testing process to test the caching strategy of the solid-state drive, thereby improving testing efficiency and reducing the impact of testing on the lifespan of the solid-state drive. It will be described in detail below.

[0070] Please refer to Figure 1 , Figure 1 This is an example diagram illustrating an application scenario provided in this embodiment. Figure 1 In this process, electronic device 10 and solid-state drive 20 are connected in communication. Electronic device 10 sends read and write data requests to solid-state drive 20 and records the logical address to be read and the read latency of the read request. By analyzing the logical address to be read and the read latency, the caching strategy of solid-state drive is tested.

[0071] The electronic device 10 can be a physical computer device, a virtual machine that can perform the same functions as a physical computer device, a server, a server group or server cluster composed of multiple servers, etc. This embodiment does not limit the specific form of the electronic device 10.

[0072] The storage media used in the solid-state drive 20 include, but are not limited to, SLC, MLC, TLC, QLC, and PLC.

[0073] It should be noted that, Figure 1 The diagram below only shows the connection relationship between the solid-state drive 20 and the electronic device 10. In fact, the solid-state drive 20 can be located inside the chassis of the electronic device 10 or outside the chassis of the electronic device 10.

[0074] based on Figure 1 In addition to the application scenarios, this embodiment also provides a block diagram example of the electronic device 10. Please refer to it. Figure 2 , Figure 2 This is a block diagram of the electronic device provided in this embodiment. Figure 2 In the electronic device 10, there are a processor 11, a memory 12 and a bus 13, and the processor 11 and the memory 12 are connected through the bus 13.

[0075] Processor 11 can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the cache strategy testing method in this embodiment can be completed by the integrated logic circuitry in the hardware of processor 11 or by software instructions. The processor 11 can be a general-purpose processor, including CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Logic Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0076] The memory 12 is used to store the program that implements the caching strategy test method. The program can be a software function module stored in the memory 12 in the form of software or firmware or embedded in the OS (Operating System) of the electronic device 10.

[0077] After receiving the execution instruction, the processor 11 executes the program to implement the cache strategy testing method of the aforementioned embodiment.

[0078] based on Figure 1 and Figure 2 During testing of solid-state drives (SSDs), the inventors discovered that when data is in the cache, it is stored in SLC blocks. At this time, all pages within the block are of the same type (SLC page), resulting in a lower read latency (tR) compared to data outside the cache, and the I / O latency is essentially the same, meaning the difference in I / O latency is minimal. When data is outside the cache, it is stored in TLC or QLC blocks. Since multiple page types exist within a flash memory block, the read latency varies significantly depending on the page type. Reordering the random read I / O latency according to LBA (Logical Block Addressing) from smallest to largest reveals a latency pattern consistent with the page types of the flash memory. Specifically, the I / O latency exhibits a cycle of high and low latency, with higher latency than that within the cache. Furthermore, to more intuitively verify these findings, the inventors provided a graphical analysis of the logical address and latency for random reads, and the results confirmed these findings.

[0079] Please refer to Figure 3 , Figure 3 This is an example diagram illustrating the read latency distribution of data inside and outside the cache provided in this embodiment. Figure 3 In this scenario, when data is within the cache, random reads result in a latency distribution for the LBA addresses that can be roughly represented as a straight line. However, when data is outside the cache, the latency distribution for the LBA addresses exhibits a stepped, cyclical distribution. Each cycle corresponds to two steps, each of which can be roughly represented as a straight line. Each step within these two steps corresponds to data in the TLC block and the QLC block. Of course, if the SSD includes more media types, the number of steps in each cycle will also increase. Furthermore, when data is within the cache, the read latency corresponding to this straight line is significantly lower than the read latency corresponding to any single step when data is outside the cache.

[0080] Based on the above findings, the inventors provide a method for testing the caching strategy of a solid-state drive by analyzing the read latency distribution map generated by the read operation. The caching strategy includes, but is not limited to, release strategy and cache size.

[0081] Please refer to Figure 4 , Figure 4 This embodiment provides a flowchart for determining the release strategy in the cache strategy testing method. Figure 1 The method includes the following steps:

[0082] Step S101: First, clear the existing data in the solid-state drive and then write new data to the solid-state drive until the writing is complete.

[0083] In this embodiment, clearing the existing data in the solid-state drive (SSD) can be achieved by initializing the SSD or by using the TRIM command supported by the operating system. The TRIM command is a standard command for the SATA (Serial Advanced Technology Attachment) interface, and its full name is "Trim" or "TRIMCommand". The main purpose of the TRIM command is to tell the SSD controller which data blocks are no longer in use and can be safely erased.

[0084] Step S102: In each of the multiple preset time periods, wait for the corresponding preset time period before issuing multiple read requests to randomly read new data each time a read operation is started, and record the logical address and read latency of each read request issued in each read operation.

[0085] In this embodiment, when data is written to the solid-state drive (SSD), the SSD controller first writes the data to the cache. When idle, it moves the data in the cache to the non-cache area. After completion, the cache area is released to restore optimal performance. The SSD's release strategy determines how the data in the cache is released. The release strategy includes, but is not limited to, the release start time, the release rate, and whether the release strategy is fixed.

[0086] In this embodiment, in order to more accurately determine the release status of data, the amount of data written is usually no more than the size of the cache area. This ensures that almost all of the written data is in the cache area before it is released, and the impact on the release status determination is within a controllable range.

[0087] In this embodiment, since solid-state drives (SSDs) from different manufacturers differ, and even different models from the same manufacturer may vary, multiple preset durations can be set according to actual conditions. For example, the preset durations can be set to 10s, 60s, 180s, 600s, etc. After each preset duration, a read operation is initiated, and multiple read requests are sent to randomly read the new data written in step S101. The logical address and read latency of each read request sent in this read operation are recorded.

[0088] In this embodiment, the size of the read request is less than or equal to the size of the flash memory page. For example, if the size of the flash memory page is 16KB, the size of the read request can be selected as 4KB, 8KB, or 16KB. Typically, the size of the read request is set to 4KB.

[0089] Step S103: Generate a read latency distribution map for each read operation based on the logical address and read latency of all read requests issued for each read operation.

[0090] In this embodiment, the x-axis of the read latency distribution map represents the logical address, and the y-axis represents the read latency. The read latency distribution map can be simulated based on the logical address and read latency of each read operation.

[0091] Step S104: Analyze the read latency distribution map of all read operations to determine the current release strategy in the cache strategy.

[0092] In this embodiment, the reason for waiting for a preset time is that releasing data from the solid-state drive is a process that takes time. By performing a read operation after each preset time, a read latency distribution map for each read operation is obtained. By analyzing the read latency distribution map for each read operation, the status of the data in the cache can be determined, such as whether the data has started to be moved out of the cache and whether the data has been completely moved out. The release strategy is then determined based on the data movement status.

[0093] In this embodiment, the current release strategy is determined based on the current test data. The release strategy may be the same or different for different test data.

[0094] The method provided in this embodiment uses a write-once-read-many approach. It utilizes the logical address of the read request and the read latency generated by each read operation to determine the release strategy in the cache strategy of the solid-state drive by analyzing the read latency distribution map. This avoids the problems of long test time, low test efficiency, and serious impact on the lifespan of the solid-state drive caused by writing data to the solid-state drive multiple times.

[0095] In an optional implementation, to facilitate analysis based on the read latency distribution map, this embodiment generates the read latency distribution map in ascending order of logical addresses. Since the generation method of the read latency distribution map is the same for each read operation, this embodiment uses any read operation as an example to illustrate its generation method:

[0096] First, sort the read latency of all read requests in ascending order of their logical addresses to obtain the read latency sequence of the read operation.

[0097] Secondly, using the logical address as the x-axis and the read latency as the y-axis, a read latency distribution map of the read operation is generated based on the read latency sequence of the read operation, and finally the read latency distribution map of each read operation is obtained.

[0098] Since the release waiting time and release rate in the release strategy have a significant impact on the release process, this embodiment provides a method for analyzing the read latency distribution map after obtaining the read latency distribution map for each read operation, in order to determine the release waiting time and release rate of the current release strategy:

[0099] (1) Analyze the read latency distribution of all read operations to determine the release start time, release waiting time and release end time. The release start time is the time when new data begins to be released from the cache to the non-cache. The release waiting time is the time between the completion of writing new data and the release start time. The release end time is the time when all new data is released from the cache to the non-cache.

[0100] In this embodiment, the release can be considered to have begun when data originally in the cache area starts to be moved to the non-cache area, and the release can be considered to have ended when all data in the cache area has been moved to the non-cache area. To determine the release start and end times based on the read latency distribution map, this embodiment provides an implementation method:

[0101] First, compare the target line segments parallel to the x-axis corresponding to the same preset logical address range in the read latency distribution diagram of each two adjacent read operations. If the read latency corresponding to the target line segment in the previous read latency distribution diagram is less than the read latency corresponding to the target line segment in the subsequent read latency distribution diagram, then the start time of the subsequent read operation is taken as the release start time.

[0102] In this embodiment, the preset logical address range can be the address space where the first new data of a preset length is written is located. For example, if the logical address where the new data is written is 0 to 30, then the preset logical address range can be set to 0 to 5.

[0103] Please refer to Figure 5 , Figure 5This is an example diagram of the read delay distribution for determining the release start time provided in this embodiment. Figure 5 In the process, after waiting for a preset time 'a', a read operation is performed at time 't1' to obtain... Figure 5 Read delay distribution in t1 Figure 1 After waiting for a duration of b, another read operation is issued at time t2, yielding... Figure 5 Read delay distribution in t2 Figure 2 , Figure 5 In the middle, read delay distribution Figure 1 The analog lines representing read latency show a straight line distribution, with the latency for data at logical addresses 0-50 being less than the read latency distribution. Figure 2 The latency of data with logical addresses between 0 and 50 indicates the read latency distribution. Figure 1 In the middle, almost all the data is in the cache, and the read latency distribution is... Figure 2 In the data, the latency of data with logical addresses between 0 and 50 is significantly greater than that of data in the read latency distribution. Figure 1 If the latency in the data is less than the preset value, it means that the read latency distribution is... Figure 2 In this context, data with logical addresses between 0 and 50 begins to be released from the cache to the non-cache area. Therefore, t2 is taken as the release start time.

[0104] It should be noted that, Figure 5 This graph is a simulation of read latency distribution based on actual data, used only to illustrate the changes in read latency. It is not like... Figure 3 A graph that is generated directly from actual data.

[0105] Secondly, the release waiting time is determined based on the release start time and the new data write end time;

[0106] Third, determine each reference delay distribution map from the read delay distribution map of all read operations. Each reference delay distribution map contains only multiple line segments that are parallel to the x-axis and are cyclically distributed.

[0107] In fact, since there are multiple preset durations, even after all the data has been moved out of the cache, the data will still be outside the cache after waiting for the preset duration. Therefore, the start time of the read operation corresponding to the earliest read latency distribution map where all the data has been moved out of the cache can be used as the release end time.

[0108] Fourth, determine the release end time based on the reference delay distribution map of the earliest start time read operation.

[0109] In addition, the release end time can also be determined by analyzing the read delay distribution maps of two adjacent maps. Please refer to [link / reference]. Figure 6 , Figure 6 This is an example diagram of the read delay distribution for determining the release end time provided in this embodiment. Figure 6 In the process, after waiting for a preset time c, a read operation is performed at time t3 to obtain... Figure 6 Read delay distribution in t3 Figure 3 After waiting for a preset time d, a read operation is performed at time t4 to obtain... Figure 6 Read delay distribution of t4 Figure 4 Read delay distribution Figure 3 There is also a portion of data in the cache, as indicated by the arrow pointing to "in the cache" in the figure, with read latency distribution... Figure 4 All data is no longer in the cache, that is... Figure 3 The last part of the data in the cache has also been released to the non-cache area, therefore, t4 is taken as the release end time.

[0110] It should be noted that, Figure 6 This graph is a simulation of read latency distribution based on actual data, used only to illustrate the changes in read latency. It is not like... Figure 3 A graph that is generated directly from actual data.

[0111] (2) Calculate the release rate based on the release start time, release end time, and the amount of new data;

[0112] (3) Use the release waiting time and release rate as the current release strategy.

[0113] In this embodiment, the release strategy of some solid-state drives may not be fixed. When the amount of data written is different, the release waiting time and release rate may change. In order to determine whether the release strategy is fixed or not, this embodiment also provides a processing method, please refer to Figure 7 , Figure 7 This embodiment provides a flowchart for determining the release strategy in the cache strategy testing method. Figure 2 The method includes the following steps:

[0114] Step S105: Obtain the reference release policy. Both the reference release policy and the current release policy include the release waiting time and the release rate. When determining the reference release policy, the amount of data written is different from the amount of new data.

[0115] Step S106: If the difference between the release waiting time and release rate of the reference release strategy and the current release strategy is within the set range, then the cache strategy of the solid-state drive is determined to be a fixed release strategy; otherwise, the cache strategy of the solid-state drive is determined to be a non-fixed release strategy.

[0116] In this embodiment, the set range of the release waiting time for the reference release strategy and the current release strategy can be the same as or different from the set range of the release rate, and can be set according to the needs of the actual scenario. The amount of data written by the two strategies is different, but to improve the accuracy of the test, both can be smaller than the cache size.

[0117] It should be noted that step S105 can be executed before step S101, or simultaneously with step S101. That is, the order in which the release strategies of the two are obtained is not limited, as long as both have been obtained before the comparison.

[0118] In this embodiment, the caching strategy includes not only the release strategy but also the cache size. To determine the cache size, this embodiment provides an implementation method based on the analysis of read latency distribution maps. Please refer to [link / reference]. Figure 8 , Figure 8 This is a flowchart illustrating the process of determining the cache size in the caching strategy testing method provided in this embodiment. The method includes the following steps:

[0119] Step S201: Write data sequentially to the solid-state drive.

[0120] In this embodiment, when testing the cache size, the amount of data written can be based on a preset proportion of the total disk capacity. The preset proportion is determined by the type of flash memory medium used by the solid-state drive. For example, for TLC, the preset proportion is 1 / 3; for QLC, the preset proportion is 1 / 4; and for PLC, the preset proportion is 1 / 5.

[0121] In this embodiment, in order to ensure the accuracy of the test, the original data in the solid-state drive can be cleared before writing data in step S201. The clearing method has been described above and will not be repeated here.

[0122] Step S202: When the data writing is complete, multiple read requests are issued to randomly read the written data, and the logical address to be read and the read latency of each read request are recorded.

[0123] Step S203: Generate the current read latency distribution map based on the logical address and read latency of all read requests. The current read latency distribution map uses the logical address as the x-axis and the read latency as the y-axis.

[0124] In this embodiment, the read latency distribution map is generated in a similar way to the aforementioned read latency distribution map, and will not be described again here.

[0125] Step S204: If the current read latency distribution map contains both a first line segment and multiple cyclically distributed second line segments, then the size of the logical space between the starting logical address and the ending logical address corresponding to the first line segment is determined as the cache size. The first line segment and each second line segment are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any second line segment.

[0126] In this embodiment, to ensure the accuracy of the analyzed cache size, a relatively large estimate of the cache size can be made first. The amount of data written should be greater than this estimate to ensure that while the cache is full, some data is also written to the non-cache area. Only then will the obtained cache size be more accurate. In other words, at this time, the read latency distribution graph simultaneously contains the first line segment and the cyclically distributed second line segment. Please refer to... Figure 9 , Figure 9 This is an example diagram of the read latency distribution for determining the cache size provided in this embodiment. Figure 9 In the diagram, the first line segment corresponds to data with logical addresses 0 to M, and the second line segment corresponds to data with logical addresses (M+1) to N. The first line segment is a straight line parallel to the x-axis, and the second line segment includes cyclically distributed second line segments, with each cycle containing two second line segments. The read latency corresponding to the first line segment is less than the read latency of any second line segment. Therefore, it can be concluded that data with logical addresses 0 to M is written to the buffer, and data with logical addresses M+1 to N is written to the non-buffered area. Thus, the size of the buffer determined in this case is (M×512 / 1024 / 1024 / 1024) GB.

[0127] It should be noted that, Figure 9 This graph is a simulation of read latency distribution based on actual data, used only to illustrate the changes in read latency. It is not like... Figure 3 A graph that is generated directly from actual data.

[0128] In this embodiment, the cache size of some solid-state drives is not fixed. To determine whether the cache size is fixed, this embodiment also provides an implementation method based on the analysis of read latency distribution maps. Please refer to [link / reference]. Figure 10 , Figure 10 This is a flowchart illustrating the process of determining whether the cache size is fixed in the caching strategy testing method provided in this embodiment. The method includes the following steps:

[0129] Step S205: Write the same amount of data sequentially to different logical spaces of the solid-state drive twice in succession;

[0130] In this embodiment, to ensure the accuracy of the test results, the logical spaces written in the two tests do not overlap. The amount of data written is slightly larger than the cache size determined in the previous test, so as to ensure that the cache area is filled during the first write.

[0131] Step S206: Send multiple read requests to the logical space to read data randomly, and record the logical address and read latency of each read request sent in the next step.

[0132] Step S207: Determine whether the data to be written in the next step is in the cache based on the logical address and read latency of all read requests issued in the next step.

[0133] In this embodiment, to determine whether the data written later is in the cache, this embodiment provides an implementation method:

[0134] First, based on the logical addresses and read latency of all read requests issued in the next iteration, a read latency distribution map for the next iteration is generated. The read latency distribution map for the next iteration is plotted with logical address as the x-axis and read latency as the y-axis.

[0135] The subsequent read latency distribution map is generated in a similar way to the aforementioned read latency distribution map, so it will not be described again here.

[0136] Secondly, if the subsequent read latency distribution graph contains both the first line segment and multiple cyclically distributed second line segments, and both the first line segment and each second line segment are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any second line segment, then it is determined that the data written in the subsequent transaction is in the cache; otherwise, it is determined that the data written in the subsequent transaction is not in the cache.

[0137] In this embodiment, the size of the logical space between the starting logical address and the ending logical address corresponding to the first line segment can also be determined as the cache size of the cache area for the data written later.

[0138] It should be noted that if it is only necessary to determine whether there is data in the cache in the next write, it can be determined that some data in the cache is already in the next write if only the first line segment exists in the read latency distribution graph of the next write and the read latency of the first line segment is less than the preset threshold. In this case, it can be concluded that the cache size is not fixed.

[0139] In step S208, if the data written in the next step is in the cache, the cache configuration of the caching strategy is determined to be a non-fixed size configuration; otherwise, the cache configuration of the caching strategy is determined to be a fixed size configuration.

[0140] In this embodiment, since the data is written twice consecutively, the cache is already full when the data is written for the first time. If the data is still written to the cache in the second time, the cache size is considered to be variable; otherwise, the cache size is considered to be fixed.

[0141] In each process described above, when reading data via a read request, the area covered by the read request can be the entire area where the data is written. In this case, the caching strategy analysis results are relatively accurate, but the testing time is relatively long. In order to adapt to scenarios with requirements for testing time, and when the loss of accuracy is within a controllable range, we can also adopt reading a portion of the entire area where the data is written to shorten the testing time.

[0142] One approach to reading a portion of the data area is to divide the logical address space of the entire area into X equal parts, and randomly read one area every Y parts. The test time can be adjusted by changing X and / or Y; decreasing X reduces the size of each random read, while increasing Y reduces the number of reads. To ensure comprehensive coverage, several areas can be selected from the beginning, middle, and end of the data area as the reading region.

[0143] To perform the corresponding steps in the above embodiments and various possible implementations, an implementation of the cache strategy testing device 100 is given below. Please refer to... Figure 11 , Figure 11 This is a block diagram of the caching strategy testing device provided in this embodiment. It should be noted that the basic principle and technical effects of the caching strategy testing device 100 provided by the present invention are the same as those of the corresponding embodiments described above. For the sake of brevity, some parts of this embodiment are not mentioned.

[0144] The cache strategy testing device 100 includes a write module 110, a read module 120, a generate module 130, and a determine module 140.

[0145] The write module 110 is used to first clear the existing data in the solid-state drive and then write new data to the solid-state drive until the writing is complete.

[0146] The reading module 120 is used to sequentially wait for the corresponding preset time period before issuing multiple read requests to randomly read the new data each time a read operation is started, according to each preset time period of a plurality of preset time periods, and to record the logical address and read delay of each read request issued in each read operation.

[0147] The generation module 130 is used to generate a read latency distribution map for each read operation based on the logical address and read latency of all read requests issued for each read operation.

[0148] The determination module 140 is used to analyze the read latency distribution map of all read operations and determine the current release strategy in the cache strategy.

[0149] In an optional implementation, the generation module 130 is specifically used for:

[0150] For any read operation, sort the read latency of all read requests in ascending order of their logical addresses to obtain the read latency sequence of the read operation.

[0151] Using logical address as the x-axis and read latency as the y-axis, a read latency distribution map is generated based on the read latency sequence of read operations, ultimately yielding the read latency distribution map for each read operation.

[0152] In an optional implementation, the determining module 140 is specifically used for:

[0153] Analyze the read latency distribution of all read operations to determine the release start time, release wait time, and release end time. The release start time is the time when new data begins to be released from the cache to the non-cache. The release wait time is the time between when the new data is written and the release start time. The release end time is the time when all the new data is released from the cache to the non-cache.

[0154] The release rate is calculated based on the release start time, release end time, and the amount of new data.

[0155] The release waiting time and release rate are used as the current release strategy.

[0156] In an optional implementation, the read latency distribution map for each read operation is plotted with the logical address as the x-axis and the read latency as the y-axis. The determination module 140 is specifically used to analyze the read latency distribution map of all read operations and determine the release start time, release waiting time, and release end time.

[0157] For each two consecutive read operations, the target line segments corresponding to the same preset logical address range in the read latency distribution map are compared one by one. If the read latency corresponding to the target line segment in the previous read latency distribution map is less than the read latency corresponding to the target line segment in the subsequent read latency distribution map, then the start time of the subsequent read operation is taken as the release start time.

[0158] The release waiting time is determined based on the release start time and the new data write end time;

[0159] Each reference delay distribution map is determined from the read delay distribution map of all read operations. Each reference delay distribution map contains only multiple line segments that are parallel to the x-axis and are cyclically distributed.

[0160] The release end time is determined based on the reference latency distribution map of the earliest read operation.

[0161] In an optional implementation, the determining module 140 is further configured to:

[0162] Obtain the reference release strategy. Both the reference release strategy and the current release strategy include the release wait time and the release rate. The amount of data written when determining the reference release strategy is different from the amount of new data.

[0163] If the difference between the release waiting time and release rate of the reference release strategy and the current release strategy is within the set range, the caching strategy of the solid-state drive is determined to be a fixed release strategy; otherwise, the caching strategy of the solid-state drive is determined to be a non-fixed release strategy.

[0164] In an optional implementation, the write module 110 is further configured to: sequentially write data to the solid-state drive;

[0165] The reading module 120 is also used to: when the data writing is complete, issue multiple read requests to randomly read the written data, and record the logical address to be read and the read latency of each read request;

[0166] The generation module 130 is also used to: generate a read latency distribution map for this read request based on the logical address and read latency of all read requests, wherein the read latency distribution map is plotted with the logical address as the x-axis and the read latency as the y-axis;

[0167] The determination module 140 is further configured to: if the current read latency distribution map contains both a first line segment and multiple cyclically distributed second line segments, then determine the size of the logical space between the starting logical address and the ending logical address corresponding to the first line segment as the cache size, wherein the first line segment and each second line segment are parallel to the x-axis and the read latency corresponding to the first line segment is less than the read latency corresponding to any second line segment.

[0168] In an optional implementation, the write module 110 is further configured to: sequentially write the same amount of data to different logical spaces of the solid-state drive twice in succession;

[0169] The reading module 120 is also used to: send multiple read requests to the logical space to be written to in the next write, randomly read the data in it, and record the logical address and read latency of each read request sent in the next write.

[0170] The determination module 140 is also used to: determine whether the data written in the next operation is in the cache based on the logical address and read latency of all the read requests issued in the next operation;

[0171] If the data written later is in the cache, the cache policy is determined to be configured as a non-fixed size cache; otherwise, the cache policy is determined to be configured as a fixed size cache.

[0172] In an optional implementation, the determining module 140, when determining whether the data written in the next transaction is in the cache based on the logical address and read latency of all subsequent read requests, specifically performs the following functions:

[0173] Based on the logical addresses and read latency of all read requests issued in the next iteration, a read latency distribution map for the next iteration is generated. The read latency distribution map for the next iteration is plotted with logical address as the x-axis and read latency as the y-axis.

[0174] If the subsequent read latency distribution graph contains both a first line segment and multiple cyclically distributed second line segments, and both the first line segment and each of the second line segments are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any of the second line segments, then it is determined that the data written in the subsequent transaction is in the cache; otherwise, it is determined that the data written in the subsequent transaction is not in the cache.

[0175] It should be noted that the above is only one implementation of the cache strategy testing device 100. As another implementation of the cache strategy testing device 100, it can also be divided into IO tool software and data processing module, which can also implement the cache strategy testing method provided in this embodiment.

[0176] The IO tool software can accept specific read and write parameters set by testers, initiate IO read and write operations, and has the function of statistics and recording IO latency.

[0177] The IO tool software also allows testers to customize the start and end address ranges, read and write lengths, etc. for read and write operations.

[0178] The IO utility software can perform random and sequential read / write operations within a specific range. When performing random operations, it supports defining different random seeds to generate different random address sequences. When performing sequential read / write operations, the LBA addresses of the operations can be adjacent or spaced out by user-defined LBA addresses.

[0179] IO tools can measure the time interval between IO submission and completion, and record and save the IO operation's latency along with information such as the LBA address and the size of the data block.

[0180] The electronic device 10 also has a data processing module for processing data such as latency / address, including: sorting the latency data according to the LBA address order, and plotting the resulting data as a scatter plot with the LBA address on the horizontal axis and the read latency on the vertical axis.

[0181] When reading a large amount of IO data, the scatter plot will be densely packed. The data processing module can then narrow down the dataset and redraw the plot.

[0182] When reading data, the SSD may be performing garbage collection, inspection, or other operations in the background, which may increase the latency of some I / O operations by several times. When this larger portion of data is plotted together with the normal data, the difference between the normal I / O latency will not be visible due to the increased vertical axis. In this case, the data processing module can limit the range of the vertical axis of the scatter plot to a range slightly larger than the normal latency.

[0183] The smallest unit of the medium read by the controller within a solid-state drive (SSD) varies and may be larger than the size of the I / O data initiated by the I / O tool. When the (N+1)th random LBA address and the flash memory physical space corresponding to the Nth random LBA address are both within the smallest unit of the medium read by the controller, the (N+1)th data will not need to be read from the flash array (NAND array). The SSD controller can directly return the data to the host, thus reducing the I / O latency. The data processing module can then plot a scatter plot based on this data, but this portion of the data can be ignored during analysis.

[0184] In summary, this invention provides a caching strategy testing method, apparatus, electronic device, and computer-readable storage medium, applied to an electronic device and a communication connection between the electronic device and a solid-state drive (SSD). The method includes: first clearing the existing data in the SSD and then writing new data to the SSD until the writing is complete; sequentially waiting for the corresponding preset time period before issuing multiple read requests to randomly read new data at each read operation, and recording the logical address and read latency of each read request issued in each read operation; generating a read latency distribution map for each read operation based on the logical address and read latency of all read requests issued in each read operation; and analyzing the read latency distribution maps of all read operations to determine the current release strategy in the caching strategy. Compared with the prior art, this embodiment has at least the following advantages: (1) The embodiment of the present invention determines the cache release strategy by writing once and reading multiple times, avoiding the impact of testing on the lifespan of the solid-state drive; (2) It avoids the problem of incorrect release strategy judgment caused by multiple writes in the prior art when the cache of the solid-state drive is not fixed; (3) By the release waiting time and release rate, it can determine whether the cache strategy is a fixed release strategy, thereby improving the completeness and accuracy of the release strategy judgment; (4) By writing first and then reading, a more accurate cache size can be obtained based on the read latency distribution map; (5) By writing twice and then reading the data written once, it can be determined whether the cache size is fixed; (6) When reading data, it can read the entire area of ​​the written data to obtain a more accurate cache strategy, or it can read a portion of the area to shorten the test time within the range of accuracy requirements.

[0185] The above descriptions are merely various embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for testing caching strategies, characterized in that, Applied to an electronic device and communicatively connected to a solid-state drive, the method includes: First, clear the existing data in the solid-state drive, then write new data to the solid-state drive until the writing is complete; Each time a read operation is initiated, the system waits for the corresponding preset duration before issuing multiple read requests to randomly read the new data, and records the logical address and read latency of each read request issued in each read operation. Based on the logical addresses and read latency of all read requests issued for each read operation, generate a read latency distribution map for each read operation; Analyze the read latency distribution of all read operations to determine the current release strategy in the cache policy.

2. The caching strategy testing method as described in claim 1, characterized in that, The step of generating a read latency distribution map for each read operation based on the logical addresses and read latency of all read requests issued for each read operation includes: For any read operation, the read latency of all read requests is sorted in ascending order of their logical addresses to obtain the read latency sequence of the read operation. Using the logical address as the x-axis and the read latency as the y-axis, a read latency distribution map of the read operation is generated based on the read latency sequence of the read operation, and finally the read latency distribution map of each read operation is obtained.

3. The caching strategy testing method as described in claim 1, characterized in that, The step of analyzing the read latency distribution of all read operations to determine the current release strategy in the cache policy includes: Analyze the read latency distribution of all read operations to determine the release start time, release wait time, and release end time. The release start time is the time when the new data begins to be released from the cache to the non-cache. The release wait time is the time from when the new data is written to the release start time. The release end time is the time when all the new data is released from the cache to the non-cache. The release rate is calculated based on the release start time, the release end time, and the amount of new data. The release waiting time and the release rate are used as the current release strategy.

4. The caching strategy testing method as described in claim 3, characterized in that, The read latency distribution diagram for each read operation is plotted with the logical address as the x-axis and the read latency as the y-axis. The steps of analyzing the read latency distribution diagrams of all read operations to determine the release start time, release waiting time, and release end time include: For each two consecutive read operations, the target line segments corresponding to the same preset logical address range in the read latency distribution diagram are compared one by one. If the read latency of the target line segment in the previous read latency distribution diagram is less than the read latency of the target line segment in the subsequent read latency distribution diagram, then the start time of the subsequent read operation is taken as the release start time. The release waiting time is determined based on the release start time and the new data write end time. Each reference delay distribution map is determined from the read delay distribution map of all the read operations, and each reference delay distribution map contains only multiple line segments that are parallel to the x-axis and are cyclically distributed; The release end time is determined based on the reference delay distribution map of the earliest read operation.

5. The caching strategy testing method as described in claim 1, characterized in that, After analyzing the read latency distribution of all read operations and determining the current release strategy in the cache policy, the following steps are included: Obtain a reference release strategy. Both the reference release strategy and the current release strategy include a release wait time and a release rate. When determining the reference release strategy, the amount of data written is different from the amount of data in the new data. If the difference between the release waiting time and the release rate of the reference release strategy and the current release strategy are both within the set range, then the caching strategy of the solid-state drive is determined to be a fixed release strategy; otherwise, the caching strategy of the solid-state drive is determined to be a non-fixed release strategy.

6. The caching strategy testing method as described in claim 1, characterized in that, The method further includes: Data is written sequentially to the solid-state drive; When the data writing is complete, multiple read requests are issued to randomly read the written data, and the logical address to be read and the read latency of each read request are recorded. Based on the logical addresses and read latency of all the read requests, a read latency distribution map is generated for this read latency, with the logical address as the x-axis and the read latency as the y-axis. If the current read latency distribution graph contains both a first line segment and multiple cyclically distributed second line segments, then the size of the logical space between the starting logical address and the ending logical address corresponding to the first line segment is determined as the cache size. Here, the first line segment and each of the second line segments are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any of the second line segments.

7. The caching strategy testing method as described in claim 1, characterized in that, The method further includes: The same amount of data is written sequentially to different logical spaces of the solid-state drive twice in succession; Multiple read requests are sent to the logical space to read data randomly, and the logical address and read latency of each read request are recorded. Determine whether the data written in the next instance is in the cache based on the logical address and read latency of all the read requests issued in the next instance; If the data written in the last instance is in the cache, then the cache configuration of the caching strategy is determined to be a non-fixed size configuration; otherwise, the cache configuration of the caching strategy is determined to be a fixed size configuration.

8. The caching strategy testing method as described in claim 7, characterized in that, The step of determining whether the data written in the next transaction is in the cache based on the logical address and read latency of all the read requests issued in the next transaction includes: Based on the logical addresses and read latency of all the read requests issued in the next iteration, a read latency distribution map for the next iteration is generated. The read latency distribution map for the next iteration is plotted with logical address as the x-axis and read latency as the y-axis. If the subsequent read latency distribution graph contains both a first line segment and multiple cyclically distributed second line segments, and both the first line segment and each of the second line segments are parallel to the x-axis, and the read latency corresponding to the first line segment is less than the read latency corresponding to any of the second line segments, then it is determined that the data written in the subsequent transaction is in the cache area; otherwise, it is determined that the data written in the subsequent transaction is not in the cache area.

9. A caching strategy testing device, characterized in that, Applied to an electronic device, wherein the electronic device and a solid-state drive are communicatively connected, the device includes: The write module is used to first clear the existing data in the solid-state drive and then write new data to the solid-state drive until the writing is complete. The reading module is used to sequentially wait for the corresponding preset duration before issuing multiple read requests to randomly read the new data each time a read operation is started, according to each of the preset durations. The module also records the logical address and read latency of each read request issued in each read operation. The generation module is used to generate a read latency distribution map for each read operation based on the logical address and read latency of all read requests issued for each read operation. The determination module is used to analyze the read latency distribution map of all read operations and determine the current release strategy in the cache strategy.

10. An electronic device, characterized in that, It includes a processor and a memory, the memory being used to store a program, and the processor being used to implement the caching strategy testing method as described in any one of claims 1-8 when executing the program.

11. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the caching strategy testing method as described in any one of claims 1-8.

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