Operation method of a super storage device and a memory device included in the super storage device

Abstract

An operation method of a super storage device and a memory device included in the super storage device is provided. The super storage device is configured to communicate with a host device that executes a plurality of applications, and includes an operation management circuit configured to receive a plurality of data from the host device, a memory device including a plurality of memory areas and an application classification circuit configured to control the plurality of data to be distributed to the plurality of memory areas based on a source application of each of the plurality of data, and one or more storage devices including a plurality of storage areas corresponding to the plurality of memory areas, respectively. The memory device is configured to flush a first memory area to a first storage area, the first memory area being one of the plurality of memory areas, the first storage area being one of the plurality of storage areas and corresponding to the first memory area.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0177928, filed with the Korean Intellectual Property Office on December 3, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor super-memory devices. More specifically, this disclosure relates to super-memory devices and methods of operating memory devices included in super-memory devices. Background Technology

[0003] Because various technologies (such as cloud services, video data storage, data analytics, and artificial intelligence model training) require large amounts of data, ultra-storage devices configured to store massive amounts of data are being researched. An ultra-storage device may include one or more storage devices. Each of the one or more storage devices may include one or more storage regions.

[0004] Super storage devices can sequentially store multiple data items originating from multiple applications running on a host device in one or more storage devices according to the order in which the data is received. In this case, the multiple data items can be stored in an unorganized manner across the one or more storage devices. For example, depending on the order in which the data is received, two or more data items originating from a single application running on the host device can be distributed across different storage areas, or multiple data items originating from different applications running on the host device can be stored in a single storage area. In this case, the operating efficiency of the super storage device can be reduced. Summary of the Invention

[0005] One or more example embodiments provide a super storage device and a method of operating a memory device included in the super storage device, wherein a storage area where data will be stored is determined based on the source application of the received data.

[0006] According to one aspect of an example embodiment, a super storage device configured to communicate with a host device executing multiple applications includes: an operation management circuit configured to receive multiple data from the host device; a memory device including multiple memory regions and an application classification circuit configured to control the distribution of the multiple data to the multiple memory regions based on the source application of each of the multiple data; and one or more storage devices including multiple memory regions respectively corresponding to the multiple memory regions. The memory device is configured to flush a first memory region to a first memory region, the first memory region being one of the multiple memory regions and corresponding to a first memory region.

[0007] According to another aspect of an example embodiment, a method of operating a memory device includes: receiving first data; identifying a source application of the first data, wherein the source application is identified from a plurality of source applications; storing the first data in a first memory region determined based on the source application among a plurality of memory regions, wherein the plurality of source applications correspond to the plurality of memory regions respectively; and writing the first memory region to an external storage device.

[0008] According to another aspect of the example embodiment, a super storage device configured to store first data and second data provided from an external host device includes: a storage device including a first storage region and a second storage region; and a memory device including a first memory region corresponding to the first storage region and a second memory region corresponding to the second storage region, wherein the memory device is configured to: cache the first data in the first memory region based on the recognition that the first data is issued from a first application of the external host device; and cache the second data in the second memory region based on the recognition that the second data is issued from a second application of the external host device. Attached Figure Description

[0009] The above and other aspects and features will become clearer from the following description of exemplary embodiments with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0011] Figure 2 This is an exemplary diagram illustrating the structure of a storage request according to an example embodiment.

[0012] Figure 3 This is an illustrative diagram showing the structure of data according to an example embodiment.

[0013] Figure 4 This is a block diagram illustrating a super storage device according to an example embodiment.

[0014] Figure 5 This is a block diagram illustrating the configuration of a CXL memory device according to an example embodiment.

[0015] Figure 6 This is a diagram illustrating the operation of the application classification circuit according to an example embodiment.

[0016] Figure 7 This is a block diagram illustrating a method for flushing a memory region according to an example embodiment.

[0017] Figure 8 This is a diagram illustrating a first storage area according to an example embodiment.

[0018] Figure 9 This is a flowchart illustrating an operation method of a CXL memory device according to an example embodiment.

[0019] Figure 10 This is a diagram illustrating the operation of a memory region management circuit according to an example embodiment.

[0020] Figure 11 This is a block diagram illustrating the configuration of a super storage device according to an example embodiment. Detailed Implementation

[0021] In the following description, various embodiments will be presented in detail and clearly to the extent that those skilled in the art can readily implement this disclosure. Specific details, such as detailed components and structures, are provided to aid in the overall understanding of the exemplary embodiments. Therefore, it will be apparent to those skilled in the art that various changes and modifications may be made to the exemplary embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of functions and structures may be omitted.

[0022] The terms described below are defined in consideration of the functions of this disclosure and are not limited to any particular function. The definitions of terms should be determined based on the content throughout the specification. Components described in the detailed description using terms such as "driver," "block," etc., can be implemented in software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

[0023] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment. The storage system SS may include a host device 10 and a super storage device 100.

[0024] The host device 10 can execute multiple applications (APPs). For example, the host device 10 can execute a first application (APP1) to an nth application (APPn). Each of the first application (APP1) to the nth application (APPn) can be one of various types of applications (such as operating systems, user applications, firmware, virtual machines, etc.). However, the example embodiment is not limited to the specific type of each of the first application (APP1) to the nth application (APPn).

[0025] In one example embodiment, host device 10 may include one or more of various processors, such as central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), data processing unit (DPU), etc.

[0026] In one example embodiment, the super storage device 100 may be a petabyte-level solid-state drive (PBSSD). For example, the super storage device 100 may be configured to store more than one petabyte of data. However, the example embodiment is not limited thereto.

[0027] Host device 10 can access super storage device 100. For example, host device 10 can store data in super storage device 100 or read data stored in super storage device 100. For example, host device 10 can issue a storage request REQ_STRG to store data DT issued from one of the first applications APP1 to the nth application APPn in super storage device 100. Hereinafter, example embodiments of host device 10 storing data in super storage device 100 will be described in detail.

[0028] The super storage device 100 may include operation management circuitry 110, compute fast link (CXL) memory device 120, and CXL memory device 130 (e.g., one or more CXL memory devices). The operation management circuitry 110, CXL memory device 120, and CXL memory device 130 may communicate with each other via a CXL interface. (Refer to the following...) Figure 4 The communication method of the operation management circuit 110, CXL memory device 120 and CXL memory device 130 is described in more detail.

[0029] Operation management circuit 110 can control the overall operation of super storage device 100. For example, operation management circuit 110 can control CXL memory device 120 and CXL storage device 130 based on a request provided by host device 10. For example, operation management circuit 110 can control CXL memory device 120 to store data DT in CXL storage device 130 in response to storage request REQ_STRG.

[0030] CXL memory device 120 can cache data DT. For example, CXL memory device 120 can temporarily store data DT provided by host device 10. CXL memory device 120 can flush the temporarily stored data DT to CXL memory device 130. In this way, CXL memory device 130 can store data DT provided by host device 10.

[0031] In one example embodiment, the CXL memory device 120 can identify the source application (i.e., "APP_source") of the data DT. For example, the CXL memory device 120 can identify which application (APP) within the host device 10 has issued the data DT. The CXL memory device 120 can write the data DT to a storage area within the CXL storage device 130 determined according to the source application (APP_source) of the data DT. Therefore, according to the example embodiment, the storage area within the CXL storage device 130 storing the data DT can be changed based on which application (APP) has issued the data DT. In this respect, the CXL memory device 120 can distribute multiple data DTs provided from the host device 10 to different storage areas based on which source application (APP_source) provided the data DT. In this case, because the data DT can be stored in an organized manner within the super storage device 100, the operating efficiency of the super storage device 100 can be improved.

[0032] In one example embodiment, CXL memory device 120 may be a volatile memory device (such as a dynamic random access memory (DRAM) device), and CXL memory device 130 may be a non-volatile memory device (such as a solid-state drive (SSD)).

[0033] Figure 2 This is an example shown Figure 1 A diagram illustrating the structure of the storage request. (Refer to...) Figure 1 and Figure 2 The storage request REQ_STRG may include the opcode OPC, the header logical address LA_head, and the number of logical blocks NUM_LB.

[0034] The opcode OPC indicates that the request provided to the super storage device 100 is a storage request REQ_STRG. The header logical address LA_head indicates the logical address (more specifically, the starting value of the logical address range) of the data DT sent with the storage request REQ_STRG within the host device 10. The number of logical blocks NUM_LB indicates how many logical blocks within the host device 10 correspond to the data DT sent with the storage request REQ_STRG. That is, the number of logical blocks NUM_LB represents the capacity of the data DT sent with the storage request REQ_STRG. Here, the capacity of the data DT can represent the storage capacity occupied by the data DT.

[0035] In one example embodiment, the storage request REQ_STRG may also include a data pointer indicating the location of the storage data DT within the host device 10. However, the example embodiment is not limited thereto.

[0036] Figure 3 This is an example shown Figure 1 A diagram illustrating the structure of the data. (Refer to...) Figures 1 to 3 The data DT can include a main data area RG_main and an auxiliary data area RG_aux. The main data area RG_main can include a bit stream. The bit stream included in the main data area RG_main can be referred to as the main data DT_main.

[0037] The auxiliary data region RG_aux may include a bitstream. A bitstream included in the auxiliary data region RG_aux may be referred to as auxiliary data DT_aux. Auxiliary data DT_aux may include extensions (EXT) of data DT (e.g., file extensions). However, the example embodiment is not limited thereto, and auxiliary data DT_aux may include various types of metadata, such as an identifier or application identifier or source application identifier indicating the source application corresponding to data DT (or an identifier or group identifier indicating the group of applications including the source application) of the data DT.

[0038] In one example embodiment, the data DT may not include the auxiliary data area RG_aux. For example, depending on the type of application issuing the data DT, the data DT may only include the main data area RG_main.

[0039] In one example embodiment, the storage request REQ_STRG and data DT may not include information about the source application APP_source of the data DT (e.g., a source application identifier). For example, the storage request REQ_STRG and data DT may not include information indicating which application APP has issued the data DT. In this case, because the host device 10 does not need to manage information about the applications that have issued the data DT, the operational load of the host device 10 can be reduced. However, the example embodiment is not limited to this, and the storage request REQ_STRG or data DT may include a source application identifier.

[0040] In one example embodiment, the storage request REQ_STRG and the data DT may not include an identifier defining the category of the data DT. For example, the storage request REQ_STRG and the data DT may not include information such as a namespace identifier, a stream identifier, etc. In this case, the operational load of the host device 10 may be reduced because the host device 10 may not need to manage namespaces and streams. However, the example embodiment is not limited to this, and the storage request REQ_STRG or the data DT may include a namespace identifier or a stream identifier.

[0041] Figure 4 To show in more detail Figure 1 A block diagram of the super memory device. (Refer to...) Figures 1 to 4The super storage device 100 may include an operation management circuit 110, a CXL memory device 120, and a CXL storage device 130. The operation management circuit 110, the CXL memory device 120, and the CXL storage device 130 can communicate with each other via a CXL switch SW_CXL. For example, the CXL switch SW_CXL can connect the operation management circuit 110, the CXL memory device 120, and the CXL storage device 130.

[0042] In one example embodiment, the CXL switch SW_CXL can support communication between the operation management circuit 110, the CXL memory device 120, and the CXL storage device 130 based on the CXL interface.

[0043] In one example embodiment, the CXL interface may represent a dynamic protocol multiplexing (or multiplexing) that supports conformance protocols, memory access protocols, and input / output (IO) protocols to enable low-latency, high-bandwidth links between different connections between accelerators, memory devices, or various electronic devices.

[0044] In one example embodiment, CXL memory device 120 and CXL storage device 130 may be connected to CXL switch SW_CXL based on the same form factor. For example, each of CXL memory device 120 and CXL storage device 130 may be connected to a PCIe slot implemented on CXL switch SW_CXL.

[0045] The operation management circuit 110 can support communication between the super storage device 100 and the host device 10. That is, the super storage device 100 can communicate with the host device 10 through the operation management circuit 110. For example, the operation management circuit 110 can receive storage request REQ_STRG and data DT from the host device 10.

[0046] In one example embodiment, the operation management circuitry 110 may communicate with the host device 10 based on at least one of various host interfaces, such as a compute fast link (CXL) interface, a peripheral component interconnect fast (PCIe) interface, a non-volatile memory fast (NVMe) interface, etc.

[0047] Operation management circuit 110 can control the overall operation of super storage device 100. For example, based on storage request REQ_STRG, operation management circuit 110 can control CXL memory device 120 and CXL storage device 130 via CXL switch SW_CXL.

[0048] For the sake of brevity, Figure 4The operation management circuit 110 is shown as a component separate from the CXL switch SW_CXL, but the example embodiment is not limited thereto. For example, the operation management circuit 110 may be included in the CXL switch SW_CXL. That is, the example embodiment is not limited to a specific implementation of the operation management circuit 110 and the CXL switch SW_CXL.

[0049] The operation management circuit 110 can generate attribute information ATI based on the storage request REQ_STRG received along with the data DT. The attribute information ATI may include the header logical address LA_head corresponding to the data DT and the capacity information of the data DT.

[0050] The operation management circuit 110 can respond to the storage request REQ_STRG by providing the data DT and the attribute information ATI corresponding to the data DT to the CXL memory device 120 (① Sending DT and ATI).

[0051] CXL memory device 120 can receive data DT and attribute information ATI corresponding to the data DT. CXL memory device 120 may include application classification circuit ACC. Application classification circuit ACC can identify (e.g., infer) the source application APP_source of data DT based on data DT and the attribute information ATI corresponding to data DT. Application classification circuit ACC can classify data DT based on the source application APP_source (② classifying DT). That is, application classification circuit ACC can classify data DT based on which of multiple applications APP has sent data DT.

[0052] CXL memory device 120 may include multiple memory regions MA. CXL memory device 120 may determine the memory region MA for temporarily storing (e.g., caching) data DT based on the source application APP_source. That is, CXL memory device 120 may determine different memory regions MA for temporarily storing data DT based on which application has issued the data DT. In other words, CXL memory device 120 may temporarily store data DT issued from different applications APP in different memory regions MA. According to an example embodiment, multiple data DTs corresponding to one application APP may be jointly cached in the memory region MA.

[0053] In one example embodiment, the application classification circuit ACC can identify the source application APP_source of the data DT based on its content. For example, the application classification circuit ACC can infer the source application APP_source of the data DT by analyzing the bitstream of the main data region RG_main of the data DT.

[0054] In one example embodiment, the data DT may include an auxiliary data region RG_aux. In this case, the application classification circuit ACC can identify the source application APP_source of the data DT based on the auxiliary data region RG_aux. For example, the application classification circuit ACC can infer the source application APP_source of the data DT based on the extended EXT included in the auxiliary data region RG_aux.

[0055] In one example embodiment, the application classification circuit ACC can identify the source application APP_source of the data DT based on the attribute information ATI. For example, the application classification circuit ACC can infer the source application APP_source of the data DT based on the capacity information of the data DT and the header logical address LA_head of the data DT.

[0056] In one example embodiment, the application classification circuit ACC can identify the source application APP_source of data DT based on other data provided prior to data DT. For example, the application classification circuit ACC can infer the source application APP_source of data DT based on various information (e.g., attribute information, master data, extensions, etc.) of other data provided to CXL memory device 120 prior to data DT. Reference will be made below. Figure 6 The application classification circuit ACC is described in more detail based on the application of APP_source, which is provided before the data DT.

[0057] In one example embodiment, the application classification circuit ACC can also be configured to infer the source application APP_source of the data DT based on two or more of the methods described above. For example, the application classification circuit ACC can infer the source application APP_source of the data DT based on one or a combination of two or more of the following: i) the bit stream of the main data area RG_main of the data DT; ii) the bit stream of the auxiliary data area RG_aux of the data DT; iii) the extended EXT of the data DT; iv) the capacity information of the data DT; v) the header logical address LA_head of the data DT; and vi) information about other data provided to the CXL memory device 120 before the data DT. That is, the example embodiment is not limited to the specific method by which the application classification circuit ACC infers the source application APP_source of the data DT.

[0058] In one example embodiment, neither the storage request REQ_STRG nor the data DT may include an identifier indicating the source application APP_source (or an identifier indicating the application group that includes the source application APP_source). For example, the application identifier may not be provided in the storage request REQ_STRG or in the data DT. That is, even if the storage request REQ_STRG and the data DT do not include an identifier indicating the source application APP_source, the application classification circuit ACC can infer the source application APP_source of the data DT. In this case, the operational load of the host device 10 can be reduced because the host device 10 may not need to manage information about the application that has issued the data DT. However, the example embodiment is not limited to this. For example, the storage request REQ_STRG or the data DT may include an application identifier indicating the source application APP_source. In this case, the application classification circuit ACC may be able to classify the data DT based on the application identifier (or infer the source application APP_source of the data DT based on the application identifier).

[0059] In one example embodiment, the identifier defining the category of the data DT may not be included in the storage request REQ_STRG or the data DT. For example, neither the storage request REQ_STRG nor the data DT may include a namespace identifier or a stream identifier. That is, even if the storage request REQ_STRG and the data DT do not include a namespace identifier and the storage request REQ_STRG and the data DT do not include a stream identifier, the application classification circuit ACC can still infer the source application APP_source of the data DT. In this case, because the host device 10 does not need to manage the namespaces and streams of the super storage device, the operational load of the host device 10 can be reduced. However, the example embodiment is not limited to this. For example, the storage request REQ_STRG or the data DT may include one or more of a namespace identifier and a stream identifier. In this case, the application classification circuit ACC may be able to infer the source application APP_source of the data DT based on one or more of the namespace identifier and the stream identifier.

[0060] CXL memory device 120 can flush a specific memory region MA to CXL memory device 130 (③Flush MA). That is, CXL memory device 120 can batch store multiple data DTs stored in a specific memory region MA to CXL memory device 130. In this way, CXL memory device 120 can cache data DTs provided from host device 10 and then store the data DTs provided from host device 10 in CXL memory device 130. Therefore, according to the example embodiment, multiple data corresponding to an application can be stored together (e.g., simultaneously) in CXL memory device 130.

[0061] In one example embodiment, CXL memory device 120 can write a specific memory region MA to CXL memory device 130 in a peer-to-peer (P2P) manner. For example, CXL memory device 120 can directly provide multiple data DTs stored in a specific memory region MA to CXL memory device 130 via CXL switch SW_CXL. In this respect, CXL memory device 120 can directly provide data to CXL memory device 130 without going through operation management circuitry 110.

[0062] In one example embodiment, when a specific memory region MA is full, the CXL memory device 120 may flush the specific memory region MA to the CXL memory device 130. However, the example embodiment is not limited thereto, and the CXL memory device 120 may also be configured to flush the specific memory region MA to the CXL memory device 130 in response to control by the operation management circuitry 110.

[0063] In one example embodiment, a memory region MA may be described as being full when the ratio of the total capacity of one or more data stored in a particular memory region MA to the capacity of the particular memory region MA is greater than a predetermined ratio (e.g., 90%). However, the example embodiment is not limited thereto.

[0064] Figure 5 To show in more detail Figure 4 A block diagram illustrating the configuration of the CXL memory device. (Refer to...) Figures 1 to 5 The CXL memory device 120 may include a CXL memory controller 121 and first memory regions MA1 to nth memory regions MAn.

[0065] Each of the first memory region MA1 to the nth memory region MAn can correspond to a different application. For example, the first memory region MA1 to the nth memory region MAn can correspond to the first application APP1 to the nth application APPn, respectively.

[0066] CXL memory controller 121 can control the overall operation of CXL memory device 120. For example, CXL memory controller 121 can sequentially receive multiple data DTs from operation management circuit 110 via CXL switch SW_CXL, and can send multiple data DTs to CXL memory device 130 via CXL switch SW_CXL.

[0067] The CXL memory controller 121 may include application classification circuitry ACC and memory region management circuitry MAMC.

[0068] The application classification circuit ACC can infer the source application APP_source of the data DT provided to the CXL memory controller 121. Based on the inferred source application APP_source, the application classification circuit ACC can store the data DT in one of the first memory region MA1 to the nth memory region MAn. For example, the application classification circuit ACC can temporarily store the data DT in the memory region MA corresponding to the source application APP_source.

[0069] For example, the application classification circuit ACC can infer that the first application APP1 is the source application APP_source of the first data DTa. In this case, the application classification circuit ACC can store the first data DTa in the first memory region MA1. As another example, the application classification circuit ACC can infer that the second application APP2 is the source application APP_source of the second data DTb. In this case, the application classification circuit ACC can store the second data DTb in the second memory region MA2. In this way, the application classification circuit ACC can distribute (e.g., store) multiple data DTs provided to the CXL memory controller 121 into the first memory region MA1 to the nth memory region MAn.

[0070] In one example embodiment, the plurality of data DTs stored in the first memory region MA1 to the nth memory region MAn can be referred to as first application data DT_APP1 to nth application data DT_APPn, respectively. For example, each of the data DTs stored in the first memory region MA1 can be referred to as first application data DT_APP1.

[0071] The memory region management circuit MAMC can manage the size of each of the first memory region MA1 to the nth memory region MAn. For example, the memory region management circuit MAMC can increase or decrease the size of each of the first memory region MA1 to the nth memory region MAn in response to the control of the operation management circuit 110.

[0072] In one example embodiment, the operation management circuit 110 may receive the required Quality of Service (QoS) level for each of the first application APP1 to the nth application APPn from the host device 10. In this case, the operation management circuit 110 may control the memory region management circuit MAMC to increase or decrease the size of each of the first memory region MA1 to the nth memory region MAn based on the required QoS level for each of the first application APP1 to the nth application APPn.

[0073] In one example embodiment, the memory region management circuit MAMC can increase or decrease the size of each of the first memory region MA1 to the nth memory region MAn based on a write amplification factor provided from the CXL memory device 130. (Refer to below...) Figure 10 A more detailed example embodiment of the memory region management circuit MAMC adjusts the size of each of the first memory region MA1 to the nth memory region MAn based on the write amplification factor.

[0074] In one example embodiment, as the capacity of a specific memory region MA increases, the CXL memory device 120 can cache a relatively large amount of data DT in the memory region MA. In this case, because a relatively large amount of data DT can be stored together in the CXL memory device 130, multiple data DTs can be stored in the CXL memory device 130 in a more appropriately organized manner. Therefore, the operating efficiency of the CXL memory device 130 can be improved. For example, since multiple data DTs are stored in the CXL memory device 130 in a more appropriately organized manner, data fragmentation of the CXL memory device 130 can be reduced and garbage collection efficiency can be improved. In this case, the write amplification factor of the CXL memory device 130 can be reduced, thus improving the operating efficiency and lifespan of the CXL memory device 130.

[0075] In one example embodiment, the host device 10 can access the data DT before the CXL memory controller 121 writes the data DT provided by the host device 10 to the CXL storage device 130. In this case, the CXL memory controller 121 may, in response to the control of the operation management circuitry 110, provide the data DT read from one of the first memory regions MA1 to the nth memory region MAn to the host device 10. In this respect, when the data DT is stored in the CXL memory device 120, the CXL memory device 120 may provide the data DT to the host device 10 without accessing the CXL storage device 130. In this case, the operating speed of the super storage device 100 can be improved. The larger the specific memory region MA, the more data DT can be stored in the memory region MA, and the operating performance of the super storage device 100 perceived by the application APP corresponding to the memory region MA can be improved. However, the example embodiment is not limited to this.

[0076] Figure 6 This illustrates an example embodiment. Figure 4 A diagram illustrating the operation of the application classification circuit. (Refer to...) Figures 1 to 6The application classification circuit ACC can receive first data DT1 to fifth data DT5 and the corresponding attribute information ATI from the first time point t1 to the fifth time point t5. For example, the attribute information ATI may include a header logical address LA_head and capacity information CAP. The header logical address LA_head may include first logical addresses LA1 to fifth logical addresses LA5, and the capacity information CAP may include first capacity information CAP1 to fifth capacity information CAP5. The application classification circuit ACC can receive the first logical address LA1 to fifth logical address LA5 from the first time point t1 to the fifth time point t5; and can also receive the first capacity information CAP1 to fifth capacity information CAP5 from the first time point t1 to the fifth time point t5.

[0077] The application classification circuit ACC can infer the source application APP_source corresponding to a specific data DT based on other data DTs and attribute information ATI received during the identification period IDP corresponding to the time point when the specific data DT is received. In the following, for a more concise explanation, an exemplary scheme in which the application classification circuit ACC infers the source application APP_source corresponding to the fourth data DT4 will be described.

[0078] The application classification circuit ACC can determine the identification period IDP corresponding to the fourth time point t4 when the fourth data DT4 is received. For example, the application classification circuit ACC can determine the identification period IDP as the time interval between the fourth time point t4 and the time point before the fourth time point t4, which is a predetermined time length. The application classification circuit ACC can infer the source application APP_source corresponding to the fourth data DT4 based on the second data DT2 to the fourth data DT4, the second logical address LA2 to the fourth logical address LA4, and the second capacity information CAP2 to the fourth capacity information CAP4 received during the identification period IDP. That is, the application classification circuit ACC can infer the source application APP_source corresponding to the fourth data DT4 based on one or more of the various information of each of the second data DT2 to the fourth data DT4 (such as the bit stream of the main data area RG_main, the bit stream of the auxiliary data area RG_aux, the extended EXT, the capacity information CAP, and the header logical address LA_head). However, the example embodiment is not limited to this. For example, the application classification circuit ACC can infer the source application APP_source corresponding to the fourth data DT4 based only on the fourth data DT4 and the attribute information ATI corresponding to the fourth data DT4.

[0079] Figure 7 This shows the brushing process in more detail. Figure 4 A block diagram of the method for accessing the memory region. (Refer to...) Figures 1 to 7The CXL memory device 120 may include a first memory region MA1 to an nth memory region MAn. The first memory region MA1 to the nth memory region MAn may respectively store first application data DT_APP1 to nth application data DT_APPn.

[0080] CXL storage device 130 may include first storage regions SA1 to nth storage regions SAn. Each of the first storage regions SA1 to nth storage regions SAn may correspond to a different memory region MA. For example, the first storage regions SA1 to nth storage regions SAn may correspond to the first memory regions MA1 to nth memory regions MAn, respectively.

[0081] Each of the first storage areas SA1 to the nth storage area SAn can be configured to store multiple data DTs written from the corresponding memory area MA. For example, the first storage areas SA1 to the nth storage area SAn can each be storage spaces allocated for the first application data DT_APP1 to the nth application data DT_APPn. That is, the first storage areas SA1 to the nth storage area SAn can respectively store data sent from the first application APP1 to the nth application APPn.

[0082] CXL memory device 120 can determine to write a specific memory region MA. For example, when the first memory region MA1 is full, CXL memory device 120 can determine to write the first memory region MA1. Optionally, CXL memory device 120 can determine to write the first memory region MA1 in response to control of operation management circuitry 110. Hereinafter, exemplary embodiments of CXL memory device 120 writing the first memory region MA1 will be described representatively. However, the exemplary embodiments are not limited thereto.

[0083] CXL memory device 120 can write the first memory region MA1 to the first memory region SA1. For example, CXL memory device 120 can access CXL memory device 130 in a P2P manner to store one or more first application data DT_APP1 stored in the first memory region MA1 to the first memory region SA1.

[0084] In one example embodiment, CXL memory device 120 may provide a storage region identifier indicating a first storage region SA1 along with one or more first application data DT_APP1 to CXL memory device 130. In this case, CXL memory device 130 may store one or more first application data DT_APP1 in the first storage region SA1 based on the storage region identifier indicating the first storage region SA1. In this way, CXL memory device 120 may store data in a specific storage region SA of CXL memory device 130.

[0085] In one example embodiment, CXL memory device 120 may provide one or more first application data DT_APP1 together with the corresponding logical address of each of the one or more first application data DT_APP1 to CXL memory device 130.

[0086] Figure 8 To show in more detail Figure 7 A diagram of the first storage region. In the following text, for a more concise explanation, reference will be made to... Figures 1 to 8 The configuration of the first storage region SA1 is described representatively. However, the example embodiment is not limited to this, and the second storage region SA2 to the nth storage region SAn can also be implemented in a similar manner.

[0087] The first storage area SA1 may include one or more superblocks SB. For example, the first storage area SA1 may include a first superblock SB1 and a second superblock SB2.

[0088] Each of one or more superblocks SB may include multiple memory blocks MB. For example, the first superblock SB1 may include memory blocks MB11 to MB14, and the second superblock SB2 may include memory blocks MB21 to MB24.

[0089] CXL storage device 130 can perform garbage collection operations on a superblock SB basis. For example, CXL storage device 130 can perform garbage collection operations on the first superblock SB1 by reading valid data DT stored in a plurality of memory blocks MB included in the first superblock SB1, erasing all memory blocks MB included in the first superblock SB1, and then re-storing the read valid data DT in any superblock SB (e.g., one or more memory blocks MB in another superblock SB included in the first storage area SA1 or others).

[0090] The CXL memory device 120 can simultaneously write first data DTa to ninth data DTi to the first memory region SA1. For example, when first data DTa to ninth data DTi are stored in the first memory region MA1, the CXL memory device 120 can simultaneously write all of the first data DTa to ninth data DTi to the first memory region SA1.

[0091] Each of the multiple memory blocks MB included in the first storage region SA1 can be implemented to store data DT. For example, memory block MB11 can store first data DTa to fourth data DTd; memory block MB12 can store fifth data DTe to sixth data DTf; memory block MB13 can store seventh data DTg; and memory block MB14 can store eighth data DTh. Similarly, memory block MB21 can store ninth data DTi. In this case, all of the first data DTa to the ninth data DTi can be the first application data DT_APP1.

[0092] In one example embodiment, the capacity of each of the first data DTa and the second data DTb may be less than a page PG. If the first data DTa and the second data DTb are stored in the CXL storage device 130 at different times, the CXL storage device 130 may store the first data DTa and the second data DTb in different pages. In this case, because data DT with a capacity less than that of a page PG is stored in a page PG, data fragmentation of the CXL storage device 130 (and further, data fragmentation of the super storage device 100) may increase. In contrast, according to the example embodiment, the CXL memory device 120 may simultaneously write the first data DTa and the second data DTb to the first storage region SA1. In this case, because the first data DTa and the second data DTb can be stored in a page PG, data fragmentation and write amplification of the CXL storage device 130 (and further, data fragmentation and write amplification of the super storage device 100) may be minimized.

[0093] According to the example embodiment, multiple data DTs stored in a single superblock SB may correspond to the same application. For example, all of the data from the first data DTa to the eighth data DTh may be data issued by the first application APP1. In this case, even if the first application APP1 issues a deletion request (e.g., a pruning request) for some data DTs (e.g., two or more data), the probability (or the extent to which such data is distributed across multiple superblocks SB) of such data DTs can be minimized. For example, the first application APP1 may issue a deletion request for the first data DTa to the sixth data DTf. In this case, unlike the case where the first data DTa to the sixth data DTf are stored in different superblocks because they are stored in the CXL storage device 130 at different times, according to the example embodiment, the CXL storage device 130 may be able to erase the first data DTa to the sixth data DTf simply by performing a garbage collection operation on the first superblock SB1. Therefore, according to the example embodiment, the CXL storage device 130 can perform garbage collection operations more efficiently, thereby minimizing the write amplification of the CXL storage device 130.

[0094] Figure 9 This is a flowchart illustrating an operation method of a CXL memory device according to an example embodiment. (Refer to...) Figures 1 to 9 During operation S110, the CXL memory device 120 can receive data DT and attribute information ATI.

[0095] In operation S120, the CXL memory device 120 can identify the source application APP_source of the data DT. For example, the application classification circuit ACC can infer the source application APP_source of the data DT by analyzing the attribute information ATI and the data DT. However, the example embodiment is not limited to this, and the application classification circuit ACC can also use other data and attribute information received before the above-described operation S110, as referenced above. Figure 6 The description method infers the source application APP_source of the data DT.

[0096] During operation S130, the CXL memory device 120 can store data DT in a memory region MA determined based on the source application APP_source. For example, if the first application APP1 is identified as the source application APP_source of data DT, the application classification circuit ACC can store data DT in the first memory region MA1 corresponding to the first application APP1.

[0097] In operation S140, the CXL memory device 120 can determine whether a write operation is required. For example, the CXL memory device 120 can determine whether the memory region MA in which data DT was newly stored in operation S130 is full. If it is determined in operation S140 that a write operation is required (i.e., the memory region MA is full) Figure 9 If the "Yes" is selected in operation S140, then operation S150 can be performed. If it is determined in operation S140 that no flushing is required (i.e., the memory region MA is not full), then... Figure 9 If the answer is "No", then operation S110 can be performed again or repeatedly. In this way, the CXL memory device 120 can sequentially receive multiple data DTs sent from the host device 10, and store the multiple data DTs in multiple memory regions MA in a distributed manner based on the source application APP_source of each of the multiple data DTs.

[0098] In operation S150, the CXL memory device 120 may flush memory region MA to the memory region SA corresponding to memory region MA. For example, if it is determined that the first memory region MA1 needs to be flushed, the CXL memory device 120 may flush one or more first application data DP_APP1 stored in the first memory region MA1 to the first memory region SA1. Therefore, according to the example embodiment, only the first application data DP_APP1 can be stored in the first memory region SA1.

[0099] Figure 10 This illustrates an example embodiment. Figure 5 A diagram illustrating the operation of the memory region management circuitry. (Refer to...) Figures 1 to 10 CXL memory device 120 may include memory region management circuitry MAMC, and CXL memory device 130 may include write amplification factor management circuitry WMC.

[0100] The write amplification factor management circuit (WMC) can measure the write amplification factor (WAF) of each of the plurality of storage regions (SA) included in the CXL storage device 130. For example, the write amplification factor management circuit (WMC) can calculate the write amplification factor (WAF) of the first storage region (SA1) as a value obtained by dividing the total capacity of the data for which it has received write requests to the first storage region (SA1) (e.g., the amount of logical data requested to be written by the host device) by the total capacity of the data for which it has performed write operations to the first storage region (SA1) (e.g., the amount of physical data actually written).

[0101] The write amplification factor management circuit (WMC) can provide the write amplification factor (WAF) of each of the multiple memory regions (SA) to the CXL memory device 120. However, the example embodiment is not limited to this, and the write amplification factor management circuit (WMC) can also be configured to calculate a write amplification factor (WAF) of the CXL memory device 130. In this case, the write amplification factor management circuit (WMC) can provide a write amplification factor (WAF) of the CXL memory device 130 to the CXL memory device 120.

[0102] The Memory Region Management Circuit (MAMC) can adjust the capacity of multiple memory regions (MA) based on the write amplification factor (WAF) of each of the multiple memory regions (SA).

[0103] For example, if the write amplification factor (WAF) of the first memory region SA1 is too high (e.g., above a predetermined first threshold), the memory region management circuit (MAMC) can increase the capacity of the first memory region MA1. For instance, the MAMC can increase the proportion of the first memory region MA1 in the CXL memory device 120 from 15% to 20%. In this case, as the capacity of the first memory region MA1 increases, the capacity of the data collectively stored in the first memory region SA1 can increase, and therefore the write amplification factor (WAF) of the first memory region SA1 can decrease.

[0104] In another example, if the write amplification factor (WAF) of the second memory region SA2 is sufficiently low (e.g., below a predetermined second threshold), the memory region management circuit (MAMC) can reduce the capacity of the second memory region MA2. For example, the MAMC can reduce the proportion of the second memory region MA2 in the CXL memory device 120 from 20% to 15%. In this case, as the capacity of the second memory region MA2 decreases, the margin for expansion of other memory regions can increase.

[0105] Figure 11 This illustrates an example embodiment. Figure 1 A block diagram illustrating the configuration of the super memory device. (Refer to...) Figures 1 to 11 , Figure 1 The super storage device 100 can be implemented as Figure 11 200 super storage devices.

[0106] The super storage device 200 may include an operation management circuit 210, a CXL memory device 220, and first CXL memory devices 230a to fourth CXL memory devices 230d. The operation management circuit 210, CXL memory device 220, and first CXL memory devices 230a to fourth CXL memory devices 230d can communicate with each other via a CXL switch SW_CXL. The configuration and operation of the operation management circuit 210, CXL memory device 220, and CXL switch SW_CXL are as described above. Figures 1 to 10 The configuration and operation described are similar, therefore detailed descriptions are omitted. For a more concise explanation, in Figure 11 Four CXL storage devices are shown, but the example embodiment is not limited to the number of CXL storage devices included in the super storage device 200.

[0107] In one example embodiment, the host device 10 may identify the super storage device 200 as a storage device having a capacity corresponding to the sum of the storage capacities of the first CXL storage device 230a to the fourth CXL storage device 230d.

[0108] Each of the first CXL storage devices 230a to the fourth CXL storage device 230d may include one or more storage regions SA. In this case, the multiple storage regions SA included in the first CXL storage devices 230a to the fourth CXL storage devices 230d may correspond to different applications APP. For example, the first CXL storage device 230a may include a storage region corresponding to the first application APP1; the second CXL storage device 230b may include a storage region corresponding to the second application APP2; the third CXL storage device 230c may include a storage region corresponding to the third application APP3; and the fourth CXL storage device 230d may include a storage region corresponding to the fourth application APP4. However, the example embodiment is not limited thereto, and references to the above are consistent. Figures 1 to 9 Similarly, each CXL storage device can also be configured to include two or more storage regions corresponding to two or more applications, respectively.

[0109] CXL memory device 220 can sequentially receive multiple data DTs sent from host device 10. CXL memory device 220 can identify the source application APP_source for each of the multiple data DTs. CXL memory device 220 can distribute the multiple data DTs to different storage areas based on the source application APP_source corresponding to each of the multiple data DTs. For example, CXL memory device 220 can write one or more data DTs corresponding to a first application APP1 to a storage area included in a first CXL memory device 230a, and can write one or more data DTs corresponding to a second application APP2 to a storage area included in a second CXL memory device 230b. In this way, CXL memory device 220 can distribute multiple data DTs to multiple CXL memory devices based on the source application APP_source corresponding to each of the multiple data DTs. In this case, the size of each storage area SA can be increased compared to an example where a CXL memory device 130 includes all of the first storage areas SA1 to the nth storage area San.

[0110] While aspects of exemplary embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A super storage device configured to communicate with a host device executing multiple applications, the super storage device comprising: The operation management circuit is configured to receive multiple data from the host device; A memory device includes a plurality of memory regions and an application classification circuit, the application classification circuit being configured to control the distribution of the plurality of data to the plurality of memory regions based on the source application of each of the plurality of data. as well as One or more storage devices, including multiple storage regions corresponding to the multiple memory regions respectively. The memory device is configured to: write a first memory region to a first storage region, wherein the first memory region is one of the plurality of memory regions and the first storage region is one of the plurality of storage regions and corresponds to the first memory region.

2. The super memory device as claimed in claim 1, wherein, The multiple applications include the first application. The application classification circuit is configured to cache a first plurality of data among the plurality of data in a first memory region, and Among them, the source application corresponding to the first set of multiple data is the first application.

3. The super memory device as described in claim 2, wherein, The multiple applications also include a second application. The plurality of memory regions further includes a second memory region. The application classification circuit is configured to cache a second set of data from the plurality of data in a second memory region. Among them, the source application corresponding to the second set of data is the second application, and The memory device is further configured to: write a second memory region to a second storage region, the second storage region being one of the plurality of storage regions and corresponding to the second memory region.

4. The super-storage device as claimed in claim 3, wherein, The memory device also includes memory region management circuitry configured to adjust the capacity of the first memory region and the second memory region.

5. The super-storage device as claimed in claim 4, wherein, The memory region management circuitry is configured to adjust the capacity of the first memory region and the second memory region based on a write amplification factor provided from the one or more memory devices.

6. The super memory device as claimed in claim 3, wherein, The one or more storage devices include a first storage device. The first storage region and the second storage region are included in the first storage device, which is one of the one or more storage devices. Each of the first and second storage regions includes one or more superblocks.

7. The super-storage device as claimed in claim 3, wherein, The one or more storage devices include a first storage device and a second storage device, wherein the first storage device includes a first storage area and the second storage device includes a second storage area.

8. The super memory device as claimed in claim 1, wherein, The memory device is configured to: write the first memory region to the first memory region when the first memory region is full.

9. The super-storage device as claimed in claim 1, wherein, The application classification circuit is also configured to: identify the source application of the first data based on at least one of the main data area of ​​the first data, the capacity of the first data, and the first logical address corresponding to the first data.

10. The super memory device of claim 1, wherein, The application classification circuit is also configured to identify the source application of the first data based on the extension included in the auxiliary data area of ​​the first data.

11. The super memory device as claimed in claim 1, wherein, The application classification circuit is also configured to: identify the source application of the first data based on the second data, the second data being provided to the memory device before the first data, and the second data being one of the plurality of data.

12. The super-storage device according to any one of claims 1 to 8, wherein, The application classification circuit is also configured to identify the source application of the third data, which is one of the plurality of data, based on the source application identifier included in the auxiliary data area of ​​the third data.

13. The super-storage device according to any one of claims 1 to 8, further comprising: A fast link switch is computed to connect an operation management circuit, a memory device, and one or more memory devices.

14. The super memory device of claim 13, wherein, The memory device and the one or more memory devices are configured to be connected to a computing fast link switch based on the same form factor.

15. A method of operating a memory device, the method comprising: Receive the first data; Identify the source application of the first data, wherein the source application is identified from a plurality of source applications; The first data is stored in a first memory region determined based on the source application, which is one of multiple memory regions, wherein the multiple source applications correspond to the multiple memory regions respectively; and The first memory region is written to an external storage device.

16. The operating method as described in claim 15, wherein, The identification steps are performed based on at least one of the main data area of ​​the first data, the capacity of the first data, and the first logical address corresponding to the first data.

17. The operating method as described in claim 15, wherein, The flushing process is performed based on the fact that the first memory region is full.

18. A super storage device configured to store first data and second data provided from an external host device, the super storage device comprising: A storage device, including a first storage area and a second storage area; as well as A memory device includes a first memory region corresponding to a first memory region and a second memory region corresponding to a second memory region, wherein the memory device is configured as follows: Based on the identification that the first data was issued from a first application on an external host device, the first data is cached in a first memory area; and Based on the identification that the second data was issued by a second application from an external host device, the second data is cached in a second memory area.

19. The super memory device of claim 18, wherein, The memory device is also configured to write the first memory region and the second memory region to the first memory region and the second memory region in an equal manner, respectively.

20. The super-storage device as claimed in claim 18 or 19, wherein, Each of the first and second storage regions includes one or more superblocks.

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