Peripheral component interconnect express device, method of operating a peripheral component interconnect express device, and method of operating a storage device

Abstract

Peripheral component interconnect express (PCIe) devices, methods of operating a peripheral component interconnect express device, and methods of operating a storage device are provided. The method of operating a peripheral component interconnect express device includes initiating establishment of a link between an electronic device and an external electronic device, performing a training operation between the electronic device and the external electronic device to change a link speed between the electronic device and the external electronic device, identifying whether a timeout occurs during the training operation, and re-performing link training and retrying changing the link speed based on the timeout occurring.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0179708, filed with the Korean Intellectual Property Office on December 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of the present invention relate to peripheral component interconnect fast (PCIe) devices, methods of operating them, and methods of operating storage devices. Background Technology

[0004] Semiconductor devices can include interfaces for exchanging data with other external devices, and these interfaces can be implemented according to various specifications. Among the interfaces used to connect semiconductor devices to each other, PCIe interfaces can be applied to various fields of high-speed data transmission. PCIe interfaces (such as serial transmission interfaces) are defined by the PCIe standard and can provide bidirectional connections, enabling simultaneous data transmission and reception. Semiconductor devices connected to each other via PCIe interfaces can improve link speed by performing equalization (EQ) operations during link training, thereby compensating for reduced signal integrity (SI) margin. However, when a timeout occurs during EQ (e.g., a timeout in EQ phase 0 or EQ phase 1), the link may be executed at a relatively low speed compared to the target link speed, and therefore, the data transmission and reception speed between semiconductor devices may be reduced. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a peripheral component interconnect fast (PCIe) device for retrying changes in link speed between electronic devices even if a timeout occurs during PCIe interface equalization, a method of operation thereof, and a method of operation of a storage device.

[0006] The exemplary embodiments of the present invention are not limited to the above-described exemplary embodiments, and other exemplary embodiments not described herein will be clearly understood by those skilled in the art through the following description.

[0007] According to some exemplary embodiments of the present invention, a method for operating a PCIe device in an electronic device is provided, the method comprising: initiating the establishment of a link between the electronic device and an external electronic device; performing a leveling operation between the electronic device and the external electronic device to change the link speed between the electronic device and the external electronic device; identifying whether a timeout occurs during the leveling operation; and re-performing link training and retrying to change the link speed based on the occurrence of the timeout.

[0008] According to some exemplary embodiments of the present invention, a PCIe device in an electronic device is provided, the PCIe device comprising: a plurality of preset memory devices configured to store a plurality of preset memory devices, communication circuitry configured to transmit and receive signals, and a processor. The processor is configured to: initiate the establishment of a link between the electronic device and an external electronic device; perform a leveling operation between the electronic device and the external electronic device to change the link speed between the electronic device and the external electronic device; identify whether a timeout occurs during the leveling operation; and re-execute link training and retry changing the link speed based on the occurrence of the timeout.

[0009] According to some exemplary embodiments of the present invention, a method for operating a storage device including a PCIe device is provided. The method includes: initiating the establishment of a link between the storage device and a host device; performing a leveling operation between the storage device and the host device to change the link speed between the storage device and the host device; identifying whether a timeout occurs in Leveling Phase 0 (EQ Phase 0) during the leveling operation; and based on the timeout in EQ Phase 0, sending a preset request signal for change to the host device after re-performing link training, and retrying to change the link speed.

[0010] According to some exemplary embodiments of the present invention, a storage system is provided, comprising: a host device including a host controller, host storage devices connected to the host controller, and host interface circuitry; and a storage device configured to communicate with the host device, the storage device including a storage controller and non-volatile storage devices. The storage controller may include a Peripheral Component Interconnect Fast (PCIe) device, the PCIe device including a plurality of preset storage devices configured to store a plurality of preset storage devices, communication circuitry configured to transmit and receive signals, and a processor. The processor is configured to initiate the establishment of a link between the host device and the storage device, perform a leveling operation between the host device and the storage device to change the link speed between the host device and the storage device, identify whether a timeout occurs during the leveling operation, and re-perform link training and retry changing the link speed based on the occurrence of the timeout.

[0011] According to some exemplary embodiments of the present invention, the PCIe device of the storage controller is configured to establish a link with the host device via a PCIe interface, thereby linking with the host device. Attached Figure Description

[0012] Some exemplary embodiments will become clearer through the following detailed descriptions in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram illustrating a storage system according to some example embodiments;

[0014] Figure 2This illustrates some example embodiments. Figure 1 A block diagram of the hierarchical state of the storage system;

[0015] Figure 3 This illustrates some example embodiments. Figure 1 A diagram illustrating the process of establishing a storage device link;

[0016] Figure 4 An example of a link established between a host device and a storage device according to some example embodiments is shown;

[0017] Figure 5 It shows the electronic device attempting to pass through Figure 3 An example of using balancing to change link speed;

[0018] Figure 6 A block diagram of a PCIe device according to some example embodiments is shown;

[0019] Figure 7 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments;

[0020] Figure 8 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments;

[0021] Figure 9 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments;

[0022] Figure 10 This is a block diagram illustrating a memory system with PCIe devices according to some example embodiments; and

[0023] Figure 11 This is a block diagram illustrating an electronic system with PCIe devices according to some example embodiments. Detailed Implementation

[0024] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings. Several exemplary embodiments are shown in the drawings, and their detailed descriptions are provided. However, this is not intended to limit the various exemplary embodiments to any particular form. For example, it will be apparent to those skilled in the art that the exemplary embodiments can be modified in various ways.

[0025] The components described in the detailed description, such as “component,” “unit,” “module,” “block,” “device,” and “device,” as well as the functional blocks shown in the accompanying drawings, may be provided as software, hardware, or a combination thereof. For example, software may include machine code, firmware, embedded code, and application software. Hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive devices, or combinations thereof.

[0026] In the attached diagram, preset may refer to the initial preset.

[0027] In the accompanying drawings, for ease of description, a memory system is illustrated as an example using a Peripheral Component Interconnect Fast (PCIe) device (e.g., PCIe devices 115 and 215) according to some example embodiments, but the example embodiments are not limited thereto. Systems / devices using PCIe devices according to some example embodiments can be applied to various electronic systems that perform data communication based on a PCIe interface.

[0028] Figure 1 This is a block diagram illustrating a storage system 10 according to some example embodiments.

[0029] refer to Figure 1 Storage system 10 may include host device 100 and storage device 200. Furthermore, storage device 200 may include storage controller 210 and non-volatile memory (NVM) device 220. Additionally, according to some example embodiments, host device 100 may include host controller 110, host storage device 120, and interface circuitry 130. Host storage device 120 may serve as a buffer memory for temporarily storing data to be sent to or from storage device 200.

[0030] Storage device 200 may include a storage medium for storing data in response to a request from host device 100. For example, storage device 200 may include at least one of a solid-state drive (SSD), embedded memory, and removable external memory. When storage device 200 includes an SSD, it may include a device compliant with the Non-Volatile Memory Faster (NVMe) standard. When storage device 200 includes embedded memory or external memory, it may include a device compliant with the Universal Flash Memory (UFS) standard or the Embedded Multimedia Card (eMMC) standard. Host device 100 and storage device 200 may each generate and transmit data packets according to their respective standard protocols.

[0031] When the NVM device 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In another example, storage device 200 may include other types of NVM. For example, storage device 200 may include magnetic random access memory (MRAM), spin-transfer torque MRAM (STT-MRAM), conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM, and other types of memory.

[0032] According to some example embodiments, the host controller 110 and the host storage device 120 may be provided as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 110 and the host storage device 120 may be integrated into a single semiconductor chip. For example, the host controller 110 may include any one of a plurality of modules provided in an application processor, and the application processor may be provided as a system-on-a-chip (SoC). Furthermore, the host storage device 120 may include embedded memory disposed within the application processor, or may include NVM or memory modules disposed outside the application processor.

[0033] The host controller 110 can manage operations that store data (e.g., write data) in the buffer of the host storage device 120 in the NVM device 220, or store data (e.g., read data) in the buffer of the NVM device 220.

[0034] Interface circuit 130 can perform data communication between host device 100 and storage device 200 according to a communication protocol. This communication protocol can be the PCIe standard. In the following description, data exchange between host device 100 and storage device 200 is based on the PCIe standard. Here, the sending and receiving paths along which data flows between host device 100 and storage device 200 are defined as links, and a link can include one or more pairs of sending and receiving paths. Furthermore, each pair of sending and receiving paths is defined as a channel, and the number of channels forming a link is defined as the link width. Host device 100 and storage device 200 can establish links at the physical layer of the PCIe interface protocol based on PCIe device 115 and PCIe device 215, respectively, to send and receive data from each other.

[0035] The host controller 110 may include a PCIe device 115, which establishes / sets up a link with the external storage device 200 via a PCIe interface. The PCIe device 115 may establish a data channel for actually sending and receiving data, a clock channel for receiving clock signals, and a power channel for inputting power voltage on multiple transmit and receive ports in the interface circuitry 130. Furthermore, the PCIe device 115 can perform the link process to establish a link with the storage device 200 by determining configurable PHY parameter values ​​at the physical layer. For example, the PCIe device 115 may include a Link Training and State Machine (LTSSM) representing various states of the link, and based on the LTSSM, link width, data rate, number of channels, channel polarity, boundaries between consecutive bits, etc., can be determined during the link process.

[0036] The storage controller 210 may include a host interface circuit 211, a memory interface 212, and a central processing unit (CPU) 213. The storage controller 210 may also include a flash translation layer (FTL) 214, a PCIe device 215, a buffer memory 216, an error correction code (ECC) engine 217, and an encryption / decryption engine 218. The storage controller 210 may also include working memory (not shown) that loads the FTL 214, and data write and read operations of the NVM device 220 may be controlled by the CPU 213 executing the FTL 214.

[0037] The host interface circuit 211 can send data packets to and receive data packets from the host device 100. Data packets sent from the host device 100 to the host interface circuit 211 may include commands or data to be written to the NVM device 220, and data packets sent from the host interface circuit 211 to the host device 100 may include responses to commands, data read from the NVM device 220, etc. The memory interface 212 can send data to be written to the NVM device 220 or receive data read from the NVM device 220.

[0038] FTL 214 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping involves translating logical addresses received from host device 100 into physical addresses used for actual data storage in NVM device 220. Wear leveling is a technique for limiting and / or preventing excessive degradation of specific blocks by ensuring substantially uniform use of blocks within NVM device 220; this can be performed, for example, by firmware techniques that balance the number of physical block erases. Garbage collection involves a technique for ensuring available capacity within NVM device 220 by copying valid data from blocks to new blocks and then erasing existing blocks.

[0039] PCIe device 215 can establish data channels for actual data transmission and reception, clock channels for receiving clock signals, and power channels for inputting power voltage on multiple transmit and receive ports in host interface circuit 211. Furthermore, PCIe device 215 can perform a connection process to establish a link with host device 100 by determining PHY parameter values ​​that can be configured at the physical layer. For example, PCIe device 215 may include an LTSSM representing various states of the link, and based on the LTSSM, link width, data rate, number of channels, channel polarity, boundaries between consecutive bits, etc., can be determined during the linking process.

[0040] PCIe devices (e.g., PCIe device 115 and PCIe device 215) can perform equalization to change the link speed between devices. According to some example embodiments, if a timeout occurs during this equalization process, the PCIe devices may not immediately reconnect at the original link speed but will instead retry changing the link speed. [Reference] Figure 6 The configuration of a PCIe device according to some example embodiments is described, and references are made to Figures 7 to 9 The method for changing the retry link speed of PCIe devices is described in detail.

[0041] In addition, the buffer memory 216 can temporarily store data to be written to or read from the NVM device 220. The buffer memory 216 can be located inside or outside the storage controller 210.

[0042] ECC engine 217 can perform error detection and correction functions on the read data read from NVM device 220. More specifically, ECC engine 217 can generate parity bits for the write data to be written to NVM device 220 and store the parity bits generated in this way together with the write data in NVM device 220. When reading data from NVM device 220, ECC engine 217 can correct errors in the read data by using the parity bits read from NVM device 220 together with the read data, and then output the error-corrected read data.

[0043] The encryption / decryption engine 218 can perform at least one of encryption and decryption operations on data input to the storage controller 210. For example, the encryption / decryption engine 218 can perform encryption and / or decryption operations using a symmetric key algorithm. Here, the encryption / decryption engine 218 can use, for example, the Advanced Encryption Standard (AES) algorithm or the Data Encryption Standard (DES) algorithm to perform encryption and / or decryption operations. Furthermore, for example, the encryption / decryption engine 218 can use a public-key encryption algorithm to perform encryption and / or decryption operations. In this case, the encryption / decryption engine 218 can, for example, use the public key to perform encryption in the encryption operation and use the private key to perform decryption in the decryption operation. For example, the encryption / decryption engine 218 can use the RivestShamir Adleman (RSA), Elliptic Curve Cryptography (ECC), or Diffie-Hellman (DH) encryption algorithms. However, the example embodiment is not limited to this; the encryption / decryption engine 218 can use quantum cryptography techniques (such as homomorphic encryption (HE), post-quantum cryptography (PQC), and function cryptography (FE)) to perform encryption and / or decryption operations.

[0044] Figure 2 This illustrates some example embodiments. Figure 1 A block diagram of the hierarchical state of the storage system 10.

[0045] refer to Figure 1 and Figure 2 Each of the host device 100 and the storage device 200 can form a layered protocol stack based on the PCIe standard. The host device 100 includes a transaction layer 405, a data link layer 410, and a physical layer 420.

[0046] Figure 1 The interface circuit 130 in the host device 100 can, for example, be based on Figure 2 The PCIe standard in the memory constitutes a layered protocol stack. Furthermore, the storage device 200 includes a transaction layer 505, a data link layer 510, and a physical layer 520.

[0047] Figure 1 The host interface circuit 211 in the storage device 200 can, for example, be based on Figure 2 The PCIe standard in the protocol stack forms a layered protocol stack. Components that communicate with each other according to the PCIe standard (e.g., host device 100 and / or storage device 200) can use data packets to send and receive information.

[0048] Data packets can be formed in transaction layers 405 and 505 and link layers 410 and 510, and sent from the sending component (e.g., host device 100 or storage device 200) to the receiving component (e.g., storage device 200 or host device 100).

[0049] In the following text, for ease of description, data packets are described as being sent, for example, from host device 100 to storage device 200. That is, data packets can be formed at transaction layer 405 and link layer 410 and sent from host device 100 to storage device 200.

[0050] Although packets sent from the transaction layer 405 of host device 100 pass through different layers, the packets can be further extended by adding the information necessary for each layer to control the packets.

[0051] Storage device 200 can perform transformations on data packets received from host device 100, such that the data packets are interpreted at physical layer 520 and link layer 510, and the transformed data packets are processed at transaction layer 505.

[0052] Transaction layers 405 and 505 can serve as interfaces between link layers 410 and 510 and the core that controls the corresponding components. For example, transaction layer 405 can act as an interface between link layer 410 and the core located in host controller 110 for controlling host device 100. Furthermore, for example, transaction layer 505 can act as an interface between link layer 510 and the core (e.g., CPU 213) located in storage controller 210 for controlling storage device 200. That is, transaction layers 405 and 505 can be responsible for assembling or disassembling data packets (e.g., transaction layer packets (TLPs)).

[0053] Link layers 410 and 510 can act as intermediate layers between transaction layers 405 and 505 and physical layers 420 and 520, respectively. More specifically, link layers 410 and 510 can apply reliable mechanisms to transaction layer packets, enabling the exchange of transaction layer packets between transaction layers 405 and 505 and physical layers 420 and 520, respectively. For example, link layer 410 receives assembled transaction layer packets via transaction layer 405. Link layer 410 can apply a packet sequence identifier (e.g., an identification number or packet number) to the transaction layer packets already received by transaction layer 405. Subsequently, link layer 410 can perform a calculation by applying an error detection code (e.g., cyclic redundancy check (CRC)) to the transaction layer packets for which the packet sequence identifier has been applied. Then, link layer 410 can send the modified transaction layer packets to physical layer 420, and physical layer 420 can send the packets received from link layer 410 to an external device (e.g., storage device 200).

[0054] As another example, link layer 510 receives assembled transaction layer packets via transaction layer 505. Link layer 510 may apply a packet sequence identifier (e.g., an identifier or packet number) to the transaction layer packets already received by transaction layer 505. Subsequently, link layer 510 may perform a calculation by applying an error detection code (e.g., CRC) to the transaction layer packets to which the packet sequence identifier has been applied. Link layer 510 may then send the modified transaction layer packets to physical layer 520, and physical layer 520 may send the packets received from link layer 510 to an external device (e.g., host device 100).

[0055] Physical layers 420 and 520 may each include logic sub-blocks 421 and 521 and electrical sub-blocks 422 and 522. Logic sub-blocks 421 and 521 are responsible for enabling physical layers 420 and 520 to perform digital functions. More specifically, logic sub-blocks 421 and 521 may include transmitters for preparing information output by electrical sub-blocks 422 and 522, respectively. Furthermore, logic sub-blocks 421 and 521 may include receivers for identifying information received from external devices and preparing to transmit the information to link layers 410 and 510 before passing it to them. For example, logic sub-block 421 may prepare information output by electrical sub-block 422 to an external device (e.g., storage device 200) and may identify information received from an external device (e.g., storage device 200) and prepare to send that information to link layer 410. As another example, logic subblock 521 can prepare information to be output to an external device (e.g., host device 100) by electrical subblock 522, and can identify information received from an external device (e.g., host device 100) and prepare to send that information to link layer 510.

[0056] Here, a link establishment procedure (e.g., LTSSM) can be performed to send and receive data packets between host device 100 and storage device 200.

[0057] In order to send and receive data packets between host device 100 and storage device 200, the process of establishing a link (e.g., LTSSM) can be performed between physical layers 420 and 520, and more specifically, between logical sub-blocks 421 and 521.

[0058] Figure 3 The process of establishing a data packet sending and receiving link between host device 100 and storage device 200 is further illustrated.

[0059] Figure 3 This illustrates some example embodiments. Figure 1 A diagram illustrating the process of establishing a link between storage device 200 and storage device 200.

[0060] Figure 1 and Figure 3 The process of establishing a link (e.g., LTSSM) between storage device 200 and host device 100 is illustrated. For example, the LTSSM can provide a link process, which is a control process for establishing / setting up and initializing the link. In addition to configuring and initializing the link on the PCIe interface, the LTSSM can also perform packet transmission support, link error recovery, and restart the PCIe interface in a low-power state.

[0061] refer to Figure 1 and Figure 3 The initial state can be a detection state. In the detection state, when a connection from another device (e.g., host device 100) is detected, the storage device 200 can enter a polling state.

[0062] In polling mode, the generated versions of the protocol (e.g., PCIe) of host device 100 and storage device 200 can be determined, and the data transfer rate (e.g., link speed) can be determined based on the highest compatible generated version. Furthermore, in polling mode, storage controller 210 can set bit locking, symbol locking, block locking, and channel polarity. In polling mode, storage controller 210 can send TS1 and TS2 as ordered sets at a transfer rate of 2.5 GT / s.

[0063] After polling, storage device 200 can enter configuration mode. In configuration mode, storage controller 210 can set the number of links, such as link width. Furthermore, in configuration mode, storage controller 210 can exchange TS1 and TS2 with host device 100 at a transmission rate of 2.5 GT / s. Storage controller 210 can assign channel numbers and can verify and correct channel inversions. Storage controller 210 can eliminate timing differences between channels.

[0064] After configuration, the storage controller 210 can enter the L0 state. The L0 state represents the normal operating state, in which data is sent and received via the established link. In the L0 state, the storage controller 210 can communicate with the host device 100 via the link.

[0065] The L0s state can represent an Active State Power Management (ASPM) state, i.e., an electrically idle / standby state. Before entering the L0 state, the storage controller 210 can reduce power consumption in the L0s state. The L1 state can be a power-saving state (e.g., low-power standby / sleep state), consuming less power than the L0s state. The L2 state is a cutoff state, using a voltage low enough to detect wake-up events. The storage controller 210 can enter a disabled state when a link is disabled. The storage controller 210 can use the loopback state for testing and fault isolation. The storage controller 210 can use the hot reset state when resetting a link via in-band signaling.

[0066] The recovery state can perform functions such as removing bit locks, symbol locks, and inter-channel offsets. It can also adjust link speeds based on data (e.g., training sequences sent and received by the transmitter and receiver) when an error occurs while operating in L0 state or when returning from L1 state to L0 state. For example, the recovery state can have sub-states such as Recovery.RcvrLock, Recovery.Equalization, Recovery.Speed, Recovery.RcvrCfg, and Recovery.Idle, and can enter detection state, configuration state, L0 state, loopback state, hot reset state, or disabled state based on the results of these sub-states. In the Recovery.Equalization sub-state, equalization between devices can be optimized by exchanging training sequences with the receiver. In the Recovery.Equalization sub-state, presets can be set when changing the stage from stage 0 to stage 3, and equalization can be completed. Each stage from stage 0 to stage 3 represents an equalization process.

[0067] The loopback state represents the test state, and the LTSSM can enter the loopback state based on the loopback bit values ​​in a preset order set of symbols exchanged between devices connected to the PCIe interface. In the loopback state, the receiver can retransmit all received data packets in the same manner. In the hot reset state, the LTSSM can perform the function of resetting the link. In the disabled state, when the receiver is in a low-impedance state, the LTSSM can switch the transmitter to an electrically idle state. During the link establishment process, the LTSSM can perform the above functions while moving between the aforementioned 11 states (e.g., detection state, polling state, ..., hot reset state, etc.) in a specific order.

[0068] Figure 4 An example of a link established between host device 100 and storage device 200 according to some example embodiments is shown.

[0069] Figure 1 and Figure 4 An example of a link (LINK) established between interface circuitry 130 of host device 100 and host interface circuitry 211 of storage device 200 is shown. The link (LINK) may include at least one channel LANE. For example, the link (LINK) may include a number of channel LANEs corresponding to a number selected from the group consisting of 1, 2, 4, 8, and 16. For example, it is assumed that the link (LINK) includes four channel LANEs. Channel LANEs can transmit or receive signals simultaneously. Channel LANEs may correspond to parallel signal lines. Channel LANEs may be configured to have the same link speed.

[0070] The data transfer rate of a link (LINK) can be determined by multiplying the number of LANEs (e.g., the link width) contained in the link by the link speed of the respective LANE. According to some example embodiments, the storage device 200 can adjust the link width (e.g., the number of LANEs contained in the link) to adjust the data transfer rate of the link.

[0071] Each channel in the LANE may include a transmit channel and a receive channel. The transmit channel of host interface circuit 211 may correspond to the arrow pointing from host interface circuit 211 to interface circuit 130. The receive channel of host interface circuit 211 may correspond to the arrow pointing from interface circuit 130 to host interface circuit 211. Each of the transmit and receive channels may include complementary signal lines.

[0072] Here, in reference Figure 3 In the described recovery state, link training and load balancing can be performed between the interface circuit 130 of the host device 100 and the host interface circuit 211 of the storage device 200. In the PCIe standard, load balancing can be performed in a total of four stages (e.g., stages 0 to 3).

[0073] Figure 5 It shows the electronic device attempting to pass through Figure 3 An example of using balancing to change link speed.

[0074] refer to Figure 1 and Figure 5 Electronic devices connected to each other via PCIe interfaces can perform load balancing between the devices to change the link speed.

[0075] Two distinct components, more specifically root complexity device 801 and endpoint device 803, can be connected to each other via a pair of distinct communication links 805a and 805b. For example, root complexity device 801 can be connected to... Figure 1The interface circuit 130 of the host device 100 corresponds to the device included in the interface circuit. Furthermore, the endpoint device 803 can be connected to... Figure 1 The host interface circuit 211 of the storage device 200 includes corresponding devices. The root complex device 801 and the endpoint device 803 respectively include transmitting logic circuits 802a and 804b and receiving logic circuits 804a and 802b to communicate with each other.

[0076] In some example embodiments, root complex device 801 may include a downstream port as described in the PCIe standard. Furthermore, in some example embodiments, endpoint device 803 may include an upstream port as described in the PCIe standard.

[0077] During PCIe interface-based load balancing, the first dataset can be transferred from the downstream port (e.g., root complex device 801) to the upstream port (e.g., endpoint device 803).

[0078] During PCIe interface-based equalization, the transmission rate of the first dataset may be less than or equal to (or substantially equal to) the first maximum data transmission rate associated with root complex device 801 and the second maximum data transmission rate associated with endpoint device 803.

[0079] In recent years, with the increase in PCIe link speeds, signal integrity (SI) margins may decrease. Root complexity device 801 (corresponding to host device 100) and endpoint device 803 (corresponding to storage device 200) can compensate for the reduced SI gain due to the increased link speed. To this end, root complexity device 801 and endpoint device 803 can perform equalization via PCIe devices 115 and 215, respectively. When the preset (e.g., initial preset) requested by PCIe device 115 of root complexity device 801 or PCIe device 215 of endpoint device 803 during the equalization process is not an optimized preset, a timeout may occur at equalization operation 0 (e.g., EQ phase 0) or equalization operation 1 (e.g., EQ phase 1). When a timeout occurs, root complexity device 801 and endpoint device 803 may link at a relatively lower link speed (e.g., third generation) than the target link speed (e.g., fourth or fifth generation), which may degrade data transmission and reception performance.

[0080] Therefore, when a timeout occurs during equalization operation (e.g., EQ phase 0 or EQ phase 1), according to some example embodiments, PCIe devices 115 and 215 may request a modified preset (e.g., an initial preset different from the preset when the timeout occurred) to retry changing the link speed, thereby preventing the link from being formed at a relatively low link speed.

[0081] Furthermore, it can prevent link speeds from decreasing due to timeouts, thereby improving data transmission and / or reception performance between electronic devices connected to each other via the PCIe interface (e.g., increasing transmission and reception rates) and enhancing the overall system communication performance. Reference Figures 6 to 9 The operation of PCIe devices 115 and 215 according to some example embodiments is described in detail.

[0082] Figure 6 A block diagram of a PCIe device 600 according to some example embodiments is shown.

[0083] refer to Figure 6 Any or all of the elements described can be compared with the reference. Figure 6 This allows communication with any or all other elements described. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcastly with any or all other elements in any of the figures, for example, in a serial and / or parallel manner, via a bus (not shown) such as a wireless and / or wired bus to transmit and / or exchange and / or receive information (e.g., but not limited to data and / or commands). The information may be in various encoding formats, such as analog and / or digital formats, but is not limited thereto.

[0084] Figure 6 The PCIe device 600 in the middle can be with Figures 1 to 5 PCIe device 115 and PCIe device 215 correspond to each other. Figure 6 In this context, an electronic device may represent storage device 200, while an external electronic device may represent host device 100. However, the inventive concept is not limited thereto, and according to some example embodiments, an electronic device may represent host device 100, while an external electronic device may represent storage device 200.

[0085] refer to Figure 6 The PCIe device 600 may include a processor 610, a communication circuit 620, and a memory 630.

[0086] The processor 610 can control the PCIe device 600 by executing multiple commands. For example, the processor 610 can execute software (e.g., a program) to control at least one different component (e.g., a hardware or software component) of the PCIe device 600, and can perform various data processing or calculations related to the PCIe interface.

[0087] Processor 610 can initiate link establishment between an electronic device and an external electronic device, and can perform equalization between the electronic device and the external electronic device to change the link speed between them. Processor 610 can identify whether a timeout occurs during equalization. When a timeout is identified, processor 610 can re-perform link training and equalization between the electronic device and the external electronic device to retry changing the link speed. In some example embodiments, when equalization operation 0 or equalization operation 1 times out while changing the link speed from 16 GT / s (e.g., fourth generation) to 32 GT / s (e.g., fifth generation), processor 610 can retry, changing the link speed to 32 GT / s (e.g., fifth generation) instead of immediately connecting to the original link speed (below 32 GT / s (e.g., fifth generation)). For example, processor 610 can re-perform link training between the electronic device and the external electronic device to gradually increase the link speed. Here, processor 610 can force a return to the detection state of LTSSM (see [link]). Figure 3 The link training is performed again, and then the link speed is increased from the first generation to the fourth generation again by recovering the state. During the retry of changing the link speed from 16GT / s (e.g., fourth generation) to 32GT / s (e.g., fifth generation), the processor 610 can retry changing the link speed by requesting a different preset (hereinafter referred to as the change preset) from the preset that timed out in the Recovery.RcvrCfg state or by sending a transmission signal generated based on the change preset. Here, the processor 610 can select the different preset from the preset that timed out as the change preset from a plurality of presets stored in memory 630 based on pre-charge. Here, the preset may include initial settings for adjusting the waveform of the transmission signal during the equalization process. The preset may correspond to the presets described in the PCIe standard. For example, the preset may include pre-charge, de-emphasis, and pre-cursor (pre-charge, de-emphasis, pre-cursor) as described in the PCIe standard. ), back cursor ( The initial preset value, etc., can specifically represent the first preset value after a link speed change. Starting from a link speed of 16GT / s (e.g., fourth generation), bidirectional preset requests (e.g., initial preset requests) can be made between the electronic device and an external electronic device. For example, before entering a sub-state of recovery (e.g., Recovery.Speed) to change the speed, the processor 610 can send a preset request signal to the other electronic device, which includes the initial preset expected in another sub-state (e.g., Recovery.RcvrCfg). The other electronic device should use a transmission signal based on the requested preset to send the first data packet after the link speed change. According to some example embodiments, when a timeout occurs during a link speed change, the processor 610 can retry changing the link speed by requesting a change of preset from the other device or by sending a transmission signal generated based on the change of preset to the other device. Reference will be made below. Figures 7 to 9 Provide a detailed description.

[0088] The communication circuit 620 may be electrically connected to the processor 610 and may receive or send signals to external devices via a wired communication network. For example, the communication circuit 620 may receive or send signals (e.g., preset request signals) to external electronic devices for link training and equalization between the electronic devices and external electronic devices.

[0089] Memory 630 may be provided as a non-transitory storage device and may store multiple commands or data executed by processor 610. For example, as a non-limiting example, memory 630 may include any type of memory accessible to processor 610, such as RAM, read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, NVM, and combinations thereof. Memory 630 may communicate with processor 610 to store multiple presets for link training and equalization. Here, the stored multiple presets may include presets described in the PCIe standard (e.g., initial presets). For example, based on the waveform of the signal, the multiple presets may include presets P0 to P9. However, the exemplary embodiment is not limited thereto, and the multiple presets may include any number of presets.

[0090] Figure 7 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments.

[0091] refer to Figure 7 According to some example embodiments, a method for changing link speed by retrying a PCIe device may include operations S100 to S140. Figure 7 The description is consistent with the above reference. Figures 1 to 6The repeated descriptions given will be replaced with references. Figures 1 to 6 The description.

[0092] exist Figure 7 In China, PCIe devices can be used with... Figures 1 to 6 Corresponding to any PCIe device (e.g., 115, 215, and 600). In Figure 7 In this context, an electronic device may represent storage device 200, while an external electronic device may represent host device 100. However, the inventive concept is not limited thereto, and according to some example embodiments, an electronic device may represent host device 100, while an external electronic device may represent storage device 200.

[0093] In operation S100, the PCIe device can initialize the establishment of a link between the electronic device and an external electronic device. The PCIe device can perform link training and equalization as described in the PCIe standard to establish the link between the electronic device and the external electronic device. For example, the PCIe device can perform link training and equalization as described in the PCIe standard to change the link speed between the electronic device and the external electronic device (e.g., increase the link speed from 16GT / s (Generation 4) to 32GT / s (Generation 5)).

[0094] In operation S110, the PCIe device can perform equalization between the electronic device and the external electronic device to change the link speed. For example, in a sub-state of the recovery state (e.g., Recovery.Equalization state), the PCIe device can exchange training sequences between the electronic device and the external electronic device during phases 0 to 3 to optimize the equalization between the electronic device and the external electronic device. When the link speed is 16GT / s or higher, in a sub-state of the recovery state (e.g., Recovery.RcvrCfg), a preset request signal can be exchanged between the electronic device and the external electronic device to request a desired preset (e.g., initial preset) from the other electronic device. Subsequently, when initially transmitting data packets at the changed link speed, the electronic device and the external electronic device can send transmission signals according to the preset requested by the other electronic device.

[0095] In operation S120, the PCIe device can identify whether a timeout has occurred during the equalization process. Here, a timeout may indicate that the phased operation of equalization has not been completed within a set time because the preset (e.g., initial preset) requested by the electronic device or external electronic device (see operation S110) is not a preset optimized for the current link. For example (for ease of description, it is assumed that the PCIe device is included in the electronic device), the timeout may include: a first timeout caused by the electronic device failing to receive a signal sent by the external electronic device (e.g., corresponding to the timeout in equalization operation 0 (phase 0); and a second timeout caused by the external electronic device failing to receive a signal sent by the electronic device (e.g., corresponding to the timeout in equalization operation 0 (phase 0)).

[0096] If no timeout occurs during the equalization process, the PCIe device can perform operation S130; if a timeout occurs during the equalization process, the PCIe device can perform operation S140.

[0097] In operation S130, the PCIe device can establish a link between the electronic device and an external electronic device. For example, the PCIe device can link the electronic device and the external electronic device at a changed link speed (e.g., an increased link speed).

[0098] In operation S140, the PCIe device can retry changing the link speed between the electronic device and the external electronic device. That is, the PCIe device can re-perform link training, change the preset of operation S110 (e.g., the initial preset), and retry changing the link speed between the electronic device and the external electronic device. For example, when a timeout occurs, the PCIe device can force a return to the detection state of the LTSSM (see...). Figure 3 The PCIe device can then re-perform link training and gradually increase the link speed to the target link speed via a recovery state. The PCIe device can retry changing the link speed to the target link speed by using a preset change (e.g., operation S110) during the equalization process of changing the link speed to the target link speed. Here, the target link speed may represent the link speed intended to be achieved by changing the link speed. According to some example embodiments, refer to... Figure 8 A method for retrying to change the link speed of the PCIe device when the first timeout occurs is described. Additionally, refer to... Figure 9 A method is described for retrying to change the link speed of the PCIe device when a second timeout occurs.

[0099] According to some example embodiments, when a timeout occurs during equalization operation (e.g., EQ phase 0 or EQ phase 1), the PCIe device can retry changing the link speed. Accordingly, according to some example embodiments, the PCIe device can prevent linking at the original link speed (relatively low speed) due to a timeout, and further improve data transmission and / or reception performance between electronic devices based on the changed link speed (relatively high speed).

[0100] Figure 8 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments.

[0101] refer to Figure 8 According to some example embodiments, the method of retrying to change the link speed via a PCIe device may include operations S200 to S245. Figure 8 The description is consistent with the above reference. Figures 1 to 7 The repeated descriptions given will be replaced with references. Figures 1 to 7 The description.

[0102] exist Figure 8 In China, PCIe devices can be used with... Figures 1 to 7 Corresponding to any PCIe device (e.g., 115, 215, and 600). In Figure 8 In this context, an electronic device may represent storage device 200, while an external electronic device may represent host device 100. However, the inventive concept is not limited thereto, and according to some example embodiments, an electronic device may represent host device 100, while an external electronic device may represent storage device 200.

[0103] exist Figure 8 For ease of description, it is assumed that a PCIe device is a PCIe device included in an electronic device, but the example embodiments are not limited thereto. According to the embodiments, a PCIe device may refer to a PCIe device included in an external electronic device.

[0104] Description of operations S200 to S210 and Figure 7 The descriptions of operations S100 to S110 are repeated, therefore they are replaced with... Figure 7 Description of operations S100 to S110.

[0105] In operation S220, the PCIe device can identify whether a first timeout has occurred during the equalization process. Here, a timeout may indicate that the phased operation of equalization has not been completed within a set time because the preset (e.g., initial preset) requested by the electronic device or external electronic device (see operation S110) is not a preset optimized for the current link. For example, the first timeout may be caused by the electronic device failing to receive a signal sent from an external electronic device. Here, the first timeout may correspond to the timeout of equalization operation 0 (phase 0).

[0106] If no first timeout occurs during the equalization process, the PCIe device can perform operation S230, and if a first timeout occurs during the equalization process, the PCIe device can perform operation S241.

[0107] In operation S230, the PCIe device can establish a link between an electronic device and an external electronic device. The PCIe device can link (or establish) the link between the electronic device and the external electronic device at a modified link speed. For example, when equalization is optimized at a link speed of 32GT / s (Gen 5) (e.g., equalization is completed and no timeout occurs), the PCIe device can link the electronic device and the external electronic device at 32GT / s (Gen 5).

[0108] In operation S241, the PCIe device can identify whether the number of retries used to change the link speed is greater than or equal to a threshold. When the number of retries is greater than or equal to the threshold, the PCIe device can perform operation S230; or when the number of retries is less than the threshold, the PCIe device can perform operation S243. Here, when the number of retries is greater than or equal to the threshold, the PCIe device can, in operation S230, link (or establish) the link between the electronic device and the external electronic device to the original link speed.

[0109] In operation S243, the PCIe device can send a modified preset request signal to an external electronic device and retry changing the link speed between the electronic device and the external electronic device. That is, when a first timeout occurs during the process of changing the link speed to the target link speed, the PCIe device can re-perform link training to change the preset in operation S210 (e.g., the initial preset), thereby retrying to change the link speed between the electronic device and the external electronic device. For example, when a first timeout occurs during the process of changing the link speed to the target link speed, the PCIe device can force a return to the detection state of the LTSSM (see [link to LTSSM]). Figure 3The PCIe device can re-perform link training and then gradually increase the link speed to the target link speed via a recovery state. In a recovery state (e.g., Recovery.RcvrCfg state) used to change the link speed to the target link speed, the PCIe device can retry changing the link speed by sending a signal requesting a first change preset to an external electronic device (e.g., a change preset request signal), the first change preset being a different initial preset from the preset that timed out (e.g., the initial preset). For example, the PCIe device can select the first change preset from a plurality of presets based on pre-loaded memory. Subsequently, during the equalization process of changing the link speed to the target link speed, the external electronic device can send a transmission signal generated based on the first change preset to the electronic device. That is, the PCIe device can use the first change preset to re-perform equalization for the target link speed (e.g., receive a transmission signal generated based on the first change preset to re-perform equalization for the target link speed) and retry changing the link speed to the target link speed. Here, the target link speed can represent the link speed intended to be achieved by changing the link speed.

[0110] In operation S245, the PCIe device may count the number of retries each time the PCIe device retryes changing the link speed. The PCIe device may store the retry count in memory. To reduce and / or prevent communication performance degradation due to repeated retries, according to some example embodiments, the PCIe device may perform retries to change the link speed within a desired (and / or alternatively, predetermined) number of retries. After counting the retries, the PCIe device may perform operation S210 again (e.g., link training and equalization operations).

[0111] When a timeout occurs during equalization operation, according to some example embodiments, the PCIe device can retry changing the link speed by requesting a modified preset (e.g., an initial preset different from the preset where the timeout occurred).

[0112] Accordingly, according to some example embodiments, PCIe devices can reduce and / or prevent links from being established at the original link speed (relatively low speed) due to timeouts, and further improve data transmission and / or reception performance between electronic devices based on the changed link speed (relatively high speed).

[0113] Figure 9 This is a flowchart illustrating a method of operating a PCIe device according to some example embodiments.

[0114] refer to Figure 9 According to some example embodiments, the method of retrying to change the link speed via a PCIe device may include operations S300 to S345. Figure 9 The description is consistent with the above reference. Figures 1 to 8 The repeated descriptions given will be replaced with references. Figures 1 to 8 The description.

[0115] exist Figure 9 In China, PCIe devices can be used with... Figures 1 to 8 Corresponding to any PCIe device (e.g., 115, 215, and 600). In Figure 9 In this context, an electronic device may represent storage device 200, while an external electronic device may represent host device 100. However, the inventive concept is not limited thereto, and according to some example embodiments, an electronic device may represent host device 100, while an external electronic device may represent storage device 200.

[0116] exist Figure 9 For ease of description, it is assumed that a PCIe device is a PCIe device included in an electronic device, but the example embodiments are not limited thereto. According to the embodiments, a PCIe device may refer to a PCIe device included in an external electronic device.

[0117] Description of operations S300 to S310 and Figure 7 The descriptions of operations S100 to S110 are repeated, therefore they are replaced with... Figure 7 Description of operations S100 to S110.

[0118] In operation S320, the PCIe device can identify whether a second timeout has occurred during the equalization process. Here, a timeout may indicate that the phased operation of equalization has not been completed within a set time because the preset (e.g., initial preset) requested by the electronic device or external electronic device (see operation S110) is not a preset (e.g., initial preset) optimized for the current link. For example, the second timeout may be caused by the external electronic device failing to receive the signal sent from the electronic device. Here, the second timeout may correspond to the timeout of equalization operation 1 (phase 1).

[0119] If no second timeout occurs during the equalization process, the PCIe device can perform operation S330, and if a second timeout occurs during the equalization process, the PCIe device can perform operation S341.

[0120] In operation S330, the PCIe device can establish a link between an electronic device and an external electronic device. The PCIe device can link (or establish) the link between the electronic device and the external electronic device at a modified link speed. For example, when equalization is optimized at a link speed of 32GT / s (Gen 5) (e.g., equalization is completed and no timeout occurs), the PCIe device can link the electronic device and the external electronic device at 32GT / s (Gen 5).

[0121] In operation S341, the PCIe device can identify whether the number of retries used to change the link speed is greater than or equal to a threshold. When the number of retries is greater than or equal to the threshold, the PCIe device can perform operation S330, or when the number of retries is less than the threshold, the PCIe device can perform operation S343. Here, when the number of retries is greater than or equal to the threshold, the PCIe device can, in operation S330, connect (or establish) the link between the electronic device and the external electronic device to the original link speed.

[0122] In operation S343, the PCIe device can send a transmission signal generated by comparing the preset requested by the preset request signal of the external electronic device (e.g., the initial preset) with the preset that timed out to the external electronic device, and can retry changing the link speed between the electronic device and the external electronic device.

[0123] In some example embodiments, the PCIe device can re-perform link training when a second timeout occurs while the link speed is being changed to the target link speed. For example, when a second timeout occurs during the equalization process of changing the link speed to the target link speed, the PCIe device can force a return to the detection state of the LTSSM (see [link to LTSSM]). Figure 3 The PCIe device can then re-perform link training and gradually increase the link speed to the target link speed via a recovery state. Subsequently, the PCIe device can receive a preset request signal from an external electronic device in a recovery state (e.g., Recovery.RcvrCfg state) to change the link speed to the target link speed. When the preset requested by the external electronic device (e.g., the initial preset) is the same as the preset that timed out, the PCIe device can generate a transmission signal based on a second change preset (which is a different initial preset from the requested preset) and send the generated transmission signal to the external electronic device to retry changing the link speed. Here, the PCIe device can select the second change preset from a plurality of presets based on pre-charge memory. Here, the target link speed can represent the link speed intended to be achieved by changing the link speed. As another example, when a second timeout occurs during the equalization process of changing the link speed to the target link speed, the PCIe device can force a return to the detection state of the LTSSM (see [link to LTSSM]). Figure 3The PCIe device can then re-perform link training and gradually increase the link speed to the target link speed via a recovery state. Subsequently, in a recovery state (e.g., Recovery.RcvrCfg state), the PCIe device can receive a preset request signal from an external electronic device to change the link speed to the target link speed. When the preset requested by the external electronic device (e.g., the requested initial preset) differs from the preset that caused the timeout, the PCIe device can generate a transmission signal based on the requested preset (e.g., the requested initial preset), send the generated transmission signal to the external electronic device, and retry changing the link speed. In other words, the PCIe device can use a second preset change to perform equalization again and retry changing the link speed to the target link speed.

[0124] In operation S345, the PCIe device may count the number of retries each time the PCIe device retryes changing the link speed. The PCIe device may store the retry count in memory. To reduce and / or prevent communication performance degradation due to repeated retries, according to some example embodiments, the PCIe device may perform retries to change the link speed within a desired (and / or alternatively, predetermined) number of retries. After counting the retries, the PCIe device may perform operation S310 again (e.g., link training and equalization operations).

[0125] When a timeout occurs during equalization operation, according to some example embodiments, the PCIe device can retry changing the link speed by sending a transmission signal using an initial preset different from the preset that caused the timeout.

[0126] Accordingly, according to some example embodiments, PCIe devices can prevent links from being established at the original link speed (relatively low speed) due to timeouts, and further improve data transmission and / or reception performance between electronic devices based on the changed link speed (relatively high speed).

[0127] Figure 10 This is a block diagram illustrating a memory system with PCIe devices according to some example embodiments.

[0128] refer to Figure 10 System 2000 can essentially include mobile systems such as portable mobile phones, smartphones, tablet PCs, wearable devices, healthcare devices, and Internet of Things (IoT) devices. However, Figure 10 The system 2000 is not necessarily limited to the mobile systems mentioned above, and may include PCs, laptops, servers, media players, automotive equipment (such as navigation units), etc.

[0129] refer to Figure 10The system 2000 may include a main processor 2100, memory 2200a and 2200b and storage devices 2300a and 2300b, and may also include one or more of the following: image capture device 2410, user input device 2420, sensor 2430, communication device 2440, display 2450, speaker 2460, power supply device 2470 and connection interface 2480.

[0130] The main processor 2100 can control all operations of the system 2000, and more specifically, can control the operations of all other components constituting the system 2000. The main processor 2100 can be provided as a general-purpose processor, a special-purpose processor, or an application processor.

[0131] The main processor 2100 may include one or more CPU cores 2110, and may also include a controller 2120 for controlling memories 2200a and 2200b and / or storage devices 2300a and 2300b. According to some example embodiments, the main processor 2100 may also include an accelerator 2130, which includes dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be provided as a separate chip physically independent of other components of the main processor 2100.

[0132] Memory 2200a and 2200b can be used as the main storage device of system 2000 and include volatile memory, such as static random access memory (SRAM) and dynamic random access memory (DRAM). However, memory 2200a and 2200b may also include NVM, such as flash memory, PRAM, MRAM, and resistive random access memory (RRAM). Memory 2200a and 2200b may also be housed in the same package as the main processor 2100.

[0133] Storage devices 2300a and 2300b can be used as non-volatile storage devices, capable of storing data regardless of whether they are powered on, and can have a relatively larger storage capacity than memories 2200a and 2200b. Storage devices 2300a and 2300b may each include storage controllers 2310a and 2310b, and NVMs 2320a and 2320b that store data under the control of storage controllers 2310a and 2310b. NVMs 2320a and 2320b may include flash memory with a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but may also include other types of NVMs such as PRAM and RRAM.

[0134] Storage devices 2300a and 2300b can be housed within system 2000 and physically separated from main processor 2100, or they can be housed in the same package as main processor 2100. Furthermore, storage devices 2300a and 2300b can be configured as SSDs or memory cards, and thus can be detachably connected to other components of system 2000 via an interface (e.g., connection interface 2480 described below). Storage devices 2300a and 2300b may include devices conforming to standard specifications such as UFS, eMMC, and NVMe, but the example embodiments are not limited thereto.

[0135] According to some example embodiments, storage devices 2300a and 2300b may include the above-mentioned references. Figures 1 to 9 PCIe devices described.

[0136] According to some example embodiments, storage devices 2300a and 2300b can initiate the establishment of a link between storage devices 2300a and 2300b and the main processor 2100 (e.g., a host device), and can perform load balancing between the devices to change the link speed between storage devices 2300a and 2300b and the main processor 2100 (e.g., the host device). During load balancing, timeouts in load balancing phase 0 (EQ phase 0) can be identified. When a timeout occurs in EQ phase 0, a change preset request signal can be sent to the main processor 2100 (e.g., the host device) to retry changing the link speed. Here, a timeout in EQ phase 0 can refer to a timeout caused by storage devices 2300a and 2300b failing to receive a signal sent from the main processor 2100 (e.g., the host device) in EQ phase 0.

[0137] In some example embodiments, when a timeout occurs in EQ phase 0, storage devices 2300a and 2300b can count the number of retries each time the link speed is changed, and when the counted number of retries is greater than or equal to a threshold, a link can be established between storage devices 2300a and 2300b and main processor 2100 (e.g., host device) at the link speed before the change.

[0138] In some example embodiments, storage devices 2300a and 2300b can identify whether a timeout occurs in EQ phase 1 during equalization, and when a timeout occurs in EQ phase 1, receive a preset request signal from the main processor 2100 (e.g., a host device), and generate a transmission signal based on a comparison between the preset requested by the preset request signal (e.g., an initial preset) and the preset where the timeout occurred. Storage devices 2300a and 2300b can send the generated transmission signal to the main processor 2100 (e.g., the host device) and retry changing the link speed. Here, the timeout in EQ phase 1 can be caused by the main processor 2100 (e.g., the host device) failing to receive the signal sent from storage devices 2300a and 2300b in EQ phase 1. For example, when the requested preset (e.g., the initial preset) is the same as the preset that caused the timeout, storage devices 2300a and 2300b can send a transmission signal based on a second changed preset to the main processor 2100 (e.g., the host device), which is a different initial preset from the requested preset (e.g., the initial preset), and retry changing the link speed. For example, when the requested preset (e.g., the initial preset) is not the same as the preset that caused the timeout, storage devices 2300a and 2300b can send a transmission signal based on the requested preset (e.g., the initial preset) to the main processor 2100 (e.g., the host device) and retry changing the link speed.

[0139] In some example embodiments, when a timeout occurs in EQ phase 1, storage devices 2300a and 2300b can count the number of retries each time the link speed is changed, and when the counted number of retries is greater than or equal to a threshold, a link can be established between storage devices 2300a and 2300b and main processor 2100 (e.g., host device) at the link speed before the change.

[0140] Image capture device 2410 can capture still images or moving images and includes cameras, video cameras, and / or webcams. However, the example embodiments are not limited thereto.

[0141] User input device 2420 can receive various types of data input by the user of system 2000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0142] Sensor 2430 can sense various types of physical quantities obtained from outside the system 2000 and convert the sensed physical quantities into electrical signals. Sensor 2430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors. However, the example embodiments are not limited thereto.

[0143] Communication device 2440 can transmit signals to and receive signals from other devices outside system 2000 according to various communication protocols. Communication device 2440 may include an antenna, transceiver, and / or modem. However, the example embodiment is not limited thereto.

[0144] The display 2450 and the speaker 2460 can be used as output devices to output visual and auditory information to the user of the system 2000, respectively.

[0145] The power supply device 2470 can appropriately convert the power provided by the built-in battery (not shown) of the system 2000 and / or an external power source, and can provide the converted power to each component of the system 2000.

[0146] Connection interface 2480 provides connectivity between system 2000 and external devices connected to system 2000 to exchange data with system 2000. Connection interface 2480 may be provided in various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCI Fast (PCIe), NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, MMC, eMMC, UFS, Embedded UFS (eUFS), and Compact Flash (CF) card interface. However, the example embodiments are not limited thereto.

[0147] Figure 11 This is a block diagram illustrating an electronic system 1000 with PCIe devices according to some example embodiments.

[0148] exist Figure 11 In the middle, each of PCIe device 1 and PCIe device 2 is connected to Figures 1 to 10 Corresponding to PCIe devices (e.g., 115, 215, and 600). In Figure 11 In this context, electronic device 1100 may represent storage device 200, while external electronic device 1200 may represent host device 100. However, the inventive concept is not limited thereto, and according to some example embodiments, electronic device 1100 may represent host device 100, while external electronic device 1200 may represent storage device 200.

[0149] Figure 11 A system for performing bidirectional communication is shown. (Reference) Figure 11The electronic system 1000 may include an electronic device 1100 and an external electronic device 1200. According to embodiments, each of the electronic devices (e.g., electronic device 1100 and external electronic device 1200) may be implemented as one of a variety of electronic devices, such as a desktop computer, laptop computer, tablet computer, smartphone, wearable device, video game console, home appliance, and medical device. However, the exemplary embodiments are not limited thereto.

[0150] However, the embodiments are not limited thereto. In some example embodiments, the electronic system 1000 may be implemented as a single electronic device. In some example embodiments, each of the electronic devices (e.g., electronic device 1100 and external electronic device 1200) may represent a component or intellectual property (IP) included in the single electronic device, and may also be implemented as a circuit, module, chip, and / or package-level object. The terms "system" and "device" are used for purposes of better understanding and are not intended to limit the embodiments.

[0151] Electronic devices (e.g., electronic device 1100 and external electronic device 1200) can communicate with each other and exchange data / signals via communication channels 1310 and 1320. Each of communication channels 1310 and 1320 may include a conductive material to transmit data / signals. For example, each of communication channels 1310 and 1320 may be formed as a trace pattern on a printed circuit board (PCB), a conductor in a cable, a metal pin / pad in a connector, etc. Figure 11 Communication channels 1310 and 1320 are shown as two unidirectional communication channels 1310 and 1320, but according to some example embodiments, these two unidirectional communication channels 1310 and 1320 can be integrated into a single bidirectional communication channel.

[0152] Electronic device 1100 may include internal circuitry INT1, PCIe device 1, transmitting circuitry TX1, and receiving circuitry RX1, which perform its unique functions. External electronic device 1200 may include internal circuitry INT2, PCIe device 2, transmitting circuitry TX2, and receiving circuitry RX2, which perform its unique functions.

[0153] Internal circuits INT1 and INT2 can operate to provide unique functions for electronic devices (e.g., electronic device 1100 and external electronic device 1200), respectively. For example, internal circuits INT1 and INT2 can constitute various components or IPs, such as processors (e.g., CPU, AP, etc.), memory, image sensors, and displays. However, the example embodiments are not limited thereto.

[0154] Electronic devices (e.g., electronic device 1100 and external electronic device 1200) may be provided as separate components, IP, or devices. Therefore, electronic device 1100 may be represented as an external device in relation to external electronic device 1200, and external electronic device 1200 may be represented as an external device in relation to electronic device 1100.

[0155] Even if a timeout occurs during the equalization process used to change the link speed between electronic devices (e.g., electronic device 1100 and external electronic device 1200), the PCIe devices (PCIe device 1 and PCIe device 2) can change the preset (e.g., the initial preset) to retry changing the link speed, thereby limiting and / or preventing link speed degradation and enabling the electronic devices (e.g., electronic device 1100 and external electronic device 1200) to exchange a large amount of data per unit time.

[0156] Using the above method, even if a timeout occurs during the equalization process, electronic devices (e.g., electronic device 1100 and external electronic device 1200) can still increase the link speed to the target link speed via PCIe devices (PCIe device 1 and PCIe device 2), thereby enabling fast data / signal exchange between electronic devices (e.g., electronic device 1100 and external electronic device 1200).

[0157] One or more of the elements disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; hardware / software combinations such as processors that execute software; or combinations of both. For example, processing circuitry may more specifically include, but is not limited to, central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0158] According to some exemplary embodiments of the present invention, a storage system is provided, comprising: a host device including a host controller, host storage devices connected to the host controller, and host interface circuitry; and a storage device configured to communicate with the host device, the storage device including a storage controller and non-volatile storage devices. The storage controller may include a Peripheral Component Interconnect Fast (PCIe) device, the PCIe device including a plurality of preset storage devices configured to store a plurality of preset storage devices, communication circuitry configured to transmit and receive signals, and a processor. The processor is configured to initiate the establishment of a link between the host device and the storage device, perform a leveling operation between the host device and the storage device to change the link speed between the host device and the storage device, identify whether a timeout occurs during the leveling operation, and re-perform link training and retry changing the link speed based on the occurrence of the timeout.

[0159] According to some exemplary embodiments of the present invention, the PCIe device of the storage controller is configured to establish a link with the host device via a PCIe interface, thereby linking with the host device.

[0160] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a fast PCIe device for peripheral component interconnection in an electronic device, the method comprising: Initiate the establishment of a link between the electronic device and an external electronic device; Perform a leveling operation between the electronic device and the external electronic device to change the link speed between the electronic device and the external electronic device; Identify whether a timeout occurs during the equalization operation; as well as Based on the timeout, re-execute the link training and retry changing the link speed.

2. The operating method according to claim 1, wherein The timeout includes: Based on the first timeout caused by the electronic device failing to receive the signal transmitted from the external electronic device, and A second timeout occurs based on the external electronic device's failure to receive a signal transmitted from the electronic device.

3. The operating method according to claim 2, wherein... Retrying to change the link speed based on the timeout being the first timeout includes: Based on the fact that the link is in a recovery state after re-executing the link training, a signal requesting a first change to the preset value is sent to the external electronic device, and the link speed is retried. The first change preset is different from the preset that causes the timeout.

4. The operating method according to claim 2, wherein Retrying to change the link speed based on the timeout being the first timeout also includes: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to a threshold, the link between the electronic device and the external electronic device is established at the original link speed.

5. The operating method according to claim 2, wherein Retrying to change the link speed based on the timeout being the second timeout includes: Based on the recovery state after re-executing the link training, a preset request signal is received from the external electronic device, and Based on the comparison between the preset requested by the preset request signal and the preset that the timeout occurred, a transmission signal is generated and sent to the external electronic device, and the link speed is retried.

6. The operating method according to claim 5, wherein Retrying to change the link speed also includes: Based on the fact that the requested preset is the same as the preset that caused the timeout and the second change preset is different from the requested preset, a transmission signal is sent to an external electronic device, and the link speed is retried. as well as Based on the fact that the requested preset is different from the preset that caused the timeout, and further based on the requested preset, a transmission signal is sent to the external electronic device, and the link speed is retried to change.

7. The operating method according to claim 2, wherein Retrying to change the link speed based on the timeout being the second timeout includes: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to a threshold, the link between the electronic device and the external electronic device is established at the original link speed.

8. A peripheral component interconnect fast PCIe device for an electronic device, the PCIe device comprising: The storage device is configured to store multiple presets; The communication circuit is configured to transmit and receive signals; as well as processor, The processor is configured as follows: Initiate the establishment of a link between the electronic device and an external electronic device. A leveling operation is performed between the electronic device and the external electronic device to change the link speed between them. Identify whether a timeout occurs during the equalization operation, and Based on the timeout, re-execute the link training and retry changing the link speed.

9. The PCIe device according to claim 8, wherein The timeout includes: Based on the first timeout caused by the electronic device failing to receive the signal transmitted from the external electronic device, and A second timeout occurs based on the external electronic device's failure to receive a signal transmitted from the electronic device.

10. The PCIe device according to claim 9, wherein The processor, based on the timeout being the first timeout, is further configured to: Based on the processor being in a recovery state after re-executing the link training, a signal requesting a first change to the preset value is sent to the external electronic device, and the change to the link speed is retried. The first change preset is different from the preset that causes the timeout.

11. The PCIe device according to claim 9, wherein The processor, based on the timeout being the first timeout, is further configured to: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to a threshold, the link between the electronic device and the external electronic device is established at the original link speed.

12. The PCIe device according to claim 9, wherein The processor, based on the timeout as the second timeout, is also configured to: Based on the fact that the processor is in a recovery state after performing the link training, it receives a preset request signal from the external electronic device, and Based on the comparison result between the preset requested by the preset request signal and the preset that the timeout occurred, a transmission signal is generated and sent to the external electronic device, and the link speed is retried.

13. The PCIe device according to claim 9, wherein The processor, based on a request to retry changing the link speed, is also configured to: Based on the fact that the requested preset is the same as the preset that caused the timeout, and further based on the fact that the second change preset is different from the requested preset, a transmission signal is sent to the external electronic device, and the link speed is retried; and Based on the fact that the requested preset is different from the preset that caused the timeout, and further based on the requested preset, a transmission signal is sent to the external electronic device, and the link speed is retried to change.

14. The PCIe device according to claim 9, wherein The processor is configured to use the second timeout based on the timeout as: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to a threshold, the link between the electronic device and the external electronic device is established at the original link speed.

15. A method of operating a storage device including a peripheral component interconnect (PCIe) device, the method comprising: Initiate the establishment of a link between the storage device and the host device; A load balancing operation is performed between the storage device and the host device to change the link speed between the storage device and the host device; Identify whether a timeout occurs during the equalization EQ phase 0 during the equalization operation; as well as Based on the timeout in the EQ phase 0, after re-executing the link training, a preset request signal for change is sent to the host device, and the link speed is retried.

16. The operating method according to claim 15, wherein, The timeout in EQ phase 0 refers to a timeout caused by the storage device failing to receive a signal sent from the host device during EQ phase 0.

17. The operating method according to claim 16, wherein Changing the link speed based on the timeout retry in EQ phase 0 also includes: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to the threshold, the link between the storage device and the host device is established at the original link speed.

18. The operating method according to claim 15, further comprising: Identify whether a timeout occurs in EQ phase 1 during the equalization operation; Based on the timeout in the EQ phase 1, a preset request signal is received from the host device after the link training is re-executed; A transmission signal is generated based on the comparison result between the preset requested by the preset request signal and the preset that caused the timeout in the EQ phase 1. as well as The generated transmission signal is sent to the host device and the link speed is retried.

19. The operating method according to claim 18, wherein, The timeout in EQ phase 1 refers to a timeout caused by the host device failing to receive a signal sent from the storage device in EQ phase 1.

20. The operating method according to claim 18, wherein Retrying to change the link speed based on a timeout occurring in EQ phase 1 also includes: Each time the link speed is changed during a retry, the number of retries is counted, and Based on the number of retries being greater than or equal to the threshold, the link between the storage device and the host device is established at the original link speed.

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