An asynchronous data transmission method and related components
By pre-storing the data to be transmitted in a register and reading it when a read signal is received, the problem of data bit width limitation in the prior art is solved, flexible asynchronous data transmission is realized, efficiency is improved and costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
Existing asynchronous data transmission methods require the uplink data bit width to be in a fixed integer ratio to the downlink data bit width, and require packing and unpacking, which limits application scenarios and increases latency.
By pre-storing the data to be transmitted in a register and then reading it when a data read signal is received, the read and write clocks do not need to be the same, and the data bit width can be different for each write and read operation, thus using a flexible asynchronous data transmission method.
It improves data transmission efficiency, expands application scenarios, and reduces data transmission costs.
Smart Images
Figure CN122152758A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data transmission, and in particular to an asynchronous data transmission method and related components. Background Technology
[0002] As market demands drive the increasing complexity of system-on-chip (SoC) designs, the number of functional modules integrated onto a single SoC chip inevitably grows, leading to a proliferation of clock signals within the chip. This results in multiple distinct clock domains within the chip. When communication between these different clock domains is required, synchronization is necessary to facilitate cross-clock domain data exchange. Existing asynchronous circuit processing techniques can handle this cross-clock domain asynchronous data transmission. However, this requires a fixed integer ratio between the uplink and downlink data bit widths, as well as packetization and depacketization of the data to be transmitted. Alternatively, a dedicated bit width conversion module can be designed to perform integer bit width conversion. This not only limits the application scenarios for asynchronous data transmission but may also introduce latency during the packetization and depacketization process. Summary of the Invention
[0003] The purpose of this invention is to provide an asynchronous data transmission method and related components. By setting a register to pre-store the data to be transmitted, the data to be read is read when a data read signal is received. The clock between reading and writing data does not need to be the same. Since data is read and written directly in the register, the data to be transmitted can be different each time data is written, and the data bit width of the data to be read can also be different each time data is read. This makes the method more flexible, improves data transmission efficiency, and expands the application scenarios.
[0004] To address the aforementioned technical problems, this invention provides an asynchronous data transmission method, comprising:
[0005] Upon receiving a data write signal, the control write data module writes the data to be transmitted into the register based on the current write data address;
[0006] The current write data address is updated based on the current write data address and the data width of the data to be transmitted, and the updated current write data address is sent to the write data module;
[0007] Upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address;
[0008] The current read data address is updated based on the current read data address and the data width of the data to be read, and the updated current read data address is sent to the read data module.
[0009] Preferably, it further includes:
[0010] The maximum storage capacity of the register is set based on the current write data address and the current read data address. The address depth corresponding to the maximum storage capacity of the register is greater than a preset multiple of the maximum data width between the data width of the data to be transmitted and the data width of the data to be read.
[0011] Preferably, the register is a FIFO (First-In, First-Out) register;
[0012] Upon receiving a data write signal, the control write data module writes the data to be transferred into the register based on the current write data address, including:
[0013] When the data write signal is received, it is determined whether the sum of the current write data address and the data width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register;
[0014] If so, then the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register;
[0015] If not, the write data module is controlled to write the data to be transmitted into the FIFO register according to the current write data address.
[0016] Preferably, upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including:
[0017] Upon receiving the data read signal, determine whether the sum of the current read data address and the data width of the data to be read is greater than the address depth of the FIFO register;
[0018] If so, then the read data module is controlled to read the data to be read from the address depth of the FIFO register according to the current read data address, and then continue to read the data to be read from the minimum storage address of the FIFO register;
[0019] If not, the read data module is controlled to read the data to be read from the FIFO register according to the current read data address.
[0020] Preferably, the highest bit of the data to be transmitted is a preset cycle state bit;
[0021] Upon receiving the data write signal, after determining whether the sum of the current write data address and the data width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the process further includes:
[0022] If so, the preset cycle state bit of the data to be transmitted is inverted.
[0023] After the write data module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, it continues to write the data to be transmitted from the minimum storage address of the FIFO register, including:
[0024] After the write data module writes the data to be transmitted, after inverting the preset loop state bit according to the current write data address, to the address depth of the FIFO register, it continues to write the data to be transmitted from the minimum storage address of the FIFO register.
[0025] If not, the preset cycle state bit of the data to be transmitted remains unchanged, and the process proceeds to the step of controlling the write data module to write the data to be transmitted into the FIFO register according to the current write data address.
[0026] Preferably, controlling the write data module to continue writing the data to be transmitted from the minimum storage address of the FIFO register after writing the data to be transmitted to the address depth of the FIFO register according to the current write data address includes:
[0027] Determine whether the loop status bit of the data to be read corresponding to the current read data address is consistent with the loop status bit of the data to be transmitted corresponding to the current write address;
[0028] If they match, the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register.
[0029] If they are inconsistent, calculate whether the address to be written to the last bit of the data to be transmitted in the FIFO register is less than the current read data address;
[0030] If it is less than the specified value, then the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register.
[0031] If it is not less than, then output a data storage error signal.
[0032] Preferably, upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including:
[0033] Upon receiving the data read signal, the system calculates whether the address of the last bit of the data to be read in the register is less than the current write data address, based on the current read data address and the data width of the data to be read.
[0034] If it is less than the current read address, the control read data module reads the data to be read from the register.
[0035] If the value is not less than the specified value, an abnormal data reading signal will be output.
[0036] To address the aforementioned technical problems, this invention provides an asynchronous data transmission system, comprising:
[0037] The first control unit is used to control the write data module to write the data to be transmitted into the register based on the current write data address when a data write signal is received.
[0038] The first address update unit is used to update the current write data address based on the current write data address and the data width of the data to be transmitted, and send the updated current write data address to the write data module;
[0039] The second control unit is used to control the data reading module to read the data to be read from the register based on the current data reading address when a data reading signal is received;
[0040] The second address update unit is used to update the current read data address based on the current read data address and the data width of the data to be read, and send the updated current read data address to the read data module.
[0041] To address the aforementioned technical problems, the present invention provides an asynchronous data transmission device, comprising:
[0042] Memory, used to store computer programs;
[0043] A processor is used to implement the steps of the asynchronous data transmission method as described above when executing a computer program.
[0044] To address the aforementioned technical problems, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the asynchronous data transmission method described above.
[0045] This application provides an asynchronous data transmission method and related components. Upon receiving a data write signal, the control write module writes the data to be transmitted into a register based on the current write data address, then updates the current write data address and sends it to the write data module. Upon receiving a data read signal, the control read module reads the data to be read from the register based on the current read data address, then updates the current read data address and sends it to the read data module. By pre-storing the data to be transmitted in the register and then reading it upon receiving the data read signal, the clocks for reading and writing data do not need to be the same. Furthermore, since data is read and written directly into the register, the data to be transmitted can be different each time it is written, and the data bit width of the data to be read can also be different each time it is read, making it more flexible, improving data transmission efficiency, and expanding application scenarios. Attached Figure Description
[0046] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 A flowchart illustrating an asynchronous data transmission method provided by the present invention;
[0048] Figure 2 A schematic diagram of the structure of an asynchronous data transmission system provided by the present invention;
[0049] Figure 3 A schematic diagram of the structure of an asynchronous data transmission device provided by the present invention;
[0050] Figure 4 This is a schematic diagram of a computer-readable storage medium provided by the present invention. Detailed Implementation
[0051] The core of this invention is to provide an asynchronous data transmission method and related components. By setting a register to pre-store the data to be transmitted, the data to be read is read when a data read signal is received. The clocks between reading and writing data do not need to be the same. Since data is read and written directly in the register, the data to be transmitted can be different each time data is written, and the data bit width of the data to be read can also be different each time data is read. This makes the method more flexible, improves data transmission efficiency, and expands the application scenarios.
[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0053] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an asynchronous data transmission method provided by the present invention. The method includes:
[0054] S11: Upon receiving a data write signal, the control data write module writes the data to be transmitted into the register based on the current data write address; the data width of the data to be transmitted is the same and / or different each time the data write signal is received;
[0055] In existing technologies, asynchronous data transmission typically requires the uplink data bit width and downlink data bit width to be in a fixed integer ratio, such as an uplink data bit width that is an integer multiple of the downlink data bit width. A bit width conversion module is used to convert the data bit width to achieve data transmission across different clock domains. While this method enables data transmission across different clock domains, the limitations on the uplink and downlink data bit widths restrict its application scenarios. Furthermore, the addition of the bit width conversion module introduces latency during data packing and unpacking, reducing data transmission efficiency.
[0056] To address the aforementioned technical issues, this application incorporates a register. Upon receiving a data write signal, the control write module writes the data to be transmitted into the register based on the current write data address. In other words, the data to be transmitted is pre-stored in the register. Specifically, if the data width of the data to be transmitted is 13 bits, the control write module first writes the first bit of the data to be transmitted into the register based on the current write data address, and then writes the 13 bits of data into the register sequentially, thus completing the pre-storage of the data to be transmitted.
[0057] It should be noted that the data to be transmitted corresponding to each received data write signal can be the same or different. For example, if the width of the data to be transmitted written last time was 11, then the width of the data to be transmitted written this time can be 11 or 13. Of course, this application does not limit this, and the specific width depends on the actual data to be transmitted.
[0058] S12: Update the current write data address based on the current write data address and the data width of the data to be transmitted, and send the updated current write data address to the write data module;
[0059] After the data to be transmitted is stored, in order to facilitate subsequent data transmission, the current write data address is updated based on the current write data address and the data width of the data to be transmitted. For example, if the data width of the data to be transmitted is 13 bits, after writing all 13 bits of data into the register, the current write data address is added to the data width of the data to be transmitted, that is, the sum of the current write data address and 13 is calculated, and the sum is updated to the new current write data address and sent to the write data module. This allows the write data module to use the new current write data address as the storage address of the first bit of the data to be transmitted when it writes the data to be transmitted into the register next time.
[0060] S13: Upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address; the data width of the data to be read is the same and / or different each time the data read signal is received;
[0061] After the data to be transmitted is pre-stored in the register, if a data read signal is received at this time, data reading is required. First, the data read module is controlled to read the data to be read from the register based on the current data read address. Specifically, if the data width of the data to be read is 17 bits, then 17 bits of data are read starting from the current data read address, which is the data to be read. Of course, the data to be read corresponding to each received data read signal can be the same or different. For example, if the data width of the data to be read last time was 11 bits, then the data width of the data to be read this time can be 11 bits or 13 bits. Of course, this application does not limit this; the specific width depends on the actual data to be read.
[0062] S14: Update the current read data address based on the current read data address and the data width of the data to be read, and send the updated current read data address to the read data module.
[0063] After the data to be read is read, in order to facilitate subsequent data reading, the current read data address is updated based on the current read data address and the data width of the data to be read. For example, if the data width of the data to be read is 17 bits, after all 17 bits of data are successfully read from the register, the current read data address is added to the data width of the data to be read, that is, the sum of the current read data address and 17 is calculated, the sum is updated to the new current read data address and sent to the read data module, so that when the read data module reads data from the register next time, it will use the new current read data address as the first bit of the data to be read.
[0064] As can be seen, this application does not limit the data width of the data to be transmitted or the data to be read. The data to be read and the data to be transmitted can have any data width, eliminating the need for data packing or unpacking processing, thus reducing data transmission costs. Specifically, when writing data, the data width written in each clock cycle can be different. For example, the data width of the data to be transmitted in the first clock cycle is 3 bits, while the data width of the data to be transmitted in the second clock cycle is 7 bits, the data width of the data to be transmitted in the third clock cycle is 0 bits, and the data width of the data to be transmitted in the fourth clock cycle is 1 bit. This application does not limit this. Similarly, when reading data, the data width of the data to be read in each clock cycle can also be different. For example, the data width of the data to be read in the first clock cycle is 2 bits, while the data width of the data to be read in the second clock cycle is 5 bits, the data width of the data to be read in the third clock cycle is 1 bit, the data width of the data to be read in the fourth clock cycle is 0 bits, and the data width of the data to be read in the fifth clock cycle is 3 bits. This application does not limit this. This means that not only can the width of the data to be transmitted and the width of the data to be read be different, but the width of the data to be transmitted each time it is written can also be different, and the width of the data to be read each time it is read can also be different. Furthermore, when no data write signal is received, or when the width of the data to be transmitted is 0 bits, the write request is invalid; correspondingly, when no data read signal is received, or when the width of the data to be read is 0 bits, the read request is invalid.
[0065] It should also be noted that when the processor acquires or updates the read data address and the write data address, it can sample the rising edge and the falling edge of the read data address and the write data address respectively to improve the data transmission speed.
[0066] The registers configured in this application allow for faster data reading and writing compared to existing storage media used for storing data packets.
[0067] In summary, this embodiment pre-stores the data to be transmitted in a register and then reads the data when a data read signal is received. The clocks for reading and writing data do not need to be the same. Furthermore, since data is read and written directly in the register, the data to be transmitted can be different each time data is written, and the data bit width of the data to be read can also be different each time data is read. This makes the method more flexible, improves data transmission efficiency, and expands the application scenarios.
[0068] Based on the above embodiments:
[0069] As a preferred embodiment, it also includes:
[0070] The maximum storage capacity of the register is set based on the current write data address and the current read data address. The address depth corresponding to the maximum storage capacity of the register is greater than a preset multiple of the maximum data width between the data width of the data to be transmitted and the data width of the data to be read.
[0071] In this embodiment, when designing the maximum storage capacity that the register can store, the data width of the data to be transmitted and the data width of the data to be read are considered. In other words, in order to facilitate data storage and reading, the maximum data width between the data width of the data to be transmitted and the data width of the data to be read is first determined, and then the maximum storage capacity of the register is set as a preset multiple of the maximum data width, thereby ensuring that the data can be completely read and written when reading or writing data.
[0072] If the width of the data to be transmitted is 13, the width of the data to be read is 17, and the preset multiple is 3, then the maximum data width is 17, and the maximum storage capacity of the register is 17 multiplied by 3, which is 51. Since 51 is the minimum storage capacity required in practice, to provide some redundancy, the pointer width of the write data module and the read data module is 6 bits, so the maximum storage capacity is 2. 6 That is, 64 storage spaces, with the smallest storage address being 000000 and the largest storage address being 111111. Of course, the pointer width can be greater than 6 bits, as long as it meets the minimum storage requirements of actual needs.
[0073] Of course, the actual width of the data to be transmitted is not necessarily 13. For example, the pointer width is 6, and each data bit width in the data to be transmitted is 7, for a total of 53 data bits. Therefore, the data to be transmitted is placed starting from address 4, meaning the minimum address depth for storing the data to be transmitted is 4, and the address depth ranges from 4 to 56, meaning the maximum address depth is 56 (56 < 2). 6 ).
[0074] It should be noted that when determining the maximum storage capacity of the register, the actual design cost must be considered. If the pointer bit width is 6, then the estimated maximum storage capacity of the register is 64. The register address depth can then be set to any integer from 33 to 64. However, choosing an address depth of 33 would waste too many bits, leading to a greater increase in cost. Therefore, the capacity of the register to store data needs to be defined based on the actual requirements of both uplink and downlink data. Furthermore, when the pointer bit width is n, the maximum storage capacity is 2. n That's all.
[0075] As a preferred embodiment, the register is a FIFO (First Input First Output) register;
[0076] Upon receiving a data write signal, the control write data module writes the data to be transferred into the register based on the current write data address, including:
[0077] When a data write signal is received, the write address of the last bit of the data to be transmitted is calculated based on the sum of the current write address and the width of the data to be transmitted, and it is determined whether the write address is greater than the address depth corresponding to the maximum storage capacity of the FIFO register.
[0078] If so, the control write data module will write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register.
[0079] If not, the control write data module writes the data to be transmitted into the FIFO register according to the current write data address.
[0080] In this embodiment, the register is a FIFO register, meaning that data in this register is stored according to a first-in, first-out (FIFO) rule. If, when the control write module writes data to the FIFO register, the address depth of the FIFO register already contains data, the control write module continues writing data starting from the smallest storage address of the FIFO register. For example, if the decimal number of the address depth of the FIFO register is 64, the decimal number of the current write address is 62, the width of the data to be transmitted is 13, and the sum of the current write address and the width of the data to be transmitted is 75, which is greater than 64, then the control write module writes the first bit of the data to be transmitted into the 62nd address space of the FIFO register, the second bit into the 63rd address space, the third bit into the 64th address space, and then writes the fourth bit into the 1st address space, and so on, ensuring the integrity of the pre-stored data to be transmitted and avoiding data loss.
[0081] If the sum of the current write data address and the width of the data to be transmitted is not greater than the address depth of the FIFO register (e.g., the decimal value of the address depth of the FIFO register is 64, the decimal value of the current write data address is 30, the width of the data to be transmitted is 13, and the sum of the current write data address and the width of the data to be transmitted is 43, which is less than 64), then the control write data module can write the data to be transmitted into the FIFO register according to the current write data address.
[0082] In a preferred embodiment, upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including:
[0083] When a data read signal is received, the address to be read for the last bit of the data to be read is calculated based on the sum of the current read data address and the data width of the data to be read, and it is determined whether the address to be read is greater than the address depth of the FIFO register;
[0084] If so, the control read data module will read the data to be read from the address depth of the FIFO register according to the current read data address, and then continue to read the data to be read from the minimum storage address of the FIFO register.
[0085] If not, the control read data module reads the data to be read from the FIFO register according to the current read data address.
[0086] Accordingly, when reading data from the FIFO register, the data to be read is split within the FIFO register. That is, part of the data is stored at the address depth of the FIFO register, and part is stored at the minimum storage address of the FIFO register. The read module is then controlled to read data from the address depth of the FIFO register according to the read address, and then continue reading data from the minimum storage address. For example, if the decimal value of the address depth of the FIFO register is 64, the current read address is 62, the width of the data to be read is 17, and the sum of the current write address and the width of the data to be transmitted is 79, which is greater than 64, then the read module is controlled to read the first bit of data from the 62nd address space of the FIFO register, the second bit from the 63rd address space, the third bit from the 64th address space, and the fourth bit from the 1st address space, and so on, ensuring the integrity of the data to be read and avoiding data loss.
[0087] If the sum of the current read data address and the width of the data to be read is not greater than the address depth of the FIFO register, such as if the address depth of the FIFO register is 51, the current read data address is 30, the width of the data to be read is 17, and the sum of the current read data address and the width of the data to be read is 47, which is less than 51, then the control read data module can read data from the FIFO register according to the current read data address.
[0088] As a preferred embodiment, before determining whether the address to be written is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the method further includes:
[0089] When a data write signal is received, determine whether the current write data address is greater than the current read data address;
[0090] If the current write data address is greater than the current read data address, proceed to the step of determining whether the address to be written is greater than the address depth corresponding to the maximum storage capacity of the FIFO register;
[0091] If the current write data address is not greater than the current read data address, then determine whether the address to be written is less than the current read data address.
[0092] If the address to be written is less than the current read data address, the write data module is controlled to write the data to be transmitted into the FIFO register according to the current write data address;
[0093] If the address to be written is not less than the current read data address, a data storage error signal will be output.
[0094] In this embodiment, when a data write signal is received, if the current write data address is greater than the current read data address (which is before the current read data address), it can be first determined whether the address to be written for the last bit of the data to be transmitted exceeds the address depth of the FIFO register. If it exceeds the address depth, data can be continued to be written from the minimum storage address of the FIFO register. If the current write data address is not greater than the current read data address (which is after the current read data address), it can be first determined whether the address to be written for the last bit of the data to be transmitted is less than the current read data address. If it is less than the current read data address, the data to be transmitted can be written directly. However, if it is not less than the current read data address, writing the data to be transmitted will overwrite the data to be read that has not yet been read, resulting in data loss. Therefore, when the address to be written is less than the current read data address, the data to be transmitted is not written, but a data storage error signal is output so that the upper module knows that the current data to be transmitted cannot be written normally.
[0095] This effectively prevents data from being overwritten before it is read, thus ensuring data integrity.
[0096] In a preferred embodiment, the highest bit of the data to be transmitted is a preset cycle state bit;
[0097] After the write data control module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, and before continuing to write the data to be transmitted from the minimum storage address of the FIFO register, it also includes:
[0098] The inverted address of the last bit of the data to be transmitted is determined based on the difference between the address to be written and the address depth, and it is then determined whether the inverted address to be written is less than the current data read address.
[0099] If the address to be written after inversion is less than the current read data address, then the preset loop state bit of the data to be transmitted is inverted, and the process proceeds to the write data control module. After writing the data to be transmitted to the address depth of the FIFO register according to the current write data address, the process continues to write the data to be transmitted from the minimum storage address of the FIFO register.
[0100] If the address to be written after inversion is not less than the current read data address, then proceed to the step of outputting a data storage error signal.
[0101] In this embodiment, the highest bit of the data to be transmitted is set to a preset loop state bit. If the current write data address is greater than the current read data address, and the address to be written of the last bit of the data to be transmitted exceeds the address depth of the FIFO register, then the data to be transmitted needs to be written to the address depth of the FIFO register before being written from the minimum storage address of the FIFO register.
[0102] Specifically, if the address to be written to the last bit of the data to be transmitted exceeds the address depth of the FIFO register, the direction of the write pointer needs to be changed when writing the data to the FIFO register. That is, the write pointer keeps moving forward as the data is written to the FIFO register, meaning it keeps increasing. However, once the write pointer reaches the address depth, it will start increasing again from the minimum storage address of the FIFO register. If the direction of the write pointer needs to be changed, the difference between the address to be written to the last bit of the data to be transmitted and the address depth of the FIFO register is used to determine the address to be transmitted. The address to be written after inverting the last bit of the data is the address depth at which the data to be transmitted is written in the FIFO register. After writing from the minimum storage address, the address of the last bit of the data to be transmitted in the FIFO register is the address to be written after inversion. If the address to be written after inversion is less than the current read data address, the data to be transmitted will be completely written into the FIFO register without overwriting any unread data. However, if the address to be written after inversion is not less than the current read data address, the data to be transmitted will be completely written into the FIFO register, overwriting any unread data. To avoid data loss, no data is written in this case.
[0103] In a preferred embodiment, the highest bit of the data to be transmitted is a preset cycle state bit;
[0104] Upon receiving a data write signal, after determining whether the sum of the current write data address and the width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the process also includes:
[0105] If so, the preset cycle state bit of the data to be transmitted will be inverted.
[0106] After the write data module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, it continues to write the data to be transmitted from the smallest storage address of the FIFO register, including:
[0107] After the write data module writes the data to be transmitted, after inverting the preset loop state bit according to the current write data address, to the address depth of the FIFO register, it continues to write the data to be transmitted from the minimum storage address of the FIFO register.
[0108] If not, the preset loop state bit of the data to be transmitted remains unchanged, and the process proceeds to the step of controlling the write data module to write the data to be transmitted into the FIFO register according to the current write data address.
[0109] When data has already been written into the address depth of the FIFO register, and the control data writing module continues to write data to be transmitted from the minimum storage address of the FIFO register, in order to avoid data loss due to the data in the FIFO register being overwritten by new data to be transmitted before it is read, the highest bit of the data to be transmitted is set as a preset cycle state bit in this embodiment. If the sum of the current write data address and the width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the preset cycle state bit of the data to be transmitted is first inverted. For example, if the preset cycle state bit of the data to be transmitted was 0 during the last write, then the preset cycle state bit of the data to be transmitted to be written this time is inverted to 1. The preset cycle state bit of the data to be transmitted will also be 1 in subsequent writes until the sum of the previous write data address and the width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register again, at which point the preset cycle state bit of the data to be transmitted is inverted to 0.
[0110] Based on this, it can be determined whether the data to be transmitted written to the FIFO register is split, with one part stored at the tail of the FIFO register, that is, the part close to the address depth, and the other part stored at the head of the FIFO register, that is, the part close to the minimum storage address, in order to avoid data loss.
[0111] It should be noted that if the FIFO register's address depth already contains data, and that data happens to be the last bit of the previously written data to be transmitted, then to write new data to the FIFO register, the preset cycle state bit of the new data to be transmitted needs to be inverted. For example, if the decimal value of the FIFO register's address depth is 64, after the write module writes the data to be transmitted into the FIFO register, the last bit of the data to be transmitted is written into the FIFO register's address depth, and the current write address is updated to 65. When the data write signal is received again, the width of the data to be transmitted is 13. The sum of 65 and 13 is 78, which is greater than 64. At this time, the preset cycle state bit of the data to be transmitted is inverted, and the current write address is switched to 1. The write module is then controlled to write the data to be transmitted from the memory space at address 1 of the FIFO register.
[0112] As a preferred embodiment, after the write data module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, it continues to write the data to be transmitted from the minimum storage address of the FIFO register, including:
[0113] Determine whether the loop status bit of the data to be transmitted corresponding to the current write address is consistent with the loop status bit of the data to be read corresponding to the current read address.
[0114] If they match, the write data module will write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register.
[0115] If they are inconsistent, calculate whether the address to be written to the last bit of the data to be transmitted in the FIFO register is less than the current read data address;
[0116] If it is less than, then the write data module will write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register.
[0117] If it is not less than, then output a data storage error signal.
[0118] When writing data to be transmitted into the FIFO register, to avoid overwriting unread data, in this embodiment, if the loop state bit of the data to be read at the current read address is the same as the loop state bit of the data to be transmitted at the current write address, the data to be transmitted will not be split, even if the data at the smallest storage address of the FIFO register has not yet been read, it will not be overwritten by the data to be transmitted. However, if the loop state bit of the data to be read at the current read address is different from the loop state bit of the data to be transmitted at the current write address, the data to be transmitted will be split, and the data to be transmitted needs to be written to the smallest storage address of the FIFO register. If the last bit of the data to be transferred is at a small storage address, it is necessary to determine whether the data at the smallest storage address of the FIFO register has been read. That is, if the address to be written in the FIFO register for the last bit of the data to be transferred is less than the current read data address, writing the data to be transferred into the FIFO register will not overwrite the unread data. If the address to be written in the FIFO register for the last bit of the data to be transferred is not less than the current read data address, writing the data to the FIFO register for the last bit of the data to be transferred will overwrite the unread data. In this case, the write data module will not write the data to be transferred, but will output a data storage error signal to avoid data loss due to overwriting the unread data.
[0119] It should be noted that if the cycle status bit of the data to be read corresponding to the current read address is consistent with the cycle status bit of the data to be transmitted corresponding to the current write address, then after the control write module writes the data to be transmitted into the FIFO register, the last bit of the data to be transmitted is written to the address depth of the FIFO register. The cycle status bit of the data to be transmitted is inverted when the data write signal is received again, and it is determined whether the cycle status bit of the data to be read corresponding to the current read address is consistent with the cycle status bit of the data to be transmitted corresponding to the current write address, so as to avoid the unread data being overwritten.
[0120] It should also be noted that the updated current read data address and the binary data generated from the current read data address can be converted into Gray code before being transmitted to the write data module or the read data module. Furthermore, when calculating whether the address to be written to the last bit of the data to be transmitted in the FIFO register is less than the current read data address, the calculation can be performed using Gray code data to reduce the possibility of data errors.
[0121] In a preferred embodiment, upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including:
[0122] When a data read signal is received, the system calculates whether the address of the last bit of the data to be read in the register is less than the current write data address, based on the current read data address and the data width of the data to be read.
[0123] If it is less than the current read address, the control read data module reads the data to be read from the register.
[0124] If the value is not less than the specified value, an abnormal data reading signal will be output.
[0125] When reading data, the write data module typically writes the data to be transmitted into the register first, and then the read data module can read the data from the register. However, because the clocks for writing and reading data are different, it is possible that the data to be transmitted has not yet been written when the data read signal is received, which will result in the inability to read the expected data. Therefore, in this embodiment, before controlling the read data module to read the data to be read, the current read data address and the data width of the data to be read are determined. The read address of the last bit of the data to be read in the register is calculated to see if it is less than the current write data address. If it is less, the register still stores unread data, which can be read by the read data module. If it is not less, the register does not store unread data, and the read data module cannot read it. Instead, a data read error signal is output to remind the uplink module to output the corresponding data.
[0126] Please refer to Figure 2 , Figure 2 This invention provides a schematic diagram of an asynchronous data transmission system, which includes:
[0127] The first control unit 21 is used to control the write data module to write the data to be transmitted into the register based on the current write data address when a data write signal is received; the data width of the data to be transmitted is the same and / or different each time a data write signal is received;
[0128] The first address update unit 22 is used to update the current write data address based on the current write data address and the data width of the data to be transmitted, and send the updated current write data address to the write data module;
[0129] The second control unit 23 is used to control the data reading module to read the data to be read from the register based on the current data reading address when a data reading signal is received; the data width of the data to be read is the same and / or different each time a data reading signal is received;
[0130] The second address update unit 24 is used to update the current read data address based on the current read data address and the data width of the data to be read, and send the updated current read data address to the read data module.
[0131] For a description of the asynchronous data transmission system provided by this invention, please refer to the above method embodiments; the invention itself will not be described in detail here.
[0132] Please refer to Figure 3 , Figure 3 This is a schematic diagram of an asynchronous data transmission device provided by the present invention. The device includes:
[0133] Memory 31 is used to store computer programs;
[0134] The processor 32 is configured to implement the steps of the asynchronous data transmission method described above when executing a computer program.
[0135] For a description of the asynchronous data transmission device provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.
[0136] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a computer-readable storage medium provided by the present invention. The computer-readable storage medium 41 stores a computer program 42, which, when executed by the processor 32, implements the steps of the asynchronous data transmission method described above.
[0137] For a description of the computer-readable storage medium 41 provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.
[0138] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0139] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An asynchronous data transmission method, characterized in that, include: Upon receiving a data write signal, the control write data module writes the data to be transmitted into the register based on the current write data address; Each time the data write signal is received, the data width of the data to be transmitted is the same and / or different. The current write data address is updated based on the current write data address and the data width of the data to be transmitted, and the updated current write data address is sent to the write data module; Upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address; Each time the data read signal is received, the data width of the data to be read is the same and / or different; The current read data address is updated based on the current read data address and the data width of the data to be read, and the updated current read data address is sent to the read data module.
2. The asynchronous data transmission method as described in claim 1, characterized in that, Also includes: The maximum storage capacity of the register is set based on the current write data address and the current read data address. The address depth corresponding to the maximum storage capacity of the register is greater than a preset multiple of the maximum data width between the data width of the data to be transmitted and the data width of the data to be read.
3. The asynchronous data transmission method as described in claim 2, characterized in that, The register is a FIFO (First-In-First-Out) register; Upon receiving a data write signal, the control write data module writes the data to be transferred into the register based on the current write data address, including: When the data write signal is received, the write address of the last bit of the data to be transmitted is calculated based on the sum of the current write data address and the data width of the data to be transmitted, and it is determined whether the write address is greater than the address depth corresponding to the maximum storage capacity of the FIFO register. If so, then the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register; If not, the write data module is controlled to write the data to be transmitted into the FIFO register according to the current write data address.
4. The asynchronous data transmission method as described in claim 3, characterized in that, Upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including: Upon receiving the data read signal, the address to be read for the last bit of the data to be read is calculated based on the sum of the current read data address and the data width of the data to be read, and it is determined whether the address to be read is greater than the address depth of the FIFO register; If so, then the read data module is controlled to read the data to be read from the address depth of the FIFO register according to the current read data address, and then continue to read the data to be read from the minimum storage address of the FIFO register; If not, the read data module is controlled to read the data to be read from the FIFO register according to the current read data address.
5. The asynchronous data transmission method as described in claim 3, characterized in that, Before determining whether the address to be written is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the method further includes: When a data write signal is received, it is determined whether the current write data address is greater than the current read data address; If the current write data address is greater than the current read data address, then proceed to the step of determining whether the address to be written is greater than the address depth corresponding to the maximum storage capacity of the FIFO register; If the current write data address is not greater than the current read data address, then determine whether the address to be written is less than the current read data address. If the address to be written is less than the current read data address, then the write data module is controlled to write the data to be transmitted into the FIFO register according to the current write data address; If the address to be written is not less than the current read data address, then a data storage error signal is output.
6. The asynchronous data transmission method as described in claim 5, characterized in that, The highest bit of the data to be transmitted is a preset cycle state bit; Before the write data module continues writing data from the minimum storage address of the FIFO register after writing the data to be transmitted to the address depth of the FIFO register according to the current write data address, the following additional steps are included: The inverted address of the last bit of the data to be transmitted is determined based on the difference between the address to be written and the address depth, and it is determined whether the inverted address to be written is less than the current data read address. If the inverted address to be written is less than the current read data address, then the preset loop state bit of the data to be transmitted is inverted, and the process proceeds to the step of controlling the write data module to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue writing the data to be transmitted from the minimum storage address of the FIFO register. If the inverted address to be written is not less than the current read data address, then proceed to the step of outputting a data storage error signal.
7. The asynchronous data transmission method as described in claim 3, characterized in that, The highest bit of the data to be transmitted is a preset cycle state bit; Upon receiving the data write signal, after determining whether the sum of the current write data address and the data width of the data to be transmitted is greater than the address depth corresponding to the maximum storage capacity of the FIFO register, the process further includes: If so, the preset cycle state bit of the data to be transmitted is inverted. After the write data module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, it continues to write the data to be transmitted from the minimum storage address of the FIFO register, including: After the write data module writes the data to be transmitted, after inverting the preset loop state bit according to the current write data address, to the address depth of the FIFO register, it continues to write the data to be transmitted from the minimum storage address of the FIFO register. If not, the preset cycle state bit of the data to be transmitted remains unchanged, and the process proceeds to the step of controlling the write data module to write the data to be transmitted into the FIFO register according to the current write data address.
8. The asynchronous data transmission method as described in claim 7, characterized in that, After the write data module writes the data to be transmitted to the address depth of the FIFO register according to the current write data address, it continues to write the data to be transmitted from the minimum storage address of the FIFO register, including: Determine whether the loop state bit of the data to be transmitted corresponding to the current write data address is consistent with the loop state bit of the data to be read corresponding to the current read address; If they match, the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register. If they are inconsistent, calculate whether the address to be written to the last bit of the data to be transmitted in the FIFO register is less than the current read data address; If it is less than the specified value, then the write data module is controlled to write the data to be transmitted to the address depth of the FIFO register according to the current write data address, and then continue to write the data to be transmitted from the minimum storage address of the FIFO register. If it is not less than, then output a data storage error signal.
9. The asynchronous data transmission method according to any one of claims 1-8, characterized in that, Upon receiving a data read signal, the control data read module reads the data to be read from the register based on the current data read address, including: Upon receiving the data read signal, the system calculates whether the address of the last bit of the data to be read in the register is less than the current write data address, based on the current read data address and the data width of the data to be read. If it is less than the current read address, the control read data module reads the data to be read from the register. If the value is not less than the specified value, an abnormal data reading signal will be output.
10. An asynchronous data transmission device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the asynchronous data transmission method as described in any one of claims 1-9 when executing a computer program.