Integrated circuit layout optimization method, apparatus, and program product

Abstract

The embodiment of the application is suitable for the field of integrated circuit technology, and provides an integrated circuit layout optimization method, device and program product.The method comprises the following steps: determining density information corresponding to a current layout of an integrated circuit, wherein the integrated circuit comprises a plurality of unit regions, the density information comprises unit densities corresponding to the plurality of unit regions, and the unit density is used to represent the proportion of the effective footprint area of a standard unit in a unit area; determining a high-density region from the plurality of unit regions according to the density information; and performing idle region filling on the high-density region to update the layout of the integrated circuit.Through the above method, the layout of the integrated circuit can be optimized, and the local density of the integrated circuit can be reduced.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to an integrated circuit layout optimization method, equipment and program product. Background Technology

[0002] In the digital back-end physical design process of integrated circuits, placement is the core link connecting logic design and physical implementation. Its quality directly determines the feasibility of subsequent routing, timing convergence efficiency, and final chip yield.

[0003] If the layout of integrated circuits is too dense, it can easily lead to severe compression of metal wiring channels, which not only increases the winding length, but also easily causes physical design rules such as non-compliance with line width and non-compliance with spacing.

[0004] Therefore, the density of integrated circuits needs to be considered during the layout process. Summary of the Invention

[0005] In view of this, embodiments of this application provide an integrated circuit layout optimization method, device, and program product to optimize the integrated circuit layout and avoid excessive local density of integrated circuits.

[0006] The first aspect of this application provides an integrated circuit layout optimization method, including: Determine the density information corresponding to the current layout of the integrated circuit. The integrated circuit includes multiple cell regions. The density information includes the cell density corresponding to the multiple cell regions. The cell density is used to characterize the effective occupied area ratio of standard cells per unit area. Based on the density information, a high-density region is determined from the plurality of unit regions; The high-density areas are filled with empty areas to update the layout of the integrated circuit.

[0007] In one possible implementation, the method further includes: The updated layout is verified, including physical rule verification, temporal analysis verification, and density analysis verification. If the updated layout passes verification, the updated layout will be used as the target layout for the integrated circuit. If the updated layout fails verification, the layout of the integrated circuit will continue to be updated based on the verification results.

[0008] In one possible implementation, the verification of the updated layout includes: Determine the layout information to verify whether the updated layout meets the physical constraints; If the updated layout satisfies the physical constraints, then determine whether the integrated circuit suffers timing degradation after the layout update; If the integrated circuit does not exhibit timing degradation, then the density information of the integrated circuit after layout update is determined; Based on the updated density information, it is determined whether there are high-density regions in the integrated circuit; If there are no high-density areas in the integrated circuit, the updated layout is deemed to have passed verification. If the updated layout violates physical design rules, exhibits temporal degradation, or contains high-density areas, then the updated layout has failed verification.

[0009] In one possible implementation, determining the density information corresponding to the current layout of the integrated circuit includes: A density heatmap of the integrated circuit is generated, which is used to characterize the density information.

[0010] In one possible implementation, determining the high-density region from the plurality of cell regions based on the cell density information includes: The size of the sliding window is determined based on the maximum area of ​​the standard cell in the integrated circuit; Based on the sliding window, the density heatmap is scanned; During the scanning process, the cell density corresponding to the sliding window region is determined; If the cell density corresponding to the sliding window region is greater than a preset threshold, then the sliding window region is determined to be a high-density region.

[0011] In one possible implementation, filling the high-density region with idle areas to update the layout of the integrated circuit includes: The filling strategy is determined based on the cell density of the high-density region; Based on the filling strategy, the high-density area is filled with empty areas.

[0012] In one possible implementation, determining the filling strategy based on the cell density of the high-density region includes: From the high-density region, a first region with a unit density greater than or equal to a first threshold is determined. The filling strategy of the first region is to fill the core region of the first region with a free region of a first size and fill the transition region of the first region with a free region of a second size, wherein the second size is smaller than the first size. From the high-density region, a second region is determined with a unit density less than a first threshold and greater than or equal to a second threshold. The filling strategy for the second region is to fill the surrounding area of ​​the second region with a free area of ​​a second size. From the high-density region, a third region with a cell density less than a second threshold is determined. The filling strategy for the third region is to fill the local positions where the cell spacing is less than the minimum wiring channel width with a free area of ​​a third size, which is smaller than the second size.

[0013] In one possible implementation, filling the high-density region with empty areas based on the filling strategy includes: The target unit in the high-density region is identified, and the target unit includes a power supply unit, a critical timing path unit, and an input / output unit. Based on the filling strategy, the high-density area outside the target unit is filled with empty areas.

[0014] A second aspect of this application provides an integrated circuit layout optimization apparatus, comprising: A density information determination module is used to determine the density information corresponding to the current layout of the integrated circuit. The integrated circuit includes multiple unit regions, and the density information includes the unit density corresponding to the multiple unit regions. The unit density is used to characterize the effective occupied area ratio of standard units within a unit area. A high-density region determination module is used to determine a high-density region from multiple unit regions based on the density information; The idle area filling module is used to fill the idle area in the high-density area to update the layout of the integrated circuit.

[0015] A third aspect of this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the first aspect above.

[0016] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0017] A fifth aspect of this application provides a computer program product that, when run on a computer device, causes the computer device to perform the method described in the first aspect.

[0018] Compared with the prior art, the embodiments of this application have the following advantages: The method described in this application embodiment can optimize the layout of integrated circuits and avoid excessively high local density. A computer device can determine the density information corresponding to the current layout of the integrated circuit, and based on this density information, identify high-density regions from multiple cell regions. The high-density regions are then filled with idle areas to update the integrated circuit layout. By filling high-density regions with idle areas, excessively high local density of the integrated circuit can be avoided, thus optimizing the integrated circuit layout. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0020] Figure 1 This is a flowchart illustrating the steps of an integrated circuit layout optimization method provided in an embodiment of this application; Figure 2 This is a thermal density map of a layout before optimization, provided in an embodiment of this application; Figure 3 This is a layout-optimized heat density map provided in an embodiment of this application; Figure 4 This is a schematic diagram of an integrated circuit layout optimization device provided in an embodiment of this application; Figure 5 This is a schematic diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] In the digital back-end physical design flow of integrated circuits, placement, as the core link connecting logic design and physical implementation, directly determines the feasibility of subsequent routing, timing convergence efficiency, and final chip yield. Cell density, defined as the effective area ratio of standard cells (including logic gates, flip-flops, buffers, etc.) per unit area, is a key quantitative indicator for measuring the rationality of the placement. As semiconductor process nodes continue to evolve to 7nm, 5nm, and below, the functional integration of chips increases exponentially. The cell density in local areas (such as the computing cores of multi-core processors, tensor computing unit arrays of AI chips, and synchronizer clusters of high-speed interfaces) can easily exceed reasonable thresholds, triggering a series of cascading technical problems.

[0023] Firstly, the competition for cabling resources has intensified, and the excessive density of units in some areas has severely squeezed the metal cabling channels. This not only increases the winding length but also easily leads to physical design rule conflicts (DRCs) such as insufficient wire width and non-compliant spacing.

[0024] Secondly, timing performance deteriorates. Excessive winding leads to increased signal delay, while the parasitic capacitance coupling effect of high-density cells is enhanced, which can easily cause setup and hold time violations, seriously affecting the chip's operating frequency.

[0025] Third, manufacturability decreases. Excessively high cell density in certain areas can lead to a smaller lithography process window, increasing the risk of pattern distortion and thus reducing chip yield. In particular, in advanced processes, the yield of areas with a density exceeding 80% can decrease by 20%-30%.

[0026] Current mainstream solutions for optimizing high-density layouts in the industry include: cell rearrangement optimization, density equalization algorithms, and customized cell selection. Cell rearrangement optimization distributes density by adjusting cell placement, but this method is prone to disrupting timing path continuity in multi-clock domain interaction areas. Density equalization algorithms achieve density amortization through global cell migration, but suffer from high computational complexity and long iteration cycles. Customized cell selection uses smaller cells to reduce density, but sacrifices drive capability and increases the difficulty of timing optimization. All of the above methods have significant limitations and struggle to achieve coordinated optimization of density control, timing assurance, and routing feasibility in high-density areas.

[0027] Based on this, this application proposes a three-level digital backend high-density layout optimization method based on cell padding, which consists of density-level identification, adaptive padding, and temporal collaborative verification.

[0028] The technical solution of this application will be described below through specific embodiments.

[0029] Reference Figure 1 The diagram illustrates a step-by-step flowchart of an integrated circuit layout optimization method provided in an embodiment of this application, which may specifically include the following steps: S101, determine the density information corresponding to the current layout of the integrated circuit. The integrated circuit includes multiple cell regions. The density information includes the cell density corresponding to the multiple cell regions. The cell density is used to characterize the effective occupied area ratio of standard cells per unit area.

[0030] The execution subject of this embodiment can be a computer device, which can be a mobile phone, tablet computer, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc. This application does not limit the specific type of computer device.

[0031] In one possible implementation, a computer device can generate a density heatmap of an integrated circuit, which is used to characterize density information.

[0032] For example, a computer device may have Electronic Design Automation (EDA) tools, which can generate density heatmaps to obtain density information. For instance, the computer device can execute the command `report_density_map -detail high` using an EDA tool to generate a high-resolution density heatmap and obtain integrated circuit cell density distribution data.

[0033] S102, based on the density information, determine a high-density region from the plurality of unit regions.

[0034] Computer equipment can identify high-density regions using a sliding window scanning algorithm, outputting key parameters such as region coordinates, area, average density, and maximum density to form a list of high-density regions. The size of the sliding window is determined based on the maximum area of ​​a standard cell in an integrated circuit; a density heatmap is scanned based on the sliding window; during the scanning process, the cell density corresponding to the sliding window region is determined; if the cell density corresponding to the sliding window region is greater than a preset threshold, the sliding window region is determined to be a high-density region.

[0035] In one possible implementation, high-density areas can be divided into different levels. For example, three density thresholds can be pre-defined: a warning threshold (75%), an over-limit threshold (85%), and a danger threshold (90%). Thus, high-density areas can be classified into warning areas, over-limit areas, and danger areas. Computer equipment can identify high-density areas of different levels using a sliding window scanning algorithm, outputting key parameters such as area coordinates, area, average density, and maximum density to form a list of high-density areas.

[0036] In one possible implementation, the computer device can execute an initialization and parameter configuration script: # Load design data (netlist, process library, floorplan, timing constraints) source . / creat_mmmc_view.tcl source . / import_design.tcl # Configure density analysis parameters `set density_window_size` 9# Sliding window size (unit: μm) `set threshold_warning 0.75` sets the warning density threshold (75%). `set threshold_exceed 0.85` sets the threshold for exceeding the density limit (85%). `set threshold_danger 0.90` sets the danger density threshold (90%). `set pad_size_normal 3` sets the pad size (μm) for areas exceeding the normal range. `set pad_size_danger_core 4` sets the core padding size for the danger zone (μm). `set pad_size_danger_trans 3` sets the padding size (μm) for the danger zone transition. `set max_area_increase 0.03` # Maximum allowed area increment (3%) # Save initial design state saveDesign -asimport_design After initialization, the computer can execute a high-density region recognition script to identify high-density regions. The high-density region recognition script can be: # Generate high-precision density heatmaps and reports report_density_map -detail high -file . / density_pre.rpt -format text # Obtain the coordinates of the core region of the map deselectAll set core_box [dbget top.fPlan.coreBox]; # Get the core region coordinates (llx, lly, urx, ury) set box_llx [lindex $core_box 0] # Set the x-coordinate of the bottom left corner set box_lly [lindex $core_box 1] # Set the y-coordinate of the bottom left corner set box_urx [lindex $core_box 2] # Set the x-coordinate of the top right corner set box_ury [lindex $core_box 3] # Top-right y-coordinate # Sliding window scanning to identify high-density areas set exceed_regions [list]# Storage regions exceeding limits (85%-90%) `set danger_regions [list]` # Stores dangerous regions (≥90%) set step $density_window_size # Scan step size equals window size # x-direction scan for {set x $box_llx} {$x<$box_urx} {set x [expr $x + $step]} { # y-direction scan for {set y $box_lly} {$y<$box_ury} {set y [expr $y + $step]} { deselectAll # Select the cells in the current window area gui_select -rect "$x $y [expr $x + $step] [expr $y + $step]" # Get the total area of ​​the selected region set total_area 0 set inst_areas [dbget selected.area] foreach area $inst_areas { set total_area [expr $total_area + $area] # Corrects the original script's error that $b_ar was undefined. } # Calculate the current window density (window area = step × step) set window_area [expr $step * $step] set current_density [expr $total_area / $window_area] # Categorize storage areas by density level if {$current_density>= $threshold_danger} { lappend danger_regions [list $x $y [expr $x + $step] [expr $y + $step]$current_density] } elseif {$current_density>= $threshold_exceed&&$current_density<$threshold_danger} { lappend exceed_regions [list $x $y [expr $x + $step] [expr $y + $step]$current_density] } } } # Output high-density region statistics puts "Identification completed: Quantity of overrun areas (85%-90%):[llength $exceed_regions]" puts "Identification completed: Quantity of hazardous areas (≥90%):[llength $danger_regions]" # Save the region list to a file set region_file [open . / high_density_regions.rpt w] puts $region_file "hazardous areas x1 y1 x2 y2 desity:" foreach region $danger_regions { puts $region_file $region } puts $region_file "overrun areas x1 y1 x2 y2 desity:" foreach region $exceed_regions { puts $region_file $region } close $region_file puts "high desity ares save as . / high_density_regions.rpt" S103, fill the high-density area with empty areas to update the layout of the integrated circuit.

[0037] The aforementioned unused areas can serve as cell isolation zones. That is, cell density can be reduced by adding isolation zones between standard cells in high-density areas.

[0038] In one possible implementation, the fill size can be preset, and during the filling process, a fixed-size isolation zone can be filled for all standard cells in the high-density area.

[0039] In another possible implementation, the computer device can determine a filling strategy based on the cell density of the high-density area; and fill the high-density area with empty areas based on the filling strategy.

[0040] For example, the higher the density of a local area, the larger the size of the fill can be. A computer device can determine a first area from a high-density area where the cell density is greater than or equal to a first threshold. The filling strategy for the first area is to fill the core area of ​​the first area with a free area of ​​a first size, and fill the transition area of ​​the first area with a free area of ​​a second size, which is smaller than the first size. From the high-density area, a second area is determined where the cell density is less than the first threshold but greater than or equal to a second threshold. The filling strategy for the second area is to fill the surrounding area of ​​the second area with a free area of ​​the second size. From the high-density area, a third area is determined where the cell density is less than the second threshold. The filling strategy for the third area is to fill local locations where the cell spacing is less than the minimum wiring channel width with a free area of ​​the third size, which is smaller than the second size.

[0041] For example, for the over-limit threshold (85%-90%) area, a standard fill size of 3μm can be used; for the danger threshold (≥90%) area, a gradient fill strategy can be used, with a fill size of 4μm in the core area and a fill size of 3μm in the outer transition area; for the warning threshold (75%-85%) area, only local positions where the cell spacing is less than the minimum wiring channel width are micro-filled with 1-2μm.

[0042] During the filling process, some cells may be left unfilled to avoid disrupting timing or violating physical design rules. The computer device can identify target cells in high-density areas, including power supply cells, critical timing path cells, and input / output cells; based on the filling strategy, the high-density areas outside the target cells are filled with empty areas.

[0043] For example, filling areas can avoid power / ground rings (P / G rings), critical timing path units (such as clock buffers, flip-flops), and I / O interface units; filling blank areas can preserve metal wiring paths to ensure that subsequent wiring resources are available; for multi-clock domain units, the clock signal isolation distance needs to be increased during filling to reduce clock crosstalk.

[0044] In one possible implementation, the computer device can execute an adaptive fill script to perform the fill operation. The adaptive fill script can be: # Define the fill function (Input: region coordinates, fill size, Output: fill success indicator) proc fill_padding {x1 y1 x2 y2 pad_size} { deselectAll # Select the target area cells and exclude power / ground cells and critical timing cells. set target_cells [get_cells -area "$x1 $y1 $x2 $y2" -filter {ref_name!~ "*PG*"&&is_clock_cell == 0}] if {[llength $target_cells] == 0} { puts "Warning: No qualified filling units exist in the area($x1,$y1)-($x2,$y2" return 0 } # Execute the fill command if {[catch {specifyInstPad $target_cells $pad_size} err_msg]} { puts "Warning: area($x1,$y1)-($x2,$y2)Fill failed Filling failed :$err_msg" return 0 } puts "successful:The area($x1,$y1)-($x2,$y2)is filled with $pad_size\mu m, involving the number of cells :[llength $target_cells]" return 1 } # Prioritize handling hazardous areas (core area 4μm + transition area 3μm) foreach region $danger_regions { set x1 [lindex $region 0] set y1 [lindex $region 1] set x2 [lindex $region 2] set y2 [lindex $region 3] set density [lindex $region 4] # 4μm filling of the core area (center 50%) of the hazardous zone set core_x1 [expr $x1 + ($x2 - $x1)*0.25] set core_y1 [expr $y1 + ($y2 - $y1)*0.25] set core_x2 [expr $x1 + ($x2 - $x1)*0.75] set core_y2 [expr $y1 + ($y2 - $y1)*0.75] fill_padding $core_x1 $core_y1 $core_x2 $core_y2 $pad_size_danger_core # 3μm filling in the transition zone of the danger zone (outside the core area) # Upper Transition Zone fill_padding $x1 $core_y2 $x2 $y2 $pad_size_danger_trans # Lower Transition Zone fill_padding $x1 $y1 $x2 $core_y1 $pad_size_danger_trans # Left transition zone (excluding upper and lower transition zones) fill_padding $x1 $core_y1 $core_x1 $core_y2 $pad_size_danger_trans # Right transition zone (excluding upper and lower transition zones) fill_padding $core_x2 $core_y1 $x2 $core_y2 $pad_size_danger_trans } # Handling out-of-limit regions (3μm fill) foreach region $exceed_regions { set x1 [lindex $region 0] set y1 [lindex $region 1] set x2 [lindex $region 2] set y2 [lindex $region 3] fill_padding $x1 $y1 $x2 $y2 $pad_size_normal } # Save the design state after filling save_design . / design_padded After the filling is completed, a new layout of the integrated circuit can be obtained. This new layout can be verified to ensure the performance of the integrated circuit. In one possible implementation, the computer device can perform physical rule verification, timing analysis verification, and density analysis verification on the updated layout. If the updated layout passes the verification, it is used as the target layout of the integrated circuit. If the updated layout fails the verification, the layout of the integrated circuit is updated again based on the verification results.

[0045] During verification, the computer equipment determines the layout information to verify whether the updated layout meets the physical constraints. If the updated layout meets the physical constraints, it determines whether the integrated circuit has timing degradation after the layout update. If the integrated circuit does not have timing degradation, it determines the density information of the integrated circuit after the layout update. Based on the updated density information, it determines whether there are high-density regions in the integrated circuit. If there are no high-density regions in the integrated circuit, the updated layout is determined to pass the verification. If the updated layout violates the physical design rules, has timing degradation, or has high-density regions, the updated layout is determined to fail the verification.

[0046] During density analysis verification, the computer equipment can regenerate the density heat map through EDA, check whether the unit density of the target area is less than the preset threshold, and at the same time, count the change in the average density of the whole chip to ensure that the overall area increase does not exceed the preset value, such as 3%.

[0047] When performing timing analysis verification, the computer device executes the timing analysis command (report_timing -max_paths 20) to compare the timing margin of the critical path before and after filling. If timing degradation occurs, such as an increase in the absolute value of WNS, the filling size is adjusted or the filling position is optimized.

[0048] During physical rule verification, the computer device can perform a physical rule check (verify_drc), focusing on whether new physical constraint violations have occurred around the filled area. For cases where verification fails, the density threshold and filling parameters are iteratively adjusted until all indicators meet the standards.

[0049] The computer equipment can execute verification and iteration scripts to perform iterative optimization of integrated circuits, wherein the verification and iteration scripts may include: # Density Verification report_density_map -detail high -file . / density_post.rpt -format text set post_max_density [dbget top.density.max] puts "Maximum Local Density after Optimization Post-OptimizationMaximum Local Density:$post_max_density" # Area Verification set init_area [dbget top.area -design . / design_init.enc] set post_area [dbget top.area] set area_increase [expr ($post_area - $init_area) / $init_area] puts "Initial Core Region Area:$init_area μm²,Optimized Core AreaCore Area After Optimization:$post_area μm²,Area increment Area increase:[expr $area_increase*100]%" # Timing verification report_timing -max_paths 20 -delay max -nworst 5 -file . / timing_max_post.rpt report_timing -max_paths 20 -delay min -nworst 5 -file . / timing_min_post.rpt set wns_post [dbget timing.wns] puts "WNS:$wns_post ns" # DRC verification verify_drc -ignore default -check spacing -check width -file . / drc_post.rpt set drc_count [dbget drc.count] puts "DRC num:$drc_count" # Iterative judgment if {$post_max_density>$threshold_exceed || $area_increase>$max_area_increase || $wns_post<0 || $drc_count>20} { puts "Validation failed, iteration and optimization are required" # Output iterative suggestions if {$post_max_density>$threshold_exceed} { puts "Iteration suggestion: Increase the filler size in the over-limit area by 0.5 μm" } if {$area_increase>$max_area_increase} { puts "Iteration suggestion: reduce the filler size of the hazardousarea transition zone by 1 μm" } if {$wns_post<0} { puts "Iteration suggestion: Optimize the fill parameters of units around the critical timing paths" } if {$drc_count>20} { puts "Iteration suggestion: Adjust the padding position to avoid DRCviolation areas" } } else { puts "Verification passed, optimization goal achieved!" save_design . / design_final_verification puts "design final save as: . / design_final_verification" } To better illustrate this solution, embodiments of this application provide... Figure 2 and Figure 3 To make a comparison, Figure 2 This is a thermal density map of a layout before optimization, provided in an embodiment of this application; Figure 3 This is a layout-optimized thermal density map provided in an embodiment of this application. Figure 2The integrated circuit area shown is a typical multi-module interactive core area, integrating synchronizers for three clock domains, cross-module handshake logic units, state machine circuits with superimposed control signals, and surrounding SRAM read / write control logic modules. The concentrated arrangement of multiple functional units leads to a surge in both cell density and trace density in this area. The heat map shows that the highest density reaches 0.877 (i.e., 87.7%), far exceeding the industry-standard 80% safe density threshold, directly facing multiple risks such as trace congestion, timing violations (Setup / Hold), physical rule conflicts (DRC), and decreased chip yield.

[0050] like Figure 3 As shown, after filling the empty areas, the heatmap shows that the highest density reaches 0.778, and the cell density of the integrated circuit decreases significantly.

[0051] This embodiment provides a hierarchical density identification mechanism, employing a combination of three-level density threshold calibration and sliding window scanning to accurately locate high-density regions at different levels. This avoids the overfilling or underfilling problems caused by traditional single-threshold identification, providing a precise region positioning foundation for adaptive filling. The filling size is dynamically adjusted based on the region's density level. Critical areas use a gradient filling approach of "core area + transition area," while areas exceeding limits use standard filling. A cell type screening mechanism is also incorporated to avoid critical cells, achieving synergy between density control and timing assurance. This solves the area waste or timing degradation problems caused by traditional fixed-size filling. A full-process verification mechanism encompassing density, timing, and physical constraints is constructed. Combined with area constraint indicators, a closed-loop iterative optimization process is formed to ensure comprehensive achievement of optimization results, improving the method's practicality and reliability. This makes it suitable for extended applications across different process nodes and design scenarios.

[0052] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0053] Reference Figure 4 The diagram illustrates an integrated circuit layout optimization device according to an embodiment of this application, which may specifically include a density information determination module 41, a high-density region determination module 42, and a free space filling module 43, wherein: Density information determination module 41 is used to determine the density information corresponding to the current layout of the integrated circuit. The integrated circuit includes multiple unit regions, and the density information includes the unit density corresponding to the multiple unit regions. The unit density is used to characterize the effective occupied area ratio of the standard unit within a unit area. The high-density region determination module 42 is used to determine a high-density region from the plurality of unit regions based on the density information; The idle area filling module 43 is used to fill the idle area in the high-density area to update the layout of the integrated circuit.

[0054] In one possible implementation, the method further includes: The updated layout is verified, including physical rule verification, temporal analysis verification, and density analysis verification. If the updated layout passes verification, the updated layout will be used as the target layout for the integrated circuit. If the updated layout fails verification, the layout of the integrated circuit will continue to be updated based on the verification results.

[0055] In one possible implementation, the verification of the updated layout includes: Determine the layout information to verify whether the updated layout meets the physical constraints; If the updated layout satisfies the physical constraints, then determine whether the integrated circuit suffers timing degradation after the layout update; If the integrated circuit does not exhibit timing degradation, then the density information of the integrated circuit after layout update is determined; Based on the updated density information, it is determined whether there are high-density regions in the integrated circuit; If there are no high-density areas in the integrated circuit, the updated layout is deemed to have passed verification. If the updated layout violates physical design rules, exhibits temporal degradation, or contains high-density areas, then the updated layout has failed verification.

[0056] In one possible implementation, determining the density information corresponding to the current layout of the integrated circuit includes: A density heatmap of the integrated circuit is generated, which is used to characterize the density information.

[0057] In one possible implementation, determining the high-density region from the plurality of cell regions based on the cell density information includes: The size of the sliding window is determined based on the maximum area of ​​the standard cell in the integrated circuit; Based on the sliding window, the density heatmap is scanned; During the scanning process, the cell density corresponding to the sliding window region is determined; If the cell density corresponding to the sliding window region is greater than a preset threshold, then the sliding window region is determined to be a high-density region.

[0058] In one possible implementation, filling the high-density region with idle areas to update the layout of the integrated circuit includes: The filling strategy is determined based on the cell density of the high-density region; Based on the filling strategy, the high-density area is filled with empty areas.

[0059] In one possible implementation, determining the filling strategy based on the cell density of the high-density region includes: From the high-density region, a first region with a unit density greater than or equal to a first threshold is determined. The filling strategy of the first region is to fill the core region of the first region with a free region of a first size and fill the transition region of the first region with a free region of a second size, wherein the second size is smaller than the first size. From the high-density region, a second region is determined with a unit density less than a first threshold and greater than or equal to a second threshold. The filling strategy for the second region is to fill the surrounding area of ​​the second region with a free area of ​​a second size. From the high-density region, a third region with a cell density less than a second threshold is determined. The filling strategy for the third region is to fill the local positions where the cell spacing is less than the minimum wiring channel width with a free area of ​​a third size, which is smaller than the second size.

[0060] In one possible implementation, filling the high-density region with empty areas based on the filling strategy includes: The target unit in the high-density region is identified, and the target unit includes a power supply unit, a critical timing path unit, and an input / output unit. Based on the filling strategy, the high-density area outside the target unit is filled with empty areas.

[0061] As the apparatus embodiments are basically similar to the method embodiments, they are described in a relatively simple manner. For relevant details, please refer to the description in the method embodiment section.

[0062] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Figure 5 As shown, the computer device 5 of this embodiment includes: at least one processor 50 ( Figure 5 (Only one is shown in the diagram), memory 51, and computer program 52 stored in said memory 51 and executable on said at least one processor 50, wherein said processor 50 executes said computer program 52 to implement the steps in any of the above method embodiments.

[0063] The computer device 5 may be a desktop computer, laptop, handheld computer, or cloud computing device, etc. This computer device may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will understand that... Figure 5The computer device 5 is merely an example and does not constitute a limitation on the computer device 5. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0064] The processor 50 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0065] In some embodiments, the memory 51 may be an internal storage unit of the computer device 5, such as a hard disk or memory of the computer device 5. In other embodiments, the memory 51 may be an external storage device of the computer device 5, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device 5. Furthermore, the memory 51 may include both internal and external storage units of the computer device 5. The memory 51 is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0066] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0067] This application provides a computer program product that, when run on a computer device, enables the computer device to perform the steps described in the above-described method embodiments.

[0068] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An integrated circuit layout optimization method, characterized in that, include: Determine the density information corresponding to the current layout of the integrated circuit. The integrated circuit includes multiple cell regions. The density information includes the cell density corresponding to the multiple cell regions. The cell density is used to characterize the effective occupied area ratio of standard cells per unit area. Based on the density information, a high-density region is determined from the plurality of unit regions; The high-density areas are filled with empty areas to update the layout of the integrated circuit.

2. The method as described in claim 1, characterized in that, The method further includes: The updated layout is verified, including physical rule verification, temporal analysis verification, and density analysis verification. If the updated layout passes verification, the updated layout will be used as the target layout for the integrated circuit. If the updated layout fails verification, the layout of the integrated circuit will continue to be updated based on the verification results.

3. The method as described in claim 2, characterized in that, The verification of the updated layout includes: Determine the layout information to verify whether the updated layout meets the physical constraints; If the updated layout satisfies the physical constraints, then determine whether the integrated circuit suffers timing degradation after the layout update; If the integrated circuit does not exhibit timing degradation, then the density information of the integrated circuit after layout update is determined; Based on the updated density information, it is determined whether there are high-density regions in the integrated circuit; If there are no high-density areas in the integrated circuit, the updated layout is deemed to have passed verification. If the updated layout violates physical design rules, exhibits temporal degradation, or contains high-density areas, then the updated layout has failed verification.

4. The method according to any one of claims 1-3, characterized in that, Determining the density information corresponding to the current layout of the integrated circuit includes: A density heatmap of the integrated circuit is generated, which is used to characterize the density information.

5. The method as described in claim 4, characterized in that, The step of determining a high-density region from multiple cell regions based on the cell density information includes: The size of the sliding window is determined based on the maximum area of ​​the standard cell in the integrated circuit; Based on the sliding window, the density heatmap is scanned; During the scanning process, the cell density corresponding to the sliding window region is determined; If the cell density corresponding to the sliding window region is greater than a preset threshold, then the sliding window region is determined to be a high-density region.

6. The method according to any one of claims 1-3 or 5, characterized in that, The step of filling the high-density region with empty areas to update the layout of the integrated circuit includes: The filling strategy is determined based on the cell density of the high-density region; Based on the filling strategy, the high-density area is filled with empty areas.

7. The method as described in claim 6, characterized in that, The step of determining the filling strategy based on the cell density of the high-density region includes: From the high-density region, a first region with a unit density greater than or equal to a first threshold is determined. The filling strategy of the first region is to fill the core region of the first region with a free region of a first size and fill the transition region of the first region with a free region of a second size, wherein the second size is smaller than the first size. From the high-density region, a second region is determined with a unit density less than a first threshold and greater than or equal to a second threshold. The filling strategy for the second region is to fill the surrounding area of ​​the second region with a free area of ​​a second size. From the high-density region, a third region with a cell density less than a second threshold is determined. The filling strategy for the third region is to fill the local positions where the cell spacing is less than the minimum wiring channel width with a free area of ​​a third size, which is smaller than the second size.

8. The method as described in claim 6, characterized in that, The filling of empty areas in the high-density area based on the filling strategy includes: The target unit in the high-density region is identified, and the target unit includes a power supply unit, a critical timing path unit, and an input / output unit. Based on the filling strategy, the high-density area outside the target unit is filled with empty areas.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-8.

10. A computer program product, characterized in that, When the computer program product is executed by a processor, it implements the method as described in any one of claims 1-8.

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