A simulation method and device for metal surface deposition morphology and a readable storage medium

Abstract

The application relates to a metal surface deposition morphology simulation method, device and readable storage medium, which comprises the following steps: obtaining an electrochemical deposition simulation model, adding a correction factor to an array height calculation formula in the electrochemical deposition simulation model, obtaining a correction factor coefficient through parameter iteration calibration, obtaining a correction array height calculation formula, obtaining a correction electrochemical deposition simulation model, obtaining layout extraction information after grid division of a chip to be simulated, and determining a target grid area of the simulation chip; based on the correction electrochemical deposition simulation model, electrochemical deposition simulation is carried out by using the layout extraction information of the target grid area, and an electrochemical deposition simulation result of the target grid area is generated. The metal surface deposition morphology simulation method effectively improves the simulation speed based on the electrochemical deposition morphology generation method of pure numerical calculation, and provides model correction for special areas with unexpected simulation results, so that the model prediction effect is ensured.

Description

Technical Field

[0001] This invention belongs to the field of chip surface terrain simulation technology, and particularly relates to a simulation method, apparatus and readable storage medium for metal surface deposition morphology. Background Technology

[0002] In semiconductor manufacturing processes, particularly in the simulation of electrochemical deposition (ECD) processes for copper / tungsten interconnects, a long-standing challenge has been achieving rapid prediction of the entire chip-level topography while maintaining accuracy. Traditional time-step-based iterative physical simulation methods (such as the Euler method and explicit iterative scheme) require multiple small time steps to simulate the gradual deposition process of materials. Each step involves complex physicochemical calculations, resulting in a huge computational load and significant time consumption in full-chip-scale simulation scenarios. Analysis reveals that this traditional approach has limitations and drawbacks in simulation speed, especially in meeting the urgent need of modern chip design for fast and accurate ECD simulation of areas with small linewidths and spacings.

[0003] Existing time-step iterative physical simulation methods still rely on simulating the physical behavior of actual deposition processes. They require dynamically selecting different computational models based on varying trench morphologies (conformal, superfill, overfill) (e.g., switching models using equivalent density methods for shrinkage or elongation), and indirectly solving for the morphology by balancing the "actual deposition volume" and "equivalent deposition volume." This process is essentially an implicit, physically-based iterative and judgmental process, rather than direct computation. Its computational overhead increases significantly with the complexity of process steps and the diversity of graphics. Simultaneously, the method needs to determine the filling mode and select the corresponding computational path for each window, with conditional judgments and branch selection introducing additional computational overhead. For the numerous small-linewidth, small-spacing regions with diverse graphic characteristics present in the layout, this accumulated overhead is significant, preventing the simulation speed from reaching its ideal optimal level.

[0004] In summary, although existing physical simulation methods offer significant speed improvements over traditional iterative simulations, they are essentially "fast simulations" based on physical process simulations rather than efficient and rapid mathematical calculations. While these methods achieve high simulation accuracy, the excessively long simulation time remains a pain point and challenge for such methods. Summary of the Invention

[0005] To address all or part of the problems of the prior art, this invention provides a simulation method, apparatus, and readable storage medium for metal surface deposition morphology that can significantly improve simulation speed while ensuring simulation accuracy.

[0006] Firstly, this embodiment provides a method for simulating the deposition morphology of a metal surface, including: Obtain an electrochemical deposition simulation model, including the array height (AH) calculation formula; A correction factor is added to the array height calculation formula, and the factor coefficients are obtained through parameter iteration calibration to obtain the corrected array height calculation formula; thus, a corrected electrochemical deposition simulation model including the corrected array height calculation formula is obtained. Obtain the layout information of the chip to be simulated after mesh generation; Based on preset screening criteria, the target mesh region of the simulation chip is determined; Based on the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the layout information of the target grid region, generating the electrochemical deposition simulation results of the target grid region.

[0007] In some embodiments, determining the target mesh region of the simulation chip based on preset filtering conditions includes: Select regions with small line widths and / or small line spacings as target grid regions; The extracted layout information includes line width and line spacing; The small linewidth region refers to a grid region where the linewidth is less than a preset linewidth threshold; the small line spacing region refers to a grid region where the line spacing is less than a preset line spacing threshold.

[0008] In some embodiments, adding a correction factor to the array height calculation formula includes: Obtain a sample dataset, including simulation data obtained by simulating the sample chip using the electrochemical deposition simulation model, and measurement data after electrochemical deposition; Based on preset screening criteria, the target region of the sample chip is determined; Based on the simulation data and measurement data, the compensation value of the target area is obtained; A lower-order term is added as a correction factor to the array height calculation formula to introduce compensation data; the compensation data and the compensation value are within a preset error range.

[0009] In some embodiments, obtaining the factorization coefficients through parameter iteration calibration to obtain the corrected array height calculation formula includes: Obtain at least one factor coefficient to be calibrated, including the factor coefficient of the correction factor; Obtain the preset parameter range of the factor coefficients; The sample dataset also includes layout extraction information of the sample chips; Based on the at least one factorization coefficient to be calibrated, a set of random numbers is generated in each iteration. An array height calculation formula is constructed according to the random numbers, and simulation results are obtained by performing simulation using the layout extraction information of the sample chip. Based on the simulation results and measurement data of the sample chip, deviation data is generated. The deviation data affects the generation of random numbers in the next iteration until a set of random numbers generated in the current iteration meets the preset iteration stop condition. The random numbers of the current iteration are used as the factorization coefficient to obtain a corrected array height calculation formula.

[0010] In some embodiments, the deviation data affecting the generation of random numbers in the next iteration includes: After at least two iterations, the deviation data (current_error) of the previous iteration and the deviation data (new_error) of the current iteration are obtained and compared: If the deviation data of the current iteration is less than the deviation data of the previous iteration (new_error < current_error), a set of random numbers generated in the current iteration is updated as the parameter basis. If the deviation data of the current iteration is not less than the deviation data of the previous iteration (new_error ≥ current_error), based on the current temperature, it is determined whether to update a set of random numbers generated in the current iteration as the parameter basis or not. Wherein, the current temperature is determined based on a preset initial value and a cooling rate; In the next iteration, based on the parameter basis, a set of random numbers is generated after adding random perturbations.

[0011] In some embodiments, the determining whether to update a set of random numbers generated in the current iteration as the parameter basis or not based on the current temperature includes: The current temperature is currT; Calculate the difference delta_energy between the deviation data of the current iteration and the deviation data of the previous iteration; Obtain a random number realDistTmp that follows a uniform distribution and takes values in [0, 1]; If e (-delta_energy / currT) > realDistTmp, a set of random numbers generated in the current iteration is updated as the parameter basis, otherwise the parameter basis is not updated.

[0012] In some embodiments, the current temperature being determined based on a preset initial value and a cooling rate includes: Obtain the preset initial value and the cooling rate; Let the current temperature be the initial value; After each iteration, the current temperature is updated based on the cooling rate.

[0013] In some embodiments, the set of random numbers generated in the current iteration meets a preset stopping iteration condition, including: The iteration stops when the current temperature is lower than a preset threshold or when the current iteration reaches the maximum number of iterations.

[0014] In some embodiments, the step of adding a correction factor to the array height calculation formula, obtaining the factor coefficients through parameter iteration calibration, and obtaining the corrected array height calculation formula further includes: Information is extracted from the layout of the sample chip, and simulation is performed based on the corrected array height calculation formula to obtain simulation data; Set an objective function (Evaluation Function) to assess the difference between the simulation data and the measurement data after electrochemical deposition of the sample chip, and determine whether the difference meets a preset difference threshold: If satisfied, the construction of the modified array height calculation formula is complete; If the conditions are not met, the system will adjust at least one of the following parameters: the initial value of the current temperature, the cooling rate, the random disturbance, and the preset parameter range of the factor coefficient. Then, the factor coefficient will be re-calibrated through parameter iteration.

[0015] In some embodiments, the simulation method for the deposition morphology of the metal surface further includes: Based on the electrochemical deposition simulation model and / or the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the extracted information of the remaining grid region to generate electrochemical deposition simulation results for the remaining grid region; wherein, the remaining grid region refers to the remaining grid region after filtering out the target grid region in the chip layout; The electrochemical deposition simulation results, including the target grid region and the remaining grid region, are obtained to complete the electrochemical deposition simulation of the chip to be simulated, and the metal surface deposition morphology characterization data, including the target grid region and the remaining grid region, are obtained.

[0016] Secondly, this embodiment provides a simulation device for metal surface deposition morphology, the device comprising: The acquisition module is used to acquire the electrochemical deposition simulation model, including the array height (AH) calculation formula; and to acquire the layout extraction information of the chip to be simulated after meshing. The correction module is used to add a correction factor to the array height calculation formula, obtain the factor coefficients through parameter iteration calibration, and obtain the corrected array height calculation formula; thus, a corrected electrochemical deposition simulation model including the corrected array height calculation formula is obtained. A filtering module is used to determine the target mesh region of the simulation chip based on preset filtering conditions; The simulation module is used to perform electrochemical deposition simulation based on the modified electrochemical deposition simulation model, using the layout information of the target grid region to generate the electrochemical deposition simulation results of the target grid region.

[0017] Thirdly, this embodiment provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the simulation method for metal surface deposition morphology described in the first aspect above.

[0018] The aforementioned simulation method for metal surface deposition morphology provides an electrochemical deposition morphology generation method based on pure numerical calculation, effectively improving simulation speed and providing strong support for subsequent CMP grinding and polishing simulation. It also provides model correction for specific areas where simulation results are not as expected, thereby ensuring the model's predictive effectiveness and guiding improvements in wafer manufacturing yield. Furthermore, a simulation device and a computer-readable storage medium for metal surface deposition morphology are disclosed, both possessing the performance and beneficial effects of the aforementioned simulation method. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a simulation method for the deposition morphology of a metal surface in one embodiment; Figure 2 This is a schematic diagram of the surface topography of electrochemical deposition in one embodiment; Figure 3 A comparison of function curves before and after adding a low-order term to the array height calculation formula in one embodiment; Figure 4 This is a schematic diagram of parameter iterative calibration of factor coefficients in one embodiment; Detailed Implementation

[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0023] It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0024] To significantly improve simulation speed while maintaining the accuracy of electrochemical deposition simulation, this embodiment provides a method such as... Figure 1 The simulation method for the deposition morphology of the metal surface shown includes: Obtain an electrochemical deposition simulation model, including the array height (AH) calculation formula; A correction factor is added to the array height calculation formula, and the factor coefficients are obtained through parameter iteration calibration to obtain the corrected array height calculation formula; thus, a corrected electrochemical deposition simulation model including the corrected array height calculation formula is obtained. Obtain the layout information of the chip to be simulated after mesh generation; Based on preset screening criteria, the target mesh region of the simulation chip is determined; Based on the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the layout information of the target grid region, generating the electrochemical deposition simulation results of the target grid region.

[0025] The above-mentioned simulation method for metal surface deposition morphology provides an electrochemical deposition morphology generation method based on pure numerical calculation, which effectively improves the simulation speed, provides strong support for subsequent CMP grinding and polishing simulation, and provides model correction for special areas where the simulation results are not as expected, thereby ensuring the model prediction effect and guiding the improvement of wafer manufacturing yield.

[0026] In this embodiment, determining the target mesh region of the simulation chip based on preset screening conditions includes: Select regions with small line widths and / or small line spacings as target grid regions; The extracted layout information includes line width and line spacing; The small linewidth region refers to a grid region where the linewidth is less than a preset linewidth threshold; the small line spacing region refers to a grid region where the line spacing is less than a preset line spacing threshold.

[0027] In chemical mechanical polishing (CMP) modeling, electrochemical deposition (ECD) models are often used as preliminary models to describe the deposition height or equivalent deposition behavior of metals under different linewidths (w) and pattern densities. The ECD model uses a multinomial inverse power function of the linewidth (w) to characterize the influence of micro-geometry on the electrochemical deposition rate and deposition uniformity.

[0028] As process nodes advance to 28nm or even more advanced, the minimum linewidth becomes smaller and smaller, causing the ECD model formula (electrochemical deposition simulation model) to no longer be applicable at small linewidths / small line spacings, resulting in extremely poor simulation effects.

[0029] Specifically, the ECD model used includes the array height (AH) calculation formula, where the electrochemical deposition surface topography can be referenced. Figure 2 : Where w represents the linewidth (in some embodiments, it can also represent the equivalent feature size), s represents the line spacing, and AH is defined as the array height of the deposition morphology; a A The factor parameter representing the first-order linewidth, b A The factor parameter representing the negative first-order linewidth, c A The factorial parameter representing the negative second-order linewidth, d A The factorial parameter representing the first-order line spacing, e A The factor parameter C that characterizes the product of the first-order line width and the line spacing. A The compensation term characterizes the result of array height calculation.

[0030] In the above AH calculation formula, each term w -1 w -2 w -3 The term w is used to describe edge effects, diffusion confinement, and electric field concentration effects; the first-order linear term w is used to describe macroscopic trend correction; and the constant term C... A Used for global offset correction.

[0031] In some other embodiments, the ECD model used also includes a formula for calculating the step height (SH): SH is defined as the step height of the sedimentary morphology; in the above formula for calculating SH, a S The factor parameter representing the first-order linewidth, b S The factor parameter representing the negative first-order linewidth, c S The factorial parameter representing the second-order linewidth, d S The factorial parameter representing the first-order line spacing, e S The factor parameter C that characterizes the product of the first-order line width and the line spacing. SThe compensation term characterizes the calculation result of the step height.

[0032] At small linewidths (such as submicron linewidths), the smallest order is only w. -2 This results in insufficient conformal filling height at the deposition point, and inadequate model constraint on extremely small linewidth regions. This can easily lead to excessive divergence in simulation values, causing the deposition height to be significantly overestimated or underestimated. Consequently, simulation results fall short of expectations, leading to deviations in process hotspot detection. This hinders process engineers from identifying manufacturing problems and ultimately impacts wafer manufacturing yield. The same applies to areas with small line spacing. Therefore, this embodiment provides ECD model correction to ensure the model's predictive effectiveness and guide improvements in wafer manufacturing yield.

[0033] In this embodiment, regions with a linewidth of less than 0.2 μm and a line spacing of less than 0.1 μm are selected as target mesh regions for the electrochemical deposition simulation model that need to be corrected. However, in other embodiments, the regions with small linewidths and small line spacings can be customized based on the specific application scenario requirements. This application does not impose any specific limitations.

[0034] It should be noted that this embodiment only provides a formula for calculating the array height (AH) and the step height (SH) in a specific application scenario. Other formulas for calculating the array height (AH) and the step height (SH) can also be provided based on other application scenario requirements. This application does not impose any specific limitations.

[0035] In this embodiment, adding a correction factor to the array height calculation formula includes: Obtain a sample dataset, including simulation data obtained by simulating the sample chip using the electrochemical deposition simulation model, and measurement data after electrochemical deposition; Based on preset screening criteria, the target region of the sample chip is determined; Based on the simulation data and measurement data, the compensation value of the target area is obtained; A lower-order term is added as a correction factor to the array height calculation formula to introduce compensation data; the compensation data and the compensation value are within a preset error range.

[0036] In existing simulation models, considering actual model performance, the array height calculation formula shows significant discrepancies between the calculated results and real chip data at small linewidths and spacings. Therefore, some special judgments are needed to ensure a high degree of matching between the calculated results and the real chip values. However, excessive special judgments are extremely detrimental to the model's generalization and scalability. Therefore, rather than adding special judgments (such as directly handling some abnormal data in the code and specifying a preset data to replace it to solve the problem of some simulation data being too outrageous), it is more necessary to modify the electrochemical deposition simulation model based on actual performance.

[0037] At very small linewidths (extremely small linewidths), higher-order negative terms of w dominate, which can capture physical phenomena with rapidly increasing nonlinearity. In actual parameter optimization, simulation results of AH observed at linewidths <0.1µm often have a data error >500Å compared to the true data. In existing array height calculation formulas, to compensate for such a large data error, other parameter terms (such as b)... A and d A Either the value needs to be maximized or reduced to a negative value, which would negatively impact the simulation results in other regions. Therefore, a lower-order, higher-order inverse power modulation term w is introduced. -3 This term provides a steeper correction, matching the experimentally observed abnormally low values ​​(d). A <0) or high value (d) A By setting the parameter value to >0, all parameter combinations can be balanced, thereby better completing the parameter optimization process, finding better simulation results, and enhancing the model's numerical suppression capability and physical rationality in regions with small line widths / small line spacings.

[0038] The formula for calculating the array height (AH) after adding the correction factor is as follows: Where w represents the line width, s represents the line spacing, and a A The factor parameter representing the first-order linewidth, b A The factor parameter representing the negative first-order linewidth, c A The factorial parameter representing the negative second-order linewidth, d A The factorial parameter representing the negative 3rd order line spacing, e A The factorial parameter f that characterizes the first-order line spacing A The factor parameter C that characterizes the product of the first-order line width and the line spacing. A The compensation term characterizes the result of array height calculation.

[0039] A low-order term d was added to the array height calculation formula. A w -3 This is to obtain a smoother function curve, resulting in better simulation results. For example... Figure 3Given the optimal parameter values ​​for proportional scaling, the effect of adding lower-order terms on the function curve of the array height calculation formula is shown. It can be observed that at the point where the independent variable is minimal, the calculation result shows an inverse. From... Figure 3 As can be seen, at the minimum values ​​of the independent variable such as line width (w) of 0.19µm, the calculation results will exhibit significant anomalies if the aforementioned lower-order term is not introduced for factor correction. This means that at small line widths and / or small line spacings, the phenomenon of abnormally large AH ​​values ​​can be effectively alleviated by adding a lower-order term with a coefficient less than 0; conversely, if the optimal parameter value is the opposite of the current parameter, adding this lower-order term with a coefficient greater than 0 can also improve the phenomenon of abnormally small AH values.

[0040] In this embodiment, obtaining the factor coefficients through parameter iterative calibration to obtain the corrected array height calculation formula includes: Obtain at least one factor coefficient to be calibrated, including the factor coefficient of the correction factor; Obtain the preset parameter range of the factor coefficients; The sample dataset also includes layout extraction information of the sample chips; Based on the at least one factor coefficient to be calibrated, a set of random numbers is generated in each iteration. An array height calculation formula is constructed based on the random numbers, and simulation results are obtained by extracting information from the layout of the sample chip. Based on the simulation results and measurement data of the sample chip, deviation data is generated; The deviation data affects the generation of random numbers in the next iteration until a set of random numbers generated in the current iteration meets the preset stopping iteration condition. The random numbers of the current iteration are used as factor coefficients to obtain the formula for calculating the corrected array height.

[0041] Specifically, a A b A c A d A e A f A C A The parameter values ​​of these factor coefficients are uniquely determined by the automatic parameter calibration algorithm (parameter iterative calibration) in ECD and CMP simulation tools.

[0042] After obtaining the preset parameter range of the factor coefficients, the automatic parameter calibration algorithm generates a set of random numbers in each iteration. The simulation results obtained by building the model based on these random numbers (based on the information extracted from the layout in the sample dataset) guide the direction of the next random number generation (based on the simulation results and the measurement data in the sample dataset to generate deviation data, and based on the deviation data to realize the influence).

[0043] In this embodiment, the deviation data affects the random number generation in the next iteration, including: After at least two iterations, obtain the deviation data (current_error) of the previous iteration and the deviation data (new_error) of the current iteration, and compare them: If the deviation data of the current iteration is less than the deviation data of the previous iteration (new_error < current_error), update a set of random numbers generated in the current iteration as the parameter basis; If the deviation data of the current iteration is not less than the deviation data of the previous iteration (new_error ≥ current_error), based on the current temperature currT, determine whether to update a set of random numbers generated in the current iteration as the parameter basis or not; Among them, the current temperature currT is determined based on a preset initial value and a cooling rate; In the next iteration, based on the parameter basis, generate a set of random numbers after adding random perturbations.

[0044] In this embodiment, the determining whether to update a set of random numbers generated in the current iteration as the parameter basis or not based on the current temperature includes: The current temperature is currT; Calculate the difference delta_energy between the deviation data of the current iteration and the deviation data of the previous iteration; Obtain a random number realDistTmp that follows a uniform distribution and takes values in [0, 1]; If e (-delta_energy / currT) > realDistTmp, update a set of random numbers generated in the current iteration as the parameter basis, otherwise do not update the parameter basis.

[0045] Specifically, in order to avoid falling into the local optimum situation such as Figure 4 in the parameter iteration calibration and calibrate to obtain the ideal global optimum situation, this embodiment uses the simulated annealing algorithm to implement. In each iteration: within the given parameter range, randomly generate a new parameter combination by adding a small random perturbation to the current parameter basis.

[0046] Calculate the deviation data (current_error) of the previous iteration and the deviation data (new_error) of the current iteration, compare new_error and current_error, and decide whether to accept the new parameter combination, that is, whether to update a set of random numbers generated in the current iteration as the parameter basis: If new_error < current_error, accept the new parameter combination; If new_error ≥ current_error, accept the new parameter combination with a certain probability, which is determined by the current temperature currT. The calculation formula is: delta_energy = new_error - current_error; realDistTmp = X ~ U(0, 1), that is, obtain a random number uniformly distributed between 0 and 1, that is, the probability of taking any number is exactly the same; If e (-delta_energy / currT) > realDistTmp, then accept the new parameter combination and update it as the parameter basis; otherwise, reject the update of the parameter basis.

[0047] In this embodiment, the current temperature currT is determined based on a preset initial value and a cooling rate, including: Obtain the preset initial value (Tmax) and cooling rate (Tk); Set the current temperature currT as the initial value; After each iteration, update the current temperature currT based on the cooling rate.

[0048] The temperature (Tmax) and cooling rate (Tk) are preset. These parameters belong to hyperparameters and can only be set before calibration and cannot be adjusted during the calibration process.

[0049] The cooling rate affects the value of the temperature drop after each iteration. The calculation formula is currT （i+1） = currT i * T k , where i represents the number of iterations; for example, if currT1 = Tmax = 100, Tk = 0.7, then currT2 = 70, currT3 = 49, currT4 = 35,...

[0050] In this embodiment, the set of random numbers generated in the current iteration meets the preset iteration stop condition, including: When the current temperature currT is lower than the preset threshold or the current iteration reaches the maximum number of iterations, stop the iteration.

[0051] The lower the temperature, the smaller the range of random numbers generated in each iteration. When the temperature is low enough, each parameter stops fluctuating, and the iteration ends, similar to the end of metal annealing, where the annealing process ends when the metal cools to a solid state. Furthermore, as the number of iterations reaches a certain threshold, the temperature also decreases accordingly. Therefore, reaching the maximum number of iterations can also be used as a condition for stopping iteration.

[0052] In this embodiment, the step of adding a correction factor to the array height calculation formula, obtaining the factor coefficients through parameter iteration calibration, and obtaining the corrected array height calculation formula further includes: Information is extracted from the layout of the sample chip, and simulation is performed based on the corrected array height calculation formula to obtain simulation data; Set an objective function (Evaluation Function) to assess the difference between the simulation data and the measurement data after electrochemical deposition of the sample chip, and determine whether the difference meets a preset difference threshold: If satisfied, the construction of the modified array height calculation formula is completed, that is, all parameters (factor coefficients) of the modified array height calculation formula are completely determined, thereby determining the model and completing the entire modeling process; If the conditions are not met, the initial value of the current temperature currT and the cooling rate T will be adjusted accordingly. k After obtaining at least one parameter from the preset parameter range of random disturbances and factor coefficients, the factor coefficients are obtained again through parameter iteration calibration.

[0053] Within a grid, a set of parameters uniquely determines an AH simulation result. This result can be high or low, or positive or negative. Compared to AH data obtained from actual chip measurements, the sole criterion for judging the quality of the AH value is whether it closely matches the measured AH data. An objective function, Evaluation_Function, is defined to calculate the difference between the simulation result and the actual measurement data under the current parameter combination. In this embodiment, the root mean square error (RMSE) is chosen as the objective function; the closer this value is to 0, the smaller the difference between the two. A preset difference threshold is set; when the RMSE does not meet the threshold, the parameters can be adjusted and the factor coefficients recalibrated.

[0054] Through the above steps, the simulated annealing algorithm can automatically calibrate parameter a. A b A c A Etc., to make the RMSE value as low as possible, that is, to make the simulation results as close as possible to the actual measurement data.

[0055] In this embodiment, the simulation method for the deposition morphology of the metal surface further includes: Based on the electrochemical deposition simulation model and / or the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the extracted information of the remaining grid region to generate electrochemical deposition simulation results for the remaining grid region; wherein, the remaining grid region refers to the remaining grid region after filtering out the target grid region in the chip layout; The electrochemical deposition simulation results, including the target grid region and the remaining grid region, are obtained to complete the electrochemical deposition simulation of the chip to be simulated, and the metal surface deposition morphology characterization data, including the target grid region and the remaining grid region, are obtained.

[0056] In practical applications, when determining the simulation structure of the remaining grid region based on the needs of the application scenario, this application does not make specific limitations on whether to use the electrochemical deposition simulation model or the modified electrochemical deposition simulation model.

[0057] The simulation method for metal surface deposition morphology provided in this embodiment determines the form of the correction term through residual analysis and adds a low-order term to the AH formula; then, it determines the coefficient of the correction term through an automatic parameter calibration algorithm, thereby improving the abnormally low values ​​at small linewidths by multiplying the correction term by the correction term coefficient, thus ensuring the prediction effect of the physical model at this point, and further guiding the improvement of wafer manufacturing yield.

[0058] The following specific application example illustrates the construction process of the modified electrochemical deposition simulation model in the above-mentioned simulation method for metal surface deposition morphology.

[0059] The formula for calculating array height after adding the correction factor can be expressed as: Among them, a A ,b A ,c A ,e A ,f A C A For the parameter to be calibrated, d A w -3 The new modulation factor introduced, namely a A ,b A ,c A ,d A ,e A ,f A C A These are the factor coefficients to be determined through parameter iteration calibration.

[0060] During the parameter (factor coefficient) determination process, the model parameters are automatically calibrated using a heuristic optimization algorithm. The specific process is as follows: 1) Data acquisition; By using a wafer test structure, the actual electrochemical deposition thickness or equivalent deposition response is measured under different linewidths and pattern densities to form a calibration dataset.

[0061] 2) Construction of the objective function; Construct an objective function to measure the error between model predictions and experimental measurements, such as using weighted root mean square error (RMSE): Among these, samples with small linewidths have a relatively high weighting, accounting for approximately 20% of the total data. Therefore, the model's fitting ability in this region is crucial and significantly impacts the calibration results. Here, J represents the weighted root mean square error, and w... i ω represents the frequency (in Hz) of the i-th sample point. i AH(w) represents the weight coefficient of the i-th sample point (samples with smaller line widths are given higher weights; note that this symbol is omega, not the w mentioned earlier). i ) indicates that the model is in w i The predicted value at AH meas (w i ) indicates at frequency w i The experimental measurements at the specified locations. This objective function, by weighting and summing the prediction errors at each frequency point, focuses the optimization process more on the fitting accuracy in areas with small linewidths, thereby improving the model's calibration performance in key regions.

[0062] 3) Heuristic search and automatic calibration; The parameter search is performed using the simulated annealing algorithm: Randomly initialize the parameter set; Random perturbations are applied within the parameter space; Accept or reject new solutions based on the Metropolis criterion; As the annealing temperature gradually decreases, it converges to the global or quasi-global optimal solution.

[0063] 4) Parameter convergence and model determination; When the objective function converges or the termination condition is met, the final parameter set is output, and the automatic model calibration is completed.

[0064] Through the above process, stable model parameters can be determined automatically without human intervention.

[0065] Using simulated annealing, an automatic parameter calibration process for the ECD model was performed using a ground truth dataset. After 20,000 iterations, the optimal model parameters returned are shown in Table 1 below. In Table 1, Model_Type indicates that the model to which this parameter belongs is BEOL_ECD (ECD model); Parameter indicates the parameter to be determined (factor coefficient), where a_A, b_A, c_A, d_A, e_A, f_A, C_A represent a A ,b A ,c A ,d A ,e A ,f A C A Begin and End represent the two endpoints of the preset parameter range for this parameter; Best represents the optimal parameter value determined by this parameter.

[0066] Table 1 Parameter Table of Optimal ECD Model Rounded to two decimal places, this model can be used to calculate... Figure 3 The AH2 baseline curve is shown.

[0067] The truth table shows that the measurement point AH at the grid point with a linewidth w=0.21µm is 9.965 Å, while the simulated value before introducing lower-order terms is 75.31 Å, and the simulated value after introducing lower-order terms is 7.38 Å. The simulation results demonstrate that introducing lower-order terms can significantly improve the simulation accuracy in regions with small linewidths / spacings, providing strong support for improving the reliability of the model.

[0068] Based on the same inventive concept, this application also provides an apparatus for implementing the simulation method for the metal surface deposition morphology described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the metal surface deposition morphology simulation apparatus provided below can be found in the limitations of the simulation method for metal surface deposition morphology described above, and will not be repeated here.

[0069] In one embodiment, a simulation apparatus for metal surface deposition morphology is provided, the apparatus comprising: The acquisition module is used to acquire the electrochemical deposition simulation model, including the array height calculation formula and the step height calculation formula; and to acquire the layout extraction information of the chip to be simulated after meshing. The correction module is used to add a correction factor to the array height calculation formula, obtain the factor coefficients through parameter iteration calibration, and obtain the corrected array height calculation formula; thus, a corrected electrochemical deposition simulation model including the corrected array height calculation formula and the step height calculation formula is obtained. A filtering module is used to determine the target mesh region of the simulation chip based on preset filtering conditions; The simulation module is used to perform electrochemical deposition simulation based on the modified electrochemical deposition simulation model, using the layout information of the target grid region to generate the electrochemical deposition simulation results of the target grid region.

[0070] The functional modules of this metal surface deposition morphology simulation device implement the steps in the above-described embodiments of the simulation methods for metal surface deposition morphology.

[0071] Each module in the aforementioned simulation device for metal surface deposition morphology can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0072] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above embodiments of the simulation method for metal surface deposition morphology.

[0073] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0074] In one embodiment, a test chip is provided, which is designed and generated using the steps in the above embodiments of the test chip design method based on failure models.

[0075] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0076] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for simulating the deposition morphology of a metal surface, characterized in that, include: Obtain an electrochemical deposition simulation model, including the array height calculation formula; A correction factor is added to the array height calculation formula. A lower-order term is set as a correction factor and added to the array height calculation formula. Compensation data is introduced, and the factor coefficients are obtained through parameter iteration calibration to obtain the corrected array height calculation formula. A corrected electrochemical deposition simulation model including the corrected array height calculation formula is obtained. Obtain the layout information of the chip to be simulated after mesh generation; Based on preset screening criteria, the target mesh region of the simulation chip is determined; Based on the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the layout extraction information of the target grid region, and the electrochemical deposition simulation results of the target grid region are generated. The step of obtaining factor coefficients through parameter iteration calibration to obtain the corrected array height calculation formula includes: Obtain at least one factor coefficient to be calibrated, including the factor coefficient of the correction factor; Obtain the preset parameter range of the factor coefficients; Obtain the sample dataset, including simulation data obtained by simulating the sample chip using the electrochemical deposition simulation model, measurement data after electrochemical deposition, and layout extraction information of the sample chip; Based on the at least one factor coefficient to be calibrated, a set of random numbers is generated in each iteration. An array height calculation formula is constructed based on the random numbers, and simulation results are obtained by extracting information from the layout of the sample chip. Based on the simulation results and measurement data of the sample chip, deviation data is generated; The deviation data affects the generation of random numbers in the next iteration until a set of random numbers generated in the current iteration meets the preset stopping iteration condition. The random numbers of the current iteration are used as factor coefficients to obtain the formula for calculating the corrected array height.

2. The simulation method for metal surface deposition morphology according to claim 1, characterized in that, The determination of the target mesh region of the simulation chip based on preset screening conditions includes: Select regions with small line widths and / or small line spacings as target grid regions; The extracted layout information includes line width and line spacing; The small linewidth region refers to a grid region where the linewidth is less than a preset linewidth threshold; the small line spacing region refers to a grid region where the line spacing is less than a preset line spacing threshold.

3. The simulation method for metal surface deposition morphology according to claim 2, characterized in that, Adding a correction factor to the array height calculation formula includes: Based on preset screening criteria, the target region of the sample chip is determined; Based on the simulation data and measurement data, the compensation value of the target area is obtained; The compensation data and the compensation value are within a preset error range.

4. The simulation method for metal surface deposition morphology according to claim 1, characterized in that, The deviation data affects the generation of random numbers in the next iteration, including: After at least two iterations, obtain the deviation data from the previous iteration and the deviation data from the current iteration, and compare them: If the deviation data of the current iteration is less than the deviation data of the previous iteration, then update the parameter base with a set of random numbers generated in the current iteration; If the deviation data of the current iteration is not less than the deviation data of the previous iteration, then based on the current temperature, determine whether to update the parameter base with a set of random numbers generated in the current iteration or not update the parameter base. The current temperature is determined based on a preset initial value and a cooling rate; In the next iteration, a set of random numbers is generated by adding random perturbations based on the parameters.

5. The simulation method for metal surface deposition morphology according to claim 4, characterized in that, The step of determining whether to update the parameter base with the set of random numbers generated in the current iteration or not, based on the current temperature, includes: The current temperature is currT; Calculate the difference delta_energy between the deviation data of the current iteration and the deviation data of the previous iteration; Get a random number realDistTmp that takes values ​​in the range [0, 1] and follows a uniform distribution. If e (-delta_energy / currT) If `realDistTmp` is used, the set of random numbers generated in the current iteration will be updated to the parameter base; otherwise, the parameter base will not be updated.

6. The simulation method for metal surface deposition morphology according to claim 4, characterized in that, The current temperature is determined based on a preset initial value and cooling rate, including: Obtain the preset initial values ​​and cooldown rate; Let the current temperature be the initial value; After each iteration, the current temperature is updated based on the cooling rate.

7. The simulation method for metal surface deposition morphology according to claim 6, characterized in that, The set of random numbers generated in the current iteration meets the preset stopping iteration conditions, including: The iteration stops when the current temperature is lower than a preset threshold or when the current iteration reaches the maximum number of iterations.

8. The simulation method for metal surface deposition morphology according to claim 4, characterized in that, The step of adding a correction factor to the array height calculation formula and obtaining the factor coefficients through parameter iteration calibration to obtain the corrected array height calculation formula further includes: Information is extracted from the layout of the sample chip, and simulation is performed based on the corrected array height calculation formula to obtain simulation data; An objective function is set to evaluate the degree of difference between the simulation data and the measurement data after electrochemical deposition of the sample chip, and to determine whether the degree of difference meets a preset difference threshold. If satisfied, the construction of the modified array height calculation formula is complete; If the conditions are not met, the system will adjust at least one of the following parameters: the initial value of the current temperature, the cooling rate, the random disturbance, and the preset parameter range of the factor coefficient. Then, the factor coefficient will be re-calibrated through parameter iteration.

9. The simulation method for metal surface deposition morphology according to claim 1, characterized in that, Also includes: Based on the electrochemical deposition simulation model and / or the modified electrochemical deposition simulation model, electrochemical deposition simulation is performed using the extracted information of the remaining grid region to generate electrochemical deposition simulation results for the remaining grid region; wherein, the remaining grid region refers to the remaining grid region after filtering out the target grid region in the chip layout; The electrochemical deposition simulation results, including the target grid region and the remaining grid region, are obtained to complete the electrochemical deposition simulation of the chip to be simulated, and the metal surface deposition morphology characterization data, including the target grid region and the remaining grid region, are obtained.

10. A simulation device for metal surface deposition morphology, characterized in that, The device includes: The acquisition module is used to acquire the electrochemical deposition simulation model, including the array height calculation formula; and to acquire the layout extraction information of the chip to be simulated after meshing. The correction module is used to add a correction factor to the array height calculation formula, setting a lower-order term as a correction factor to the array height calculation formula, introducing compensation data, obtaining factor coefficients through parameter iteration calibration, and obtaining a corrected array height calculation formula; thus obtaining a corrected electrochemical deposition simulation model including the corrected array height calculation formula; the step of obtaining factor coefficients through parameter iteration calibration to obtain the corrected array height calculation formula includes: acquiring at least one factor coefficient to be calibrated, including the factor coefficient of the correction factor; acquiring a preset parameter range for the factor coefficient; and acquiring a sample dataset, including a sample chip using the electrochemical deposition simulation model. The simulation data obtained from the true model simulation, the measurement data after electrochemical deposition, and the layout extraction information of the sample chip are used. Based on the at least one factor coefficient to be calibrated, a set of random numbers is generated in each iteration. The array height calculation formula is constructed according to the random numbers, and the simulation results are obtained by using the layout extraction information of the sample chip. Based on the simulation results and measurement data of the sample chip, deviation data is generated. The deviation data affects the generation of random numbers in the next iteration until the set of random numbers generated in the current iteration meets the preset stopping iteration condition. The random numbers of the current iteration are used as factor coefficients to obtain the corrected array height calculation formula. A filtering module is used to determine the target mesh region of the simulation chip based on preset filtering conditions; The simulation module is used to perform electrochemical deposition simulation based on the modified electrochemical deposition simulation model, using the layout information of the target grid region to generate the electrochemical deposition simulation results of the target grid region.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the simulation method for the metal surface deposition morphology as described in any one of claims 1 to 9.

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