基于存内索引的多层感知机高能效存内计算方法及装置
By generating lookup tables in the multilayer perceptron model and utilizing on-chip memory for dynamic loading and concurrent multi-address caching, the contradiction between low power consumption and high throughput in the traditional von Neumann architecture is resolved, achieving efficient multilayer perceptron computation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-05-09
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies struggle to simultaneously achieve low power consumption and high throughput in multilayer perceptron computing within the traditional von Neumann architecture. In particular, the computational efficiency of the MLP layer in the Transformer architecture is low, leading to difficulties in edge deployment.
By extracting the weight parameters of the multilayer perceptron model to generate a lookup table and dynamically loading it using on-chip memory, combined with multi-address concurrent cache and hierarchical reduction circuit, single-cycle multi-address parallel access and deep overlap of computation and memory access are achieved, replacing traditional multiplier operations.
It significantly reduces the dynamic power consumption of the multiplier, improves the efficiency of weight acquisition, and achieves high throughput computation with extremely low power consumption, effectively balancing the needs of low power consumption and high throughput.
Smart Images
Figure CN122154795B_ABST