A method and system for compiling optimization of general circuits in distributed quantum computing

Abstract

The application provides a kind of distributed quantum computing general circuit compilation optimization method and system, it is related to quantum computing technical field, this method includes: the block division of magic state perception is carried out to general quantum circuit, and circuit is divided into several basic blocks with T gate as the segmentation point;Each basic block is iteratively simplified based on ZX calculus, and the number of T gates in the block is compressed;Distributed quantum computing architecture model with magic state factory is constructed;Magic state distribution and remote gate operation are double-layer collaborative scheduling, and the scheduling scheme is solved based on multi-commodity flow model;The block-level quasi-parallel execution is realized through the extended quasi-parallel determination rule;Finally, the final result is output after merging correction information and completing the classical post-processing. The quasi-parallel optimization of distributed compilation is extended from Clifford circuit to general quantum circuit containing non-Clifford gate in the application, the collaborative scheduling of magic state and entanglement link resources is realized, and the execution efficiency and resource utilization of distributed quantum computing are improved.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a compilation optimization method and system that supports general circuits in distributed quantum computing containing non-Clifford gates. Background Technology

[0002] Quantum computing is a novel computing model that manipulates quantum information units according to the laws of quantum mechanics. It possesses the potential for exponential speedup in specific problems such as large number factorization, quantum chemical simulation, and combinatorial optimization, a potential unmatched by classical computing. Currently, the development of quantum computing hardware is limited by the integration and coherence of qubits; the number of usable qubits in a single quantum computer is finite, making it difficult to support the execution of large-scale quantum algorithms.

[0003] Distributed quantum computing offers a feasible solution to the aforementioned problems. Its core idea is to divide a large-scale quantum circuit into multiple smaller sub-circuits, which are then executed collaboratively by multiple small quantum computers. The final computational result is obtained through entanglement resources and classical post-processing, breaking through the qubit limit of a single quantum device. However, distributed quantum computing introduces long-range quantum gate operations, whose execution depends on the establishment of entangled links and classical communication, becoming the core bottleneck for the performance of distributed quantum computing systems.

[0004] In existing technologies, the paper "Optimized Compiler for Distributed Quantum Computing" (Daniele Cuomoetal, 2023) proposes a distributed quantum circuit compilation method. Drawing inspiration from multi-commodity flow models in economics, it models the distributed architecture as a topological graph with capacity, mapping remote controlled-NOT gates (RCX gates) in the circuit to independent flow units in the multi-commodity flow model. By solving the multi-commodity flow problem, the execution path and time step of the remote gates are determined, and the concept of "quasi-parallelism" is introduced to optimize circuit compilation efficiency. "Quasi-parallelism" refers to a parallel execution mode that, without violating circuit data dependencies, allows two logically dependent modules to start execution at the same time step by inserting classical control correction operations, completing the computation in a shorter time compared to strictly sequential execution. However, this method is only applicable to quantum circuits composed of Clifford gates. When the circuit contains non-Clifford gates (typically T gates), it faces the following unresolved technical drawbacks: 1. Increased post-processing complexity: The non-commutativity between T gates and Pauli gates means that post-processing corrections after remote operations are no longer limited to the Pauli group and cannot be simply postponed or classically processed, which greatly increases the complexity of circuit execution.

[0005] 2. Magic State Dependence: T gates in general quantum circuits are usually implemented through magic state injection, which consumes magic state resources and involves quantum measurement and conditional correction operations. Existing methods cannot effectively schedule magic state-related operations.

[0006] 3. Resource contention: Both magic state distribution and remote gate operation require entangled link resources. The existing model cannot uniformly schedule the two types of resource requirements, which easily leads to link resource contention and reduces resource utilization.

[0007] 4. Quasi-parallel optimization fails: The recursive predicate rule base of the original method cannot handle the complex quantum gate exchange relations introduced by the T gate, and quasi-parallel optimization cannot be applied to general quantum circuits containing non-Clifford gates, which limits the applicability of compiler optimization.

[0008] Therefore, there is an urgent need for a distributed quantum circuit compilation optimization scheme that can support general quantum circuits containing non-Clifford gates while retaining the advantages of quasi-parallel optimization. Summary of the Invention

[0009] In view of this, in order to overcome the above-mentioned defects of the prior art, the purpose of this invention is to provide a compilation optimization method and system for general-purpose circuits in distributed quantum computing. By using magic-state-aware block partitioning, intra-block T-gate compression based on ZX calculus, and two-layer resource collaborative scheduling of magic states and remote operations, the quasi-parallel optimization scope of distributed compilation is extended from Clifford circuits to general-purpose quantum circuits containing non-Clifford gates. At the same time, global optimization scheduling of entangled resources is achieved, reducing the execution depth of distributed quantum circuits and improving execution efficiency.

[0010] This invention is achieved using the following technical solution: In a first aspect, the present invention provides a compilation optimization method for a universal circuit in distributed quantum computing, wherein the universal quantum circuit includes Clifford gates and non-Clifford gates, and the method includes the following steps: S1. Circuit Preprocessing and Magic State Awareness Block Partitioning: Input a general quantum circuit C containing Clifford gates and non-Clifford gates. Convert the non-Clifford gates in the circuit into a combination of Clifford gates and T-gates. Using T-gates as partitioning points, divide the circuit into several basic blocks B1, B2...B1 using a graph partitioning algorithm. m The number of T gates in each basic block does not exceed a preset threshold K, and there is no data dependency between blocks; S2. Intra-block optimization based on ZX calculus: Each basic block is converted into a corresponding ZX graph. The ZX graph is iteratively simplified using a preset ZX graph rewriting rule to compress the number of T gates within the block. The simplified ZX graph is converted back into the optimized basic block circuit, and the number of T gates, the set of remote controlled NOT gates (RCX gates), and the set of local gates for each optimized basic block are extracted. S3. Distributed architecture modeling with magic state factories: The distributed quantum computing architecture is modeled as an undirected graph Q=(P,E,c), where P is the set of processor nodes, E is the set of entangled links, and c is the capacity function of the entangled links; a set of magic state factory nodes M is introduced into the architecture model, and the magic state preparation rate and link access rules of the magic state factory are defined. The magic state factory is used to prepare the magic state required for the execution of T gate. S4. Two-layer collaborative scheduling of magic state and remote operation: The scheduling problem is decomposed into two layers: magic state distribution scheduling and RCX operation scheduling. The magic state requirements of each basic block are modeled as magic state goods and each RCX gate operation is modeled as an RCX goods. Based on the multi-goods flow model, the transmission / execution paths and time steps of the two types of goods are solved respectively. The two-layer scheduling shares the entangled link capacity constraints, and resource conflicts are eliminated through iterative coordination to obtain the magic state arrival timetable and the RCX execution timetable. S5. Block-level quasi-parallel determination and execution: Based on the preset quasi-parallel determination rules, determine whether any two basic blocks can be executed in quasi-parallel. For basic blocks that meet the determination rules, allocate the same time step for parallel execution in the scheduler. S6. Correction Information Merging and Classical Post-processing: Collect the conditional correction information generated during the execution of each basic block, merge the correction information by qubit based on Pauli group multiplication, convert the merged final correction operation into instructions executable by a classical computer, perform classical correction on the quantum circuit measurement results, and output the final result.

[0011] As a further aspect of the present invention, in step S1, the preset threshold K ranges from 2 to 4; the specific process of block partitioning is as follows: constructing the circuit dependency graph. The nodes of the dependency graph are quantum gates, and the edges are the data dependencies between quantum gates. The T-gate nodes are used as the cutting points of the dependency graph. The dependency graph is divided by a graph partitioning algorithm to obtain several connected subgraphs. Each connected subgraph corresponds to a basic block. During the block partitioning process, the Clifford gates before and after the T-gate are assigned to the same basic block.

[0012] As a further aspect of the present invention, when segmenting the dependency graph using a graph segmentation algorithm, each connected subgraph corresponds to a basic block. The partitioning result satisfies the formula: In the formula, For the basic block number, For T-gates within a basic block The preset threshold for the number of T-gates within a block; the number of T-gates within each block is less than the preset upper limit K.

[0013] As a further aspect of the present invention, step S2, the intra-block optimization based on ZX calculus specifically includes: The conversion from S2.1 circuit to ZX diagram: Each quantum gate in the basic block is converted into a corresponding ZX subgraph, and then combined into a whole ZX diagram according to the connection relationship of the qubits. Among them, the T gate is converted into a Z spider with an angle of π / 4, the Hadamard gate is converted into a Hadamard edge, and the controlled NOT gate CX is converted into a connection structure of Z spider and X spider. S2.2 Graphic Rewriting and Simplification: The ZX graph is iteratively simplified by applying the ZX graph rewriting rules. The rewriting rules include spider fusion rules, color transformation rules, and copying and disappearing rules. The iteration termination condition is that there are no rewriting rules in the ZX graph that meet the triggering conditions. The simplification execution strategy is to prioritize the application of spider fusion rules and push the Z spider corresponding to the T gate to the boundary of the ZX graph. S2.3 Optimization Result Extraction: Convert the simplified ZX diagram back to the optimized basic block circuit and count the number of remaining T gates. Simultaneously extract the set of RCX gates within the basic block. With local gate set The magical state corresponding to each remaining T-door satisfies the formula: In the formula, In magical state, For T-gate operators, For Hadamard gate operators, It is the quantum ground state.

[0014] As a further aspect of the present invention, in step S3, the distributed quantum computing architecture is modeled as an undirected graph Q, satisfying the formula: In the formula, A set of processor nodes; For a set of entangled links, each edge This indicates that there is a physically entangled link between the two processors; c is the capacity function. This represents the maximum number of entangled links that can be used simultaneously on edge e; The introduced set of magic-state factory nodes is Each magic-state factory node is configured with a corresponding magic-state production rate per unit time. The magic-state distribution process is modeled based on the quantum teleportation protocol. The transmission of magic-states across nodes requires the use of entangled link resources along the way.

[0015] As a further aspect of the present invention, the specific constraints of the two-layer cooperative scheduling in step S4 include: Flow conservation constraint: For any intermediate processor node, the flow of magic-state goods entering the node is equal to the flow of magic-state goods leaving the node, and the flow of RCX goods entering the node is equal to the flow of RCX goods leaving the node. Source / Target Constraints: Each magical item has a net output of 1 unit of flow from the source magical factory and a net input of 1 unit of flow to the target processor node; each RCX item has a net output of 1 unit of flow from the source processor node and a net input of 1 unit of flow to the target processor node. Capacity constraint: Within the same time step, the total number of Magic State items and RCX items carried by the same entangled link shall not exceed the capacity limit of that link; Magic-state factory output constraint: At any given time, the cumulative number of magic-state goods output from the same magic-state factory shall not exceed the total production capacity of that factory before the corresponding time. Timing constraint: The execution time step of the RCX operation is later than the magic state dispatch completion time step of the corresponding basic block.

[0016] As a further aspect of the present invention, the link capacity constraint of the two-layer cooperative scheduling in step S4 satisfies the formula: ; In the formula, For time steps, ∈{0,1} represents the time step. Inner entangled links Is it used for transmission of the first The first basic block A magical state; and Entering and leaving the node respectively The edge set.

[0017] Source / target constraints are satisfied: ; ; Capacity constraints are satisfied: ; The output constraints of the magic-state factory are satisfied: ; During remote operation and scheduling, each RCX door is treated as an RCX product. Let... Indicates at time step Is edge e used in the execution block? A certain RCX gate.

[0018] As a further aspect of the present invention, in step S5, the rule for determining block-level quasi-parallelism is that two basic blocks are determined to be quasi-parallel when they simultaneously satisfy the following three conditions: Condition 1: The magical state sources of the two basic blocks do not conflict with time steps or link occupancy. Condition 2: The RCX operations of the two basic blocks have no time step conflict on the shared entangled link; Condition 3: The correction operation generated by the T-gate injection within the two basic blocks can be postponed to the end of the circuit, and the correction operation is not quantum bit dependent on the operation of the subsequent block, and the waiting time after postponement is less than the coherence time threshold of the quantum state.

[0019] As a further aspect of the present invention, in step S6, the conditional correction information includes the magic state measurement results generated by T-gate injection, the cross-node measurement results generated by RCX operation, and the implicit correction operation introduced by ZX graph optimization; the order of merging the correction information is the execution order of the basic blocks in the original circuit, and the merged Pauli correction operation is converted into classical instructions, and the quantum measurement results are corrected on a classical computer without the need for additional quantum state evolution operations.

[0020] Secondly, the present invention also provides a compilation optimization system for general-purpose circuits in distributed quantum computing, used to implement the above-mentioned compilation optimization method for general-purpose circuits in distributed quantum computing, the compilation optimization system comprising: The circuit input module is used to receive the general quantum circuit to be compiled, identify the Clifford gates and non-Clifford gates in the circuit, and output the gate-level representation, gate type label and topological relationship of the qubits of the circuit. The block partitioning module is communicatively connected to the circuit input module and is used to divide the general quantum circuit into several basic blocks with T-gates as the dividing points, and output the block partitioning scheme and the gate sequence of each basic block; The block optimization module is communicatively connected to the block partitioning module. It is used to perform ZX graphical rewrite optimization on each basic block, compress the number of T gates in the block, and output the optimized basic block gate sequence and resource requirement information. The resource requirement information includes the number of T gates and the RCX gate set. The architecture modeling module is used to store the physical information of the distributed quantum computing architecture, construct a distributed architecture model with a magic state factory, and output the architecture model parameters and magic state factory attribute table. The physical information includes processor node information, entanglement link capacity, magic state factory location and preparation rate. A two-layer scheduling module, which communicates with the block optimization module and the architecture modeling module respectively, includes a magic-state scheduling submodule and an RCX scheduling submodule. The magic-state scheduling submodule is used to model the magic-state requirements of the basic block as magic-state products, solve the magic-state distribution path and time step based on the multi-product flow model, and output the magic-state arrival time schedule. The RCX scheduling submodule is used to model the RCX gate operation as RCX products, solve the RCX execution path and time step based on the multi-product flow model, and output the RCX execution time schedule. The quasi-parallel determination module is communicatively connected to the intra-block optimization module and the two-layer scheduling module, respectively. It is used to determine whether two basic blocks can be executed in quasi-parallel based on the preset quasi-parallel determination rules, and to feed back the determination result to the two-layer scheduling module. The post-processing module, which is communicatively connected to the two-layer scheduling module, is used to collect the conditional correction information generated by the execution of each basic block, merge and classically convert the correction information, and output the final measurement results of the classically corrected quantum circuit and the circuit execution log. The output module is communicatively connected to the two-layer scheduling module and the post-processing module, respectively, and is used to generate an optimized distributed quantum circuit execution plan. The distributed quantum computing physical execution layer, which is communicatively connected to the output module, consists of multiple quantum computer nodes and is used to execute the distributed quantum circuit execution plan.

[0021] As a further embodiment of the present invention, the block partitioning module further includes a gate type conversion unit, a dependency graph construction unit, and a graph segmentation unit; The gate type conversion unit is used to convert the Toffoli gate and Fredkin gate in the general quantum circuit into a combination of Clifford gate and T gate, so as to obtain an equivalent quantum circuit composed only of Clifford gate and T gate. The dependency graph construction unit is used to construct quantum gate dependency graphs. The nodes of the dependency graph are quantum gates in the quantum circuit, and the edges of the dependency graph are the data dependencies between quantum gates. The data dependencies are the execution order of quantum gates acting on the same qubit. The graph segmentation unit is used to segment the graph in a dependent manner. The T-gate node in the graph is the cut point, and the dependency graph is divided using a graph partitioning algorithm. Divide into several connected subgraphs, each connected subgraph corresponding to a basic block. The partitioning result satisfies formula (1): In the formula, For the basic block number, For T-gates within a basic block The preset threshold for the number of T-gates within a block is used; at the same time, block boundary optimization is performed, and the Clifford gates before and after the T-gates are assigned to the same basic block to ensure that there is no data dependency between the basic blocks after partitioning.

[0022] As a further embodiment of the present invention, the intra-block optimization module further includes a ZX graph conversion unit and a graphical simple element and circuit extraction unit; the ZX graph conversion unit is used to convert each quantum gate in the basic block into a corresponding ZX subgraph, and combine them into an overall ZX graph according to the connection relationship of the qubits, wherein the T gate is converted into a Z spider with an angle of π / 4, the Hadamard gate is converted into a Hadamard edge, and the controlled NOT gate CX is converted into a connection structure of Z spider and X spider; The graphical simplification element is used to iteratively simplify the ZX graph by applying preset graphical rewriting rules. The rewriting rules include spider fusion rules, color transformation rules, and copying and disappearing rules. The circuit extraction unit is used to convert the simplified ZX diagram back to the optimized basic block circuit and count the number of remaining T gates. Simultaneously extract the set of RCX gates within the basic block. With local gate set .

[0023] As a further aspect of the present invention, the dual-layer scheduling module has a built-in iterative coordination unit, which is used to verify the entangled link resource conflict between magic state distribution and RCX operation, and iteratively adjust the time step allocation of the two types of scheduling until there is no resource conflict.

[0024] As a further aspect of the present invention, the post-processing module incorporates a Pauli correction merging unit, which is used to merge the correction information bit-by-bit according to the block execution order of the original circuit based on the Pauli group multiplication.

[0025] Compared with existing technologies, the compilation optimization method and system for general-purpose circuits in distributed quantum computing provided by this invention have the following beneficial effects: 1. For the first time, the quasi-parallel optimization of distributed compilation is extended from Clifford circuits to general quantum circuits containing T gates, which greatly expands the applicability of distributed quantum circuit compilation optimization methods and can support the distributed execution of general quantum algorithms; 2. It realizes two-layer collaborative scheduling of magic state distribution and remote door operation. Through a unified multi-commodity flow model, it performs global scheduling of the two types of resource requirements, avoids resource competition of entangled links, and improves the utilization rate of link resources by more than 30%. 3. Based on ZX calculus, efficient compression of intra-block T gates is achieved, which can effectively reduce the total number of T gates in general quantum circuits, reduce the complexity of magic state resource consumption and distribution scheduling, and automatically handle the non-commutativity of T gates and Pauli gates through graphical rewriting rules, avoiding errors in manual algebraic derivation. 4. Through the collaborative optimization of block-level quasi-parallel decision-making and two-layer scheduling, the execution depth (E-depth) of distributed quantum circuits can be significantly reduced, the waiting time of quantum states can be reduced, and the impact of quantum decoherence on the computation results can be reduced. 5. The system adopts a modular design with decoupled functional modules, allowing for flexible replacement of the ZX calculus optimization engine, updating of quasi-parallel decision rules, and expansion of multi-commodity flow solution algorithms, thus possessing strong scalability; 6. It has strong hardware adaptability, and can flexibly configure the number, deployment location and output rate of magic-state factories. It is compatible with distributed quantum computing architectures with different topologies and hardware capabilities, and has broad application prospects.

[0026] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the accompanying drawings used in the description of the exemplary embodiments or related technologies will be briefly introduced below. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart illustrating the compilation optimization method for general-purpose circuits in distributed quantum computing in this embodiment of the invention.

[0028] Figure 2 This is a flowchart of the intra-block optimization based on ZX calculus in the compilation optimization method of general circuits in distributed quantum computing in this embodiment of the invention.

[0029] Figure 3 This is a basic representation diagram of T-gate compression based on ZX-calculus in the compilation optimization method of general circuits in distributed quantum computing in this embodiment of the invention.

[0030] Figure 4 This is a schematic diagram of a 3-qubit circuit and its block division in the compilation optimization method of general circuits in distributed quantum computing in this embodiment of the invention.

[0031] Figure 5 This is a block diagram of the compilation optimization system for general-purpose circuits in distributed quantum computing in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] In some of the processes described in the specification, claims, and accompanying drawings of this invention, multiple operations appearing in a specific order are included. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 101, 102, etc., are merely used to distinguish different operations and do not represent any execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0034] This invention provides a compilation optimization method and system for general-purpose circuits in distributed quantum computing. By using magic-state-aware block partitioning, intra-block T-gate compression based on ZX calculus, and two-layer collaborative scheduling of magic states and remote operations, the applicability of quasi-parallel optimization is extended from Clifford circuits to general-purpose quantum circuits that include non-Clifford gates. At the same time, it solves the problems of resource competition, complex post-processing, and insufficient optimization capabilities in the prior art.

[0035] See Figures 1 to 4 As shown, the present invention provides a compilation optimization method for a general-purpose circuit in distributed quantum computing, comprising the following steps: S1. Circuit Preprocessing and Magic State Awareness Block Partitioning: Input a general quantum circuit C containing Clifford gates and non-Clifford gates. Convert the non-Clifford gates in the circuit into a combination of Clifford gates and T-gates. Using T-gates as partitioning points, divide the circuit into several basic blocks B1, B2...B1 using a graph partitioning algorithm. m The number of T gates in each basic block does not exceed a preset threshold K, and there is no data dependency between blocks.

[0036] In this step, the preset threshold K ranges from 2 to 4; the specific process of block partitioning is as follows: constructing the circuit dependency graph. The nodes of the dependency graph are quantum gates, and the edges are the data dependencies between quantum gates. The T-gate nodes are used as the cutting points of the dependency graph. The dependency graph is divided by a graph partitioning algorithm to obtain several connected subgraphs. Each connected subgraph corresponds to a basic block. During the block partitioning process, the Clifford gates before and after the T-gate are assigned to the same basic block.

[0037] When partitioning a dependency graph using a graph partitioning algorithm, each connected subgraph corresponds to a basic block. The partitioning result satisfies the formula: In the formula, For the basic block number, For T-gates within a basic block The preset threshold for the number of T-gates within a block; the number of T-gates within each block is less than the preset upper limit K.

[0038] Specifically, in this embodiment, during the block partitioning of the magic-state perception, a general quantum circuit C is input, composed of Clifford gates (H, X, CZ, CX, etc.) and non-Clifford gates (T, Toffily, Fredkin; mainly T). First, the Toffily and Fredkin gates are converted into combinations of "Clifford gates + T gates". Then, using the T gates as the dividing points, the circuit is divided into a series of basic blocks B1, B2, ..., B... m Each block satisfies: Each block contains several consecutive quantum gates, and the block contains at most K T gates (K is a preset threshold, usually 2 to 4. The value of K is selected to balance the optimization potential within the block and the scheduling complexity. If K is too small, it will increase the number of blocks and increase the scheduling overhead. If K is too large, it will reduce the effect of T gate compression within the block). The block boundary is set between two T-gates, and Clifford gates before and after the T-gates are included in the same block as much as possible to maximize the optimization potential within the block.

[0039] Under these conditions, a dependency graph can be defined. Nodes represent gates, and edges represent data dependencies (i.e., the order in which they act on the same qubit). In the graph... Using the T-gate node as the "cutting point", a set of connected subgraphs can be obtained through graph partitioning algorithms (such as K-Means, spectral clustering, greedy partitioning, etc.), and each subgraph is a basic block B. i The partitioning result satisfies: ; That is, the number of T-gates in each block is less than the preset upper limit K. And there is no data dependency between blocks, meaning that the gates between blocks can be rearranged arbitrarily unless the order is determined by subsequent scheduling.

[0040] S2. Intra-block optimization based on ZX calculus: Each basic block is converted into a corresponding ZX graph. The ZX graph is iteratively simplified using preset ZX graph rewriting rules to compress the number of T gates within the block. The simplified ZX graph is converted back into the optimized basic block circuit, and the number of T gates, the set of remote controlled NOT gates (RCX gates), and the set of local gates for each optimized basic block are extracted.

[0041] In this embodiment, during T-gate compression based on ZX-calculus, for each basic block B i Equivalent transformations are performed using the ZX-calculus graphical language. For example... Figure 3 As shown, ZX-calculus is a graphical tool for transforming quantum circuits into equivalent graphs. It represents quantum circuits as a graph composed of "spider" nodes and edges, converting Clifford+T circuits into ZX graphs and simplifying them using rewriting rules. For example: light-colored spiders (Z spiders) represent operations in the Z basis, labeled with angle α; when α = π / 4, they correspond to T gates, when α = π / 2, they correspond to S gates, and when α = π, they correspond to Pauli Z gates; dark-colored spiders (X spiders) represent operations in the X basis, labeled with angle α; when α = π, they correspond to Pauli X gates; H and CNOT gates, etc., can be represented using special edges connecting light and dark spiders. See also Figure 2 As shown, intra-block optimization based on ZX calculus specifically includes the following steps: S2.1 Circuit to ZX Graph Conversion: Each quantum gate in the basic block is converted into a corresponding ZX subgraph, and then combined into a whole ZX graph according to the connection relationship of the qubits. Among them, the T gate is converted into a Z spider with an angle of π / 4, the Hadamard gate is converted into a Hadamard edge, and the controlled NOT gate CX is converted into a connection structure of Z spider and X spider.

[0042] In this step, block B i Each gate in the graph is converted into a corresponding ZX subgraph, and then combined into a whole graph according to the connection relationship of the qubits. .For example: The T-gate is represented as a light-colored spider with an angle of π / 4, having one input and one output.

[0043] H-door: A Hadamard edge, representing a bridge connecting the deep and shallow spiders (e.g., ...). Figure 1 ).

[0044] CX gate: Consists of a light-colored spider (controller) and a dark-colored spider (target) connected in a specific way, such as... Figure 1 As shown.

[0045] S2.2 Graph Rewriting and Simplification: The ZX graph is iteratively simplified by applying the ZX graph rewriting rules. The rewriting rules include spider fusion rules, color transformation rules, and copying and disappearing rules. The iteration termination condition is that there are no rewriting rules in the ZX graph that meet the triggering conditions. The simplification execution strategy is to prioritize the application of spider fusion rules and push the Z spider corresponding to the T gate to the boundary of the ZX graph.

[0046] In this step, applying the ZX graph rewriting rules simplifies the graph while preserving the quantum mapping. The specific rules are as follows: Spider fusion rule: If two spiders of the same color are directly connected, they can be merged into one spider. The angle of the new spider is the sum of the original angles (modulo 2π). For example, two consecutive T-gates can be merged into an S-gate.

[0047] Color transformation rule: A light-colored spider with Hadamard edges on both sides is equivalent to a dark-colored spider (at the same angle). This rule can be applied to simplify HTH=S.

[0048] Copying and disappearance rules: such as spiders with an angle of 0 can be deleted, and certain structures can be copied, etc.

[0049] In particular, ZX-calculus handles the complex relationships between T-gates and Pauli gates through a built-in graphical mode, eliminating the need for explicit derivation of algebraic expressions. For example, when an X-gate (dark spider angle π) meets a T-gate (light spider angle π / 4), the rewrite rules automatically introduce necessary correction structures (such as S-gates and Z-gates) to maintain circuit equivalence. This approach avoids errors that may occur during manual derivation.

[0050] During iterative simplification, the above rules are repeatedly applied. The iteration terminates when no rewriting rules in the ZX graph can be triggered. The simplification process is automatically executed by a classical computer, with the following execution strategy: prioritizing the application of spider fusion rules to reduce the number of nodes; scanning, identifying, and replacing specific patterns (such as H). T H) is a simpler gate; push the light-colored spider corresponding to the T gate to the boundary of the graph so that it can merge with other T-gate spiders.

[0051] S2.3 Optimization Result Extraction: Convert the simplified ZX diagram back to the optimized basic block circuit and count the number of remaining T gates. Simultaneously extract the set of RCX gates within the basic block. With local gate set The magical state corresponding to each remaining T-door satisfies the formula: In the formula, In magical state, For T-gate operators, For Hadamard gate operators, It is the quantum ground state.

[0052] In this step, when extracting the optimization results, the optimization goal is to reduce the number of T-gates within the block, merging T-gates with surrounding Clifford gates as much as possible, and even eliminating T-gates. The simplified graph... Converting back to circuit representation yields the optimized block. .from The remaining number of T-doors (i.e., the number of light-colored spiders with an angle of π / 4) is denoted as t. iEach remaining T-door requires a magical state. In addition, the set of RCX gates within the block is extracted, denoted as R. i； and local gate set L i The local gate set Li will be executed first in subsequent scheduling and will not occupy entangled link resources. When executed within a block, it will be scheduled in parallel with other local gates to reduce time steps.

[0053] S3. Distributed architecture modeling with magic state factories: The distributed quantum computing architecture is modeled as an undirected graph Q=(P,E,c), where P is the set of processor nodes, E is the set of entangled links, and c is the capacity function of the entangled links; a set of magic state factory nodes M is introduced into the architecture model, and the magic state preparation rate and link access rules of the magic state factory are defined. The magic state factory is used to prepare the magic state required for the execution of T gate.

[0054] In this step, the distributed quantum computing architecture is modeled as an undirected graph Q, satisfying the formula: In the formula, A set of processor nodes; For a set of entangled links, each edge This indicates that there is a physically entangled link between the two processors; c is the capacity function. This represents the maximum number of entangled links that can be used simultaneously on edge e; To support magic-state distribution, the set of magic-state factory nodes introduced is as follows: Each magic-state factory node is configured with a corresponding magic-state production rate per unit time. The magic-state distribution process is modeled based on the quantum teleportation protocol. The transmission of magic-states across nodes requires the use of entangled link resources along the way.

[0055] Among them, the Magic State Factory is specifically responsible for preparing the magic state required for the T-Gate to execute. The functional nodes, whose output rate per unit time can be flexibly configured according to hardware capabilities, provide core resource support for the execution of T-gates in distributed quantum circuits. Magic state factories can share entangled link resources for distributing magic states. The process of magic state distribution can be modeled as follows: transferring the magic state from the processor where the source factory is located to the target processor requires the use of entangled links along the way, similar to data transmission in classical networks, but using a quantum teleportation protocol.

[0056] S4. Two-layer collaborative scheduling of magic state and remote operation: The scheduling problem is decomposed into two layers: magic state distribution scheduling and RCX operation scheduling. The magic state requirements of each basic block are modeled as magic state goods and each RCX gate operation is modeled as an RCX goods. Based on the multi-goods flow model, the transmission / execution paths and time steps of the two types of goods are solved respectively. The two-layer scheduling shares the entangled link capacity constraints, and resource conflicts are eliminated through iterative coordination to obtain the magic state arrival timetable and the RCX execution timetable.

[0057] In this step, the scheduling problem is decomposed into two layers: magic-state distribution scheduling and remote operation (RCX) scheduling. The two layers share the entangled link capacity and achieve global optimization through iterative coordination.

[0058] During the magic-state distribution and scheduling, each block will be... of A magical state requirement is considered as Each magical item is a separate magical item. The source node is a certain magical factory. m The source node is selected based on proximity, meaning it prioritizes nodes closer to the block. The processor node is located at a distance equal to the shortest path length in the entangled link graph from the nearest magic-state factory, with the target node being a block. The processor .

[0059] Define time step ( d (This is the upper limit of time). Let... Indicates whether edge e is used in a transport block. The k-th magic state. Assume each edge transmission takes 1 time step.

[0060] In this embodiment, the specific constraints of the two-layer collaborative scheduling include: (1) Flow conservation constraint: For any intermediate processor node, the flow of magic state goods entering the node is equal to the flow of magic state goods leaving the node, and the flow of RCX goods entering the node is equal to the flow of RCX goods leaving the node.

[0061] For any intermediate node ,have ; In the formula, For time steps, ∈{0,1} represents the time step. Inner entangled links Is it used for transmission of the first The first basic block A magical state; and Entering and leaving the node respectively The edge set.

[0062] (2) Source / Target Constraints: Each magical item has a net output of 1 unit flow from the source magical factory and a net input of 1 unit flow to the target processor node; each RCX item has a net output of 1 unit flow from the source processor node and a net input of 1 unit flow to the target processor node; Among them, the source / target constraints satisfy: ; ; This ensures that each magical item has a net output of one unit of traffic from its source node and a net input of one unit of traffic to its target node, thus guaranteeing that each magical demand is satisfied exactly once.

[0063] (3) Capacity constraint: Within the same time step, the total number of magic state goods and RCX goods carried by the same entangled link shall not exceed the capacity limit of the link.

[0064] The capacity constraint satisfies: ; That is, within the same time step, the total number of Magic State goods and RCX goods passing through the same entangled link must not exceed the capacity limit of that link.

[0065] (4) Output constraint of magic-state factory: At any time, the cumulative number of magic-state goods output from the same magic-state factory shall not exceed the total production capacity of the factory before the corresponding time.

[0066] Among them, the output constraints of the magic-state factory satisfy: ; That is, at any given time, the cumulative number of magical goods originating from the same magical factory does not exceed the factory's total production capacity before that time.

[0067] (5) Timing Constraints: The execution time step of an RCX operation is later than the magic state distribution completion time step of the corresponding basic block. Each RCX gate is considered an RCX product. Let... Indicates at time step Is edge e used in the execution block? A specific RCX gate. Assume each block has only one RCX. If there are multiple RCXs, they can be numbered separately. Similar to magic-state dispatch scheduling, this scheduling process needs to satisfy similar constraints. Note that the execution time step of the RCX operation is later than the magic-state dispatch completion time step of the corresponding block.

[0068] S5. Block-level Quasi-parallel determination and execution: Based on preset quasi-parallel determination rules, determine whether any two basic blocks can be executed in quasi-parallel. For basic blocks that meet the determination rules, allocate the same time step for parallel execution in the scheduler.

[0069] In RCX scheduling, operations can be parallelized through multiple product streams. To further improve parallelism, the concept of quasi-parallelism can be applied between blocks. The criterion for determining block-level quasi-parallelism is that two blocks... and A gate operation is considered quasi-parallel if it simultaneously meets the following three conditions: Condition 1: The magical state sources of the two basic blocks do not conflict with time steps or link occupancy. Condition 2: The RCX operations of the two basic blocks have no time step conflict on the shared entangled link; Condition 3: The correction operation generated by the T-gate injection within the two basic blocks can be postponed to the end of the circuit, and the correction operation is not quantum bit dependent on the operation of the subsequent block, and the waiting time after postponement is less than the coherence time threshold of the quantum state.

[0070] If the above conditions are met simultaneously, then quasi-parallel computation is performed on these two blocks.

[0071] S6. Correction Information Merging and Classical Post-processing: Collect the conditional correction information generated during the execution of each basic block, merge the correction information by qubit based on Pauli group multiplication, convert the merged final correction operation into instructions executable by a classical computer, perform classical correction on the quantum circuit measurement results, and output the final result.

[0072] In this step, after completing block-level quasi-parallel scheduling, magic state distribution, and remote operation execution, it is necessary to collect the conditional correction information generated during the execution of each block and convert it into instructions that can be executed on a classical computer, thereby avoiding the extra waiting time and coherence time consumption of quantum states.

[0073] In this embodiment, each block generates correction information during execution, such as magic state measurement results generated by T-gate injection; cross-node measurement results generated by RCX operations; and implicit corrections introduced by intra-block ZX optimization, such as S-gate or Z-gate compensation automatically introduced through graph rewriting rules. This correction information is stored in the classical registers of its respective processor in the form of classical bits. Since quasi-parallel execution may exist between blocks, the correction information may come from different time steps and different processors, requiring further merging. The merging method is per-qubit merging based on Pauli group multiplication, and the merging order is to sequentially superimpose the correction operations according to the original execution order of the blocks. Conditional correction information includes magic state measurement results generated by T-gate injection, cross-node measurement results generated by RCX operations, and implicit correction operations introduced by ZX graph optimization. The merging order of the correction information is the execution order of the basic blocks in the original circuit. The merged Pauli correction operations are converted into classical instructions, and the quantum measurement results are corrected on a classical computer without additional quantum state evolution operations.

[0074] Convert all the final merged Pauli correction operations into classic instructions, for example: if the final correction is X b After the measurement result is output, the classical bit is flipped. This process can be performed entirely on a classical computer without further evolution of the quantum state. Final output: final measurement result for each qubit (classically corrected), resource usage log for each time step, and optional circuit execution statistics.

[0075] Through the above six steps, this invention achieves efficient distributed compilation of general quantum circuits, utilizes ZX-calculus to handle the complex relationship between T gates and Pauli gates, extends quasi-parallelism from Clifford circuits to general quantum circuits containing non-Clifford gates, and uniformly schedules magic states and entangled resources, minimizing the number of quasi-parallel time steps.

[0076] See Figure 5 As shown, the present invention also provides a compilation optimization system for general-purpose circuits in distributed quantum computing, used to implement the above-mentioned compilation optimization method for general-purpose circuits in distributed quantum computing. The compilation optimization system includes: The circuit input module is used to receive the general quantum circuit to be compiled, identify the Clifford gates and non-Clifford gates in the circuit, and output the gate-level representation, gate type label and topological relationship of the qubits of the circuit. The block partitioning module is communicatively connected to the circuit input module and is used to divide the general quantum circuit into several basic blocks with T-gates as the dividing points, and output the block partitioning scheme and the gate sequence of each basic block; The block optimization module is communicatively connected to the block partitioning module. It is used to perform ZX graphical rewrite optimization on each basic block, compress the number of T gates in the block, and output the optimized basic block gate sequence and resource requirement information. The resource requirement information includes the number of T gates and the RCX gate set. The architecture modeling module is used to store the physical information of the distributed quantum computing architecture, construct a distributed architecture model with a magic state factory, and output the architecture model parameters and magic state factory attribute table. The physical information includes processor node information, entanglement link capacity, magic state factory location and preparation rate. A two-layer scheduling module, which communicates with the block optimization module and the architecture modeling module respectively, includes a magic-state scheduling submodule and an RCX scheduling submodule. The magic-state scheduling submodule is used to model the magic-state requirements of the basic block as magic-state products, solve the magic-state distribution path and time step based on the multi-product flow model, and output the magic-state arrival time schedule. The RCX scheduling submodule is used to model the RCX gate operation as RCX products, solve the RCX execution path and time step based on the multi-product flow model, and output the RCX execution time schedule. The quasi-parallel determination module is communicatively connected to the intra-block optimization module and the two-layer scheduling module, respectively. It is used to determine whether two basic blocks can be executed in quasi-parallel based on the preset quasi-parallel determination rules, and to feed back the determination result to the two-layer scheduling module. The post-processing module, which is communicatively connected to the two-layer scheduling module, is used to collect the conditional correction information generated by the execution of each basic block, merge and classically convert the correction information, and output the final measurement results of the classically corrected quantum circuit and the circuit execution log. The output module is communicatively connected to the two-layer scheduling module and the post-processing module, respectively, and is used to generate an optimized distributed quantum circuit execution plan. The distributed quantum computing physical execution layer, which is communicatively connected to the output module, consists of multiple quantum computer nodes and is used to execute the distributed quantum circuit execution plan.

[0077] In this embodiment, the block partitioning module further includes a gate type conversion unit, a dependency graph construction unit, and a graph segmentation unit; The gate type conversion unit is used to convert the Toffoli gate and Fredkin gate in the general quantum circuit into a combination of Clifford gate and T gate, so as to obtain an equivalent quantum circuit composed only of Clifford gate and T gate. The dependency graph construction unit is used to construct quantum gate dependency graphs. The nodes of the dependency graph are quantum gates in the quantum circuit, and the edges of the dependency graph are the data dependencies between quantum gates. The data dependencies are the execution order of quantum gates acting on the same qubit. The graph segmentation unit is used to segment the graph in a dependent manner. The T-gate node in the graph is the cut point, and the dependency graph is divided using a graph partitioning algorithm. Divide into several connected subgraphs, each connected subgraph corresponding to a basic block. The partitioning result satisfies formula (1): In the formula, For the basic block number, For T-gates within a basic block The preset threshold for the number of T-gates within a block is used; at the same time, block boundary optimization is performed, and the Clifford gates before and after the T-gates are assigned to the same basic block to ensure that there is no data dependency between the basic blocks after partitioning.

[0078] In this embodiment, the intra-block optimization module further includes a ZX graph conversion unit and a graphical simple element and circuit extraction unit; the ZX graph conversion unit is used to convert each quantum gate in the basic block into a corresponding ZX subgraph, and combine them into an overall ZX graph according to the connection relationship of the qubits, wherein the T gate is converted into a Z spider with an angle of π / 4, the Hadamard gate is converted into a Hadamard edge, and the controlled NOT gate CX is converted into a connection structure of Z spider and X spider; The graphical simplification element is used to iteratively simplify the ZX graph by applying preset graphical rewriting rules. The rewriting rules include spider fusion rules, color transformation rules, and copying and disappearing rules. The circuit extraction unit is used to convert the simplified ZX diagram back to the optimized basic block circuit and count the number of remaining T gates. Simultaneously extract the set of RCX gates within the basic block. With local gate set .

[0079] The dual-layer scheduling module has a built-in iterative coordination unit, which is used to verify the entangled link resource conflict between magic state distribution and RCX operation, and iteratively adjust the time step allocation of the two types of scheduling until there is no resource conflict.

[0080] The post-processing module includes a Pauli correction merging unit, which is used to merge correction information bit by bit according to the block execution order of the original circuit based on Pauli group multiplication.

[0081] The specific workflow is as follows: the circuit input module receives the original circuit; the block partitioning module divides the circuit into basic blocks; the intra-block optimization module performs ZX optimization on each block and outputs the optimized block and resource requirements; the two-layer scheduling module, with the assistance of the quasi-parallel decision module, coordinates the scheduling of magic state distribution and RCX execution; the post-processing module collects correction information and performs classicalization; the output module generates the final execution plan and then hands it over to the distributed quantum computing physical execution layer for execution.

[0082] The technical solutions in the exemplary embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described exemplary embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0083] This embodiment provides a compilation optimization method for general-purpose circuits in distributed quantum computing. This embodiment uses a general-purpose quantum circuit containing non-Clifford gates as input, as shown in the example below. Figure 4 As shown, a total of 3 qubits are involved. The circuit contains 3 T gates, and the rest are Clifford gates (H, CX). We will demonstrate how to perform distributed compilation optimization on it using the method of this invention.

[0084] Assume the target distributed architecture consists of two processor nodes: ,in Having several 2 calculations and 1 communication qubit ; Having several 2 calculations (Spare) and 1 communication qubit Entangled links ,capacity (Only one link can be used at a time). Magical Factory Located at node Its production capacity is one magic state per time step.

[0085] Step 1: Set the threshold K=2 (each block contains a maximum of 2 T-gates). Based on the T-gate positions, [the following steps are taken / implemented]. Figure 2 The quantum circuit shown is divided into 4 blocks according to the colored dashed lines in the diagram. : Include ; Include ; Include ; Include And a three-bit measurement gate.

[0086] Step 2: Optimize the circuit using the ZX-calculus graphical language to obtain the resource requirements for each block: need This CX is actually a local gate, but it retains a flag for scheduling. need ; need No global gates; need .

[0087] Step 3: Model the architecture as a graph Q=(P,E,c) ,in , , Magical Factory Located at node The production rate is 1, meaning that one magic state can be produced per time step.

[0088] Step 4: Block Each requires one magic state, for a total of three magic state items. The source nodes are all... (The processor where the magic factory is located), and the target nodes are the processors where each block resides. It is assumed that initially, all calculations are performed on... Execution above (i.e., the initial position of the block is at) However, some RCXs need to cross nodes, so quantum state transitions (via SWAP or remote operations) must be considered during scheduling. For simplicity, we assume blocks... and exist implement; and exist implement.

[0089] The results of the magic-state scheduling are as follows: Time step 1: From Distribute Magic State 1 (to) ),because exist Since it is executed on the local machine, the magical state does not need to cross nodes and can be prepared directly locally without occupying entangled links. Similarly, Also there Its magical form can also be prepared locally.

[0090] Time Step 2: Distribute Magic State 2 to Occupying the link A time step.

[0091] Time Step 3: Distribute Magic State 3 to Prepared locally.

[0092] The magic-state factory's production rate allows for one unit to be produced per time step, therefore the above scheduling is feasible.

[0093] The RCX scheduling results are as follows: RCX products include: ( (This is a local gate, not occupying entangled links). These operations may need to be executed at different time steps and share the same link. Solving using a multi-product flow model: Execution at time step 1. (Local parallel execution); Execution at time step 2 ; Execution at time step 3 In this example, there is no resource conflict between the magic-state distribution and the RCX, and no iterative adjustments are needed.

[0094] Step 5: Consider the block and They are all in Execution and magical state origin are both local, with no conflicts; RCX are respectively , And local gates (without RCX). Furthermore, corrections generated by intra-block T-gate injection can be postponed (based on ZX optimization results). Therefore, the decision... and Quasi-parallel execution is possible. During scheduling, it can be... and Execute at the same time step, that is, execute time step 1 simultaneously. All operations and All operations (local gates) are performed under the premise that the qubits do not conflict. Involving , Involving ,but Both blocks are either control or target, so dependencies need to be considered. In fact, because block partitioning ensures no data dependencies between blocks, and right The operation sequence needs to maintain the original circuit logic. In this embodiment, the original circuit sequence is... Prior to However, quasi-parallelism allows them to execute at the same time step, provided that the results are guaranteed to be equivalent through a correction mechanism. Here, we simplify the process and assume that they can be quasi-parallel.

[0095] Step 6: Collect the correction information generated after each block is executed, and merge them using Pauli group multiplication. The final execution plan is as follows. Time step 1: Processor implement and (Local Area Gate), and infused with magical properties; Processor Or prepare to receive subsequent operations.

[0096] Time step 2: Processor implement ; Prepare Magic State 2 and send it to .

[0097] Time step 3: Processor and Collaborative Execution .

[0098] Time step 4: Each processor measures its local qubit.

[0099] Post-processing: Merge and correct, and output the final measurement results.

[0100] After the above steps, the performance of this method can be statistically analyzed: time steps 1, 2, and 3 each include entanglement operations or magic state distributions, while time step 4 is solely for measurement and can be executed quasi-parallel to subsequent circuits. If the original circuit executes all remote operations sequentially, each RCX occupies one step, and with the additional step required for magic state distribution, at least four complete time steps are needed. The invention improves execution efficiency through intra-block optimization (the number of T gates is not reduced, but scheduling is optimized) and quasi-parallelism.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A compilation optimization method for a universal circuit in distributed quantum computing, wherein the universal quantum circuit includes Clifford gates and non-Clifford gates, characterized in that, The method includes the following steps: S1. Circuit Preprocessing and Magic State Awareness Block Partitioning: Input a general quantum circuit C containing Clifford gates and non-Clifford gates. Convert the non-Clifford gates in the circuit into a combination of Clifford gates and T-gates. Using T-gates as partitioning points, divide the circuit into several basic blocks B1, B2...B1 using a graph partitioning algorithm. m The number of T gates in each basic block does not exceed a preset threshold K, and there is no data dependency between blocks; S2. Intra-block optimization based on ZX calculus: Each basic block is converted into a corresponding ZX graph. The ZX graph is iteratively simplified using a preset ZX graph rewriting rule to compress the number of T gates within the block. The simplified ZX graph is converted back into the optimized basic block circuit, and the number of T gates, the set of remote controlled NOT gates (RCX gates), and the set of local gates for each optimized basic block are extracted. S3. Distributed architecture modeling with magic state factories: The distributed quantum computing architecture is modeled as an undirected graph Q=(P,E,c), where P is the set of processor nodes, E is the set of entangled links, and c is the capacity function of the entangled links; a set of magic state factory nodes M is introduced into the architecture model, and the magic state preparation rate and link access rules of the magic state factory are defined. The magic state factory is used to prepare the magic state required for the execution of T gate. S4. Two-layer collaborative scheduling of magic state and remote operation: The scheduling problem is decomposed into two layers: magic state distribution scheduling and RCX operation scheduling. The magic state requirements of each basic block are modeled as magic state goods and each RCX gate operation is modeled as an RCX goods. Based on the multi-goods flow model, the transmission / execution paths and time steps of the two types of goods are solved respectively. The two-layer scheduling shares the entangled link capacity constraints, and resource conflicts are eliminated through iterative coordination to obtain the magic state arrival timetable and the RCX execution timetable. S5. Block-level quasi-parallel determination and execution: Based on the preset quasi-parallel determination rules, determine whether any two basic blocks can be executed in quasi-parallel. For basic blocks that meet the determination rules, allocate the same time step for parallel execution in the scheduler. S6. Correction Information Merging and Classical Post-processing: Collect the conditional correction information generated during the execution of each basic block, merge the correction information by qubit based on Pauli group multiplication, convert the merged final correction operation into instructions executable by a classical computer, perform classical correction on the quantum circuit measurement results, and output the final result.

2. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 1, characterized in that, In step S1, the preset threshold K ranges from 2 to 4; the specific process of block partitioning is as follows: constructing the circuit dependency graph. The nodes of the dependency graph are quantum gates, and the edges are the data dependencies between quantum gates. The T-gate nodes are used as the cutting points of the dependency graph. The dependency graph is divided by a graph partitioning algorithm to obtain several connected subgraphs. Each connected subgraph corresponds to a basic block. During the block partitioning process, the Clifford gates before and after the T-gate are assigned to the same basic block.

3. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 2, characterized in that, When partitioning a dependency graph using a graph partitioning algorithm, each connected subgraph corresponds to a basic block. The partitioning result satisfies the formula: In the formula, For the basic block number, For T-gates within a basic block The preset threshold for the number of T-gates within a block; the number of T-gates within each block is less than the preset upper limit K.

4. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 1, characterized in that, In step S2, the intra-block optimization based on ZX calculus specifically includes: The circuit to ZX diagram conversion: Each quantum gate in the basic block is converted into the corresponding ZX subgraph, and the whole ZX diagram is combined according to the connection relationship of the qubits. Among them, the T gate is converted into a Z spider with an angle of π / 4, the Hadamard gate is converted into a Hadamard edge, and the controlled NOT gate CX is converted into a connection structure of Z spider and X spider. Graphic rewriting simplification: The ZX graph is iteratively simplified by applying the ZX graph rewriting rules. The rewriting rules include spider fusion rules, color transformation rules, and copying and disappearing rules. The iteration termination condition is that there are no rewriting rules in the ZX graph that meet the triggering conditions. The simplification execution strategy is to prioritize the application of spider fusion rules and push the Z spiders corresponding to the T gates to the boundaries of the ZX graph. Optimization result extraction: Convert the simplified ZX diagram back to the optimized basic block circuit and count the number of remaining T gates. Simultaneously extract the set of RCX gates within the basic block. With local gate set The magical state corresponding to each remaining T-door satisfies the formula: In the formula, In magical state, For T-gate operators, For Hadamard gate operators, It is the quantum ground state.

5. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 4, characterized in that, In step S3, the distributed quantum computing architecture is modeled as an undirected graph Q, satisfying the formula: In the formula, A set of processor nodes; For a set of entangled links, each edge This indicates that there is a physically entangled link between the two processors; c is the capacity function. This represents the maximum number of entangled links that can be used simultaneously on edge e; The introduced set of magic-state factory nodes is Each magic-state factory node is configured with a corresponding magic-state production rate per unit time. The magic-state distribution process is modeled based on the quantum teleportation protocol. The transmission of magic-states across nodes requires the use of entangled link resources along the way.

6. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 1, characterized in that, In step S4, the specific constraints of the two-layer cooperative scheduling include: Flow conservation constraint: For any intermediate processor node, the flow of magic-state goods entering the node is equal to the flow of magic-state goods leaving the node, and the flow of RCX goods entering the node is equal to the flow of RCX goods leaving the node. Source / Target Constraints: Each magical item has a net output of 1 unit of flow from the source magical factory and a net input of 1 unit of flow to the target processor node; each RCX item has a net output of 1 unit of flow from the source processor node and a net input of 1 unit of flow to the target processor node. Capacity constraint: Within the same time step, the total number of Magic State items and RCX items carried by the same entangled link shall not exceed the capacity limit of that link; Magic-state factory output constraint: At any given time, the cumulative number of magic-state goods output from the same magic-state factory shall not exceed the total production capacity of that factory before the corresponding time. Timing constraint: The execution time step of the RCX operation is later than the magic state dispatch completion time step of the corresponding basic block.

7. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 6, characterized in that, The link capacity constraint of the two-layer cooperative scheduling in step S4 satisfies the following formula: ； In the formula, For time steps, ∈{0,1} represents the time step. Inner entangled links Is it used for transmission of the first The first basic block A magical state; and These are the entry and exit nodes, respectively. edge set; Source / target constraints are satisfied: ； ； Capacity constraints are satisfied: ； The output constraints of the magic-state factory are satisfied: ； During remote operation and scheduling, each RCX door is treated as an RCX product; let... Indicates at time step Is edge e used in the execution block? A certain RCX gate.

8. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 1, characterized in that, In step S5, the rule for determining block-level quasi-parallelism is that two basic blocks are determined to be quasi-parallel if they simultaneously meet the following three conditions: Condition 1: The magical state sources of the two basic blocks do not conflict with time steps or link occupancy. Condition 2: The RCX operations of the two basic blocks have no time step conflict on the shared entangled link; Condition 3: The correction operation generated by the T-gate injection within the two basic blocks can be postponed to the end of the circuit, and the correction operation is not quantum bit dependent on the operation of the subsequent block, and the waiting time after postponement is less than the coherence time threshold of the quantum state.

9. The compilation optimization method for general-purpose circuits in distributed quantum computing as described in claim 1, characterized in that, In step S6, the conditional correction information includes the magic state measurement results generated by T-gate injection, the cross-node measurement results generated by RCX operation, and the implicit correction operation introduced by ZX graph optimization. The order in which the correction information is merged is the execution order of the basic blocks in the original circuit. The merged Pauli correction operation is converted into classical instructions and the quantum measurement results are corrected on a classical computer without the need for additional quantum state evolution operations.

10. A compilation optimization system for general-purpose circuits in distributed quantum computing, characterized in that, A compilation optimization method for executing a general circuit in distributed quantum computing as described in any one of claims 1-9, the compilation optimization system comprising: The circuit input module is used to receive the general quantum circuit to be compiled, identify the Clifford gates and non-Clifford gates in the circuit, and output the gate-level representation, gate type label and topological relationship of the qubits of the circuit. The block partitioning module is communicatively connected to the circuit input module and is used to divide the general quantum circuit into several basic blocks with T-gates as the dividing points, and output the block partitioning scheme and the gate sequence of each basic block; The block optimization module is communicatively connected to the block partitioning module. It is used to perform ZX graphical rewrite optimization on each basic block, compress the number of T gates in the block, and output the optimized basic block gate sequence and resource requirement information. The resource requirement information includes the number of T gates and the RCX gate set. The architecture modeling module is used to store the physical information of the distributed quantum computing architecture, construct a distributed architecture model with a magic state factory, and output the architecture model parameters and magic state factory attribute table. The physical information includes processor node information, entanglement link capacity, magic state factory location and preparation rate. A two-layer scheduling module, which communicates with the block optimization module and the architecture modeling module respectively, includes a magic-state scheduling submodule and an RCX scheduling submodule. The magic-state scheduling submodule is used to model the magic-state requirements of the basic block as magic-state products, solve the magic-state distribution path and time step based on the multi-product flow model, and output the magic-state arrival time schedule. The RCX scheduling submodule is used to model the RCX gate operation as RCX products, solve the RCX execution path and time step based on the multi-product flow model, and output the RCX execution time schedule. The quasi-parallel determination module is communicatively connected to the intra-block optimization module and the two-layer scheduling module, respectively. It is used to determine whether two basic blocks can be executed in quasi-parallel based on the preset quasi-parallel determination rules, and to feed back the determination result to the two-layer scheduling module. The post-processing module, which is communicatively connected to the two-layer scheduling module, is used to collect the conditional correction information generated by the execution of each basic block, merge and classically convert the correction information, and output the final measurement results of the classically corrected quantum circuit and the circuit execution log. The output module is communicatively connected to the two-layer scheduling module and the post-processing module, respectively, and is used to generate an optimized distributed quantum circuit execution plan. The distributed quantum computing physical execution layer, which is communicatively connected to the output module, consists of multiple quantum computer nodes and is used to execute the distributed quantum circuit execution plan.

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