Method and apparatus for processing quantum error correction syndrome data stream, terminal and medium

Abstract

The application discloses a kind of processing method, device, terminal and medium of quantum error correction syndrome data stream, the method comprises: based on the state data of alignment after corresponding measurement and control instrument, obtain comprehensive feature vector;Based on the preset health threshold, the pure clean sparse feature vector is obtained by dead bit filtering processing to the comprehensive feature vector;Based on the preset priority coding tree, the feature extraction result is obtained by sparse feature extraction processing to the pure clean sparse feature vector;Based on the bandwidth characteristics of the fixed bit width block transmission bus corresponding to processing system and the preset message structure, the target high-bandwidth utilization rate aggregation message is obtained by processing the feature extraction result.The application aims to realize the hardware level compression and cleaning processing to mass quantum error correction syndrome data stream, to reduce the bandwidth demand of measurement and control data link bus.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method, apparatus, terminal and medium for processing quantum error correction syndrome data streams. Background Technology

[0002] In fault-tolerant quantum computing (such as SurfaceCode-based architectures), the system needs to measure a massive number of ancilla qubits at extremely high frequencies (typically on the microsecond scale). After state decisions by the measurement and control instruments, these measurement results are represented as a multi-channel synchronous 0 / 1 logic bit stream.

[0003] However, as the number of qubits expands to hundreds or even thousands, the measurement and control system faces extremely serious problems: existing instruments typically package the entire array of raw 0 / 1 states for each measurement cycle and upload it to the host computer via a backplane bus (such as PXIe) or network. This O(N) complexity (N is the number of bits) data stream contains a great deal of redundancy and can easily exhaust the system's physical bandwidth; quantum error correction graph matching algorithms (such as MWPM) do not care about absolute 0 or 1 states, but rather about the "flipping" of states in the time dimension. Before executing the core decoding algorithm, the host computer CPU must consume a large number of clock cycles to perform memory-intensive operations such as unpacking, buffering, and bitwise XORing of massive amounts of messages, resulting in closed-loop feedback delay jitter, which seriously threatens the coherence of quantum states; thermal noise or physical degradation of bits in the measurement and control link can lead to frequent "pseudo-flips". If all of this data is reported to the host computer, it will exponentially increase the pathfinding complexity of the decoding algorithm. Summary of the Invention

[0004] The main objective of this application is to provide a method, apparatus, terminal, and medium for processing quantum error correction syndrome data streams, aiming to achieve hardware-level compression and cleaning of massive quantum error correction syndrome data streams to reduce the bandwidth requirements of the measurement and control data link bus.

[0005] To achieve the above objectives, this application provides a method for processing quantum error correction syndrome data streams, which is applied to a processing system deployed in the FPGA of a measurement and control instrument; The method includes: Based on the aligned state data corresponding to the measurement and control instrument, a comprehensive feature vector is obtained, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream; Based on a preset health threshold, the comprehensive feature vector is subjected to dead bit filtering to obtain a pure sparse feature vector. Based on a preset priority encoding tree, sparse feature extraction processing is performed on the pure sparse feature vector to obtain the feature extraction result; Based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure, the feature extraction results are processed to obtain the target high-bandwidth utilization aggregated message to adapt to the bus transmission process corresponding to the processing system.

[0006] Specifically, the aligned state data corresponding to the measurement and control instrument includes a global measurement vector; The comprehensive feature vector obtained based on the aligned state data corresponding to the measurement and control instrument includes: A set of high-speed registers is allocated inside the FPGA to cache the global measurement vector of the previous measurement cycle; The comprehensive feature vector is obtained by performing a bitwise Boolean XOR operation on the global measurement vector and the global measurement vector of the previous measurement cycle.

[0007] Specifically, the step of performing dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector includes: Based on the channel dimension of the comprehensive feature vector, a behavior history shift register is instantiated for the auxiliary bit to obtain the historical flip data corresponding to the auxiliary bit, wherein the behavior history shift register is used to record the flip history of the auxiliary bit; The noise penalty score for the channel is obtained by performing a weighted integral on the historical flipped data corresponding to the auxiliary bit. Based on the comparison result between the noise penalty score and the preset health threshold, a fully auxiliary bit mask vector is generated; Based on the fully auxiliary bit mask vector, the comprehensive feature vector is bit-silenced to obtain the pure sparse feature vector.

[0008] Specifically, the step of performing a weighted integral calculation on the historical flipped data corresponding to the auxiliary bit to obtain the noise penalty score corresponding to the channel includes: The noise penalty score is calculated using the following formula:

[0009] in, This represents the noise penalty score. Indicates the number of measurement cycles. Indicates the number of auxiliary bits. This indicates the depth corresponding to the behavior history shift register. This indicates the preset weighting coefficient. Indicates the first in the historical flipped data The auxiliary bit in the first The time dimension state flip event value for each measurement period This represents the time offset within the sliding window corresponding to the measurement period.

[0010] Specifically, the fully auxiliary bit mask vector includes mask bits; The step of generating a fully auxiliary bitmask vector based on the comparison result between the noise penalty score and the preset health threshold includes: If the noise penalty score is less than or equal to the preset health threshold, the auxiliary bit signal is determined to be healthy, and a mask bit with a value of 1 is generated; if the noise penalty score is greater than the preset health threshold, the auxiliary bit is determined to be a dead bit, and a mask bit with a value of 0 is generated.

[0011] Specifically, the feature extraction result is either a defect index array or the pure sparse feature vector; The step of performing sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain feature extraction results includes: Using the pure sparse feature vector as input, all valid bits with a value of 1 are scanned from bottom to top through a preset priority coding tree to obtain the binary address index corresponding to the valid bits. The binary address index includes the binary address corresponding to the valid bits and the index value corresponding to the auxiliary bits that have been flipped. Based on the binary address index, the number of auxiliary bits that have been flipped is compared with a preset bypass threshold. If the number of auxiliary bits that have been flipped is not greater than the preset bypass threshold, the defect index array is obtained by outputting a preset priority coding tree. If the number of auxiliary bits that have been flipped is greater than the preset bypass threshold, the pure sparse feature vector is obtained by outputting a preset priority coding tree.

[0012] Specifically, the feature extraction results are processed based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure to obtain the target high-bandwidth utilization aggregated message, including: Based on the bandwidth characteristics, the feature extraction results are subjected to word alignment processing to obtain the feature extraction results after word alignment processing; The feature extraction results after word alignment are subjected to cross-period aggregation processing to obtain aggregated data; Based on the preset message structure, a large frame header and a subframe header are added to the aggregated data. The large frame header includes a reference absolute timestamp and a total length, and the subframe header includes a relative clock offset and a valid number of flips. A CRC32 checksum is added to the aggregated data to generate the target high bandwidth utilization aggregated message.

[0013] To achieve the above objectives, this application also provides a processing device for quantum error correction syndrome data streams, applied to a processing system, wherein the processing system is deployed in the FPGA of a measurement and control instrument; The device includes: The first unit is used to obtain a comprehensive feature vector based on the aligned state data corresponding to the measurement and control instrument. The comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream. The second unit is used to perform dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector. The third unit is used to perform sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain the feature extraction result. The fourth unit is used to process the feature extraction results based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure to obtain the target high-bandwidth utilization aggregated message, so as to adapt to the bus transmission process corresponding to the processing system.

[0014] To achieve the above objectives, this application also provides a terminal, including a processor and a memory, the memory storing multiple instructions; the processor loads instructions from the memory to execute the steps in any of the methods provided in this application.

[0015] To achieve the above objectives, this application also provides a medium storing a plurality of instructions adapted for loading by a processor to execute the steps in any of the methods provided in this application.

[0016] This application provides a method, apparatus, terminal, and medium for processing quantum error correction syndrome data streams. First, a comprehensive feature vector is obtained based on the aligned state data corresponding to the measurement and control instrument. Then, based on a preset health threshold, dead bit filtering is performed on the comprehensive feature vector to obtain a pure sparse feature vector. Next, based on a preset priority coding tree, sparse feature extraction is performed on the pure sparse feature vector to obtain a feature extraction result. Finally, based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and a preset message structure, the feature extraction result is processed to obtain a target high-bandwidth utilization aggregated message. This achieves hardware-level compression and cleaning of massive quantum error correction syndrome data streams, thereby reducing the bandwidth requirements of the measurement and control data link bus. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the method provided in the embodiments of this application; Figure 2 This is a block diagram of a real-time edge preprocessing and high-density compression architecture for quantum error correction syndrome provided in an embodiment of this application; Figure 3 This is a schematic diagram of the compression rate-error rate curve of the extraction operation data provided in the embodiments of this application; Figure 4 A schematic diagram of the compression ratio-message page size curve provided for embodiments of this application; Figure 5 A schematic diagram of the error correction delay-message page size curve provided for embodiments of this application; Figure 6 This is a schematic diagram of the device provided in the embodiments of this application; Figure 7 This is a schematic diagram of the terminal structure provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] As the number of qubits expands to hundreds or even thousands, the measurement and control system faces extremely serious problems: existing instruments typically package the entire array of raw 0 / 1 states for each measurement cycle and upload it to the host computer via a backplane bus (such as PXIe) or network. This O(N) complexity (N is the number of bits) data stream contains a great deal of redundancy and can easily exhaust the system's physical bandwidth; quantum error correction graph matching algorithms (such as MWPM) do not care about absolute 0 or 1 states, but rather about the "flipping" of states in the time dimension. Before executing the core decoding algorithm, the host computer CPU must consume a large number of clock cycles to perform memory-intensive operations such as unpacking, buffering, and bitwise XORing of massive amounts of messages, resulting in closed-loop feedback latency jitter, which seriously threatens the coherence of quantum states; thermal noise or physical degradation of bits in the measurement and control link can lead to frequent "pseudo-flips". If all of this data is reported to the host computer, it will exponentially increase the pathfinding complexity of the decoding algorithm.

[0020] Therefore, this application provides a method, apparatus, terminal, and medium for processing quantum error correction syndrome data streams to solve practical technical problems.

[0021] In some embodiments, the device may be integrated into an electronic device, such as a terminal or server.

[0022] In some embodiments, the server may also be implemented as a terminal.

[0023] The server can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms.

[0024] The terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, etc., but is not limited to these. The terminal and the server can be connected directly or indirectly through wired or wireless communication, which is not limited herein.

[0025] The following sections provide detailed descriptions of each example. It should be noted that the sequence numbers of the following embodiments are not intended to limit the preferred order of the embodiments.

[0026] A method for processing quantum error correction syndrome data streams is proposed, which enables hardware-level compression and cleaning of massive quantum error correction syndrome data streams to reduce the bandwidth requirements of the measurement and control data link bus.

[0027] In some embodiments, the method is applied to a processing system deployed in an FPGA of a measurement and control instrument.

[0028] like Figure 1 The specific process of the method can be as follows: S110. Based on the aligned state data corresponding to the measurement and control instrument, a comprehensive feature vector is obtained, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream.

[0029] In some embodiments, the aligned state data corresponding to the measurement and control instrument includes a global measurement vector.

[0030] Specifically, the process of obtaining the comprehensive feature vector based on the aligned state data corresponding to the measurement and control instrument includes the steps A1 to A2 shown below: A1. A set of high-speed registers is allocated inside the FPGA to cache the global measurement vector of the previous measurement cycle; In some embodiments, the global measurement vector output by the measurement and control instrument is first received. This vector is after front-end RF link threshold judgment and cross-clock domain synchronization alignment. Bit-width binary vector, where This is the global timestamp for the current measurement period. This represents the total number of auxiliary bits currently controlled by the measurement and control instrument. Each element in the vector takes a value of 0 or 1, corresponding to the measurement status of a single auxiliary bit. A high-speed register group with a width identical to the global measurement vector is allocated within the FPGA, specifically for caching the global measurement vector from the previous measurement cycle. This ensures that when the current period's data arrives, historical data can be immediately used in the calculation.

[0031] A2. Perform a bitwise Boolean XOR operation on the global measurement vector and the global measurement vector of the previous measurement cycle to obtain the comprehensive feature vector.

[0032] In some embodiments, calling the FPGA Two parallel-input XOR gates perform bitwise Boolean XOR operations synchronously on a single rising edge of the clock. The operation logic is as follows:

[0033] The result of the calculation is the comprehensive feature vector. When each element in the vector takes a value of 0, it indicates that the corresponding auxiliary bit has not flipped its state in the current period compared to the previous period; when it takes a value of 1, it indicates that the corresponding auxiliary bit has flipped its state. This vector fully characterizes the auxiliary bit state flipping events in the time dimension of the quantum error correction syndrome data stream.

[0034] S120. Based on a preset health threshold, the comprehensive feature vector is subjected to dead bit filtering to obtain a pure sparse feature vector.

[0035] In some embodiments, the step of filtering out dead bits from the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector includes the steps B1 to B4 shown below: B1. Based on the channel dimension of the comprehensive feature vector, instantiate a behavior history shift register for the auxiliary bit to obtain the historical flip data corresponding to the auxiliary bit, wherein the behavior history shift register is used to record the flip history of the auxiliary bit.

[0036] In some embodiments, for the comprehensive feature vector For each channel, instantiate a channel with a depth of [depth value]. Behavior history shift register The observation window depth is configurable and can be adjusted according to the noise characteristics of the actual measurement and control scenario. Each behavior history shift register continuously records the past behavior of the corresponding auxiliary bit. The time-dimensional state flip event values ​​of each measurement period form the historical flip data of this auxiliary bit.

[0037] B2. Perform a weighted integral calculation on the historical flip data corresponding to the auxiliary bit to obtain the noise penalty score corresponding to the channel.

[0038] In some embodiments, the step of performing a weighted integral calculation on the historical flipped data corresponding to the auxiliary bit to obtain the noise penalty score corresponding to the channel includes the following specific implementation process: The noise penalty score is calculated using the following formula:

[0039] in, This represents the noise penalty score. Indicates the number of measurement cycles. Indicates the number of auxiliary bits. This indicates the depth corresponding to the behavior history shift register. This indicates the preset weighting coefficient. It is typically configured to give higher weights to recent events and lower weights to older events, in order to more sensitively reflect the current noise state of the channel. Indicates the first in the historical flipped data The auxiliary bit in the first The time dimension state flip event value for each measurement period This represents the time offset within the sliding window corresponding to the measurement period. The value range is 0 to .

[0040] B3. Based on the comparison result between the noise penalty score and the preset health threshold, generate a fully auxiliary bit mask vector.

[0041] In some embodiments, the fully auxiliary bit mask vector includes mask bits.

[0042] Specifically, the step of generating a fully auxiliary bitmask vector based on the comparison result between the noise penalty score and the preset health threshold includes the following specific implementation process: If the noise penalty score is less than or equal to the preset health threshold, the auxiliary bit signal is determined to be healthy, and a mask bit with a value of 1 is generated; if the noise penalty score is greater than the preset health threshold, the auxiliary bit is determined to be a dead bit, and a mask bit with a value of 0 is generated.

[0043] Specifically, preset health thresholds are set in advance. This threshold can be dynamically configured based on the physical characteristics of the qubits and the system's fault tolerance requirements. Noise penalty fractions are applied channel by channel. With preset health threshold Comparison: If ≤ Determine if the auxiliary bit signal is healthy, and generate a mask bit with a value of 1; if > The auxiliary bit is determined to be a dead bit, and a mask bit with a value of 0 is generated. The mask bits of all channels are concatenated sequentially to form a length of... Fully auxiliary bit mask vector .

[0044] B4. Based on the fully auxiliary bit mask vector, perform bit-silencing processing on the comprehensive feature vector to obtain the pure sparse feature vector.

[0045] In some embodiments, call The parallel AND gates will synthesize the feature vectors. With full auxiliary bit mask vector Perform a bitwise AND operation to silence the bits. See below:

[0046] The result of the operation is the pure sparse feature vector. The pseudo-flip events corresponding to the high-noise dead bits in this vector have been completely filtered out, and only the true flip events of the healthy channels are retained.

[0047] S130. Based on the preset priority coding tree, perform sparse feature extraction processing on the pure sparse feature vector to obtain the feature extraction result.

[0048] In some embodiments, the sparse feature extraction process performed on the pure sparse feature vector based on a preset priority coding tree to obtain the feature extraction result includes the steps C1 to C2 shown below: C1. Using the pure sparse feature vector as input, scan all valid bits with a value of 1 from bottom to top through a preset priority coding tree to obtain the binary address index corresponding to the valid bits. The binary address index includes the binary address corresponding to the valid bits and the index value corresponding to the auxiliary bits that have been flipped.

[0049] In some embodiments, a preset priority encoding tree is pre-constructed. This logic tree consists of cascaded multiplexers and priority encoders, supporting fully parallel fast scanning. A clean, sparse feature vector is input into the preset priority encoding tree. The logic tree traverses all bits of the vector from bottom to top, identifying all valid bits with a value of 1. A corresponding binary address index is generated for each valid bit. This index contains the binary address corresponding to the valid bit, i.e., the index value corresponding to the auxiliary bit that has been flipped. The index width is determined by the total number of auxiliary bits. Decision, for example when When the value is 1024, the index width is 10 bits.

[0050] C2. Based on the binary address index, compare the number of auxiliary bits that have been flipped with a preset bypass threshold. If the number of auxiliary bits that have been flipped is not greater than the preset bypass threshold, the defect index array is obtained by outputting a preset priority coding tree. If the number of auxiliary bits that have been flipped is greater than the preset bypass threshold, the pure sparse feature vector is obtained by outputting a preset priority coding tree.

[0051] In some embodiments, a counter is used to count the number of auxiliary bits that have flipped during the current period. That is, the total number of binary address indices.

[0052] Preset the default bypass threshold to ,in The bypass threshold coefficient is between 0 and 1, used to determine whether the current flip rate exceeds the optimal range of sparse coding.

[0053] like ≤ This indicates that the current operating condition is normal with a low error rate. The preset priority coding tree outputs all binary address indices in sequence, forming a defect index array; if > This indicates that encountering strong global noise, sparse encoding would actually increase the amount of data. In this case, bypass logic is triggered, directly outputting the pure sparse feature vector. .

[0054] S140. Based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure, the feature extraction results are processed to obtain the target high-bandwidth utilization aggregated message to adapt to the bus transmission process corresponding to the processing system.

[0055] In some embodiments, the feature extraction results are processed based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and a preset message structure to obtain a target high-bandwidth utilization aggregated message, including the steps D1 to D4 as shown below: D1. Based on the bandwidth characteristics, perform word alignment processing on the feature extraction results to obtain the feature extraction results after word alignment processing.

[0056] In some embodiments, based on the memory alignment requirements of a fixed-width block transmission bus, a hardware fixed-length mapping module performs word alignment processing on each index in the feature extraction result. Specifically, the high-order bits of each fixed-length binary address index are padded with zeros to expand it into a standard 16-bit half-word format, avoiding the need for additional shift operations when the back-end host computer reads memory byte by byte, thus improving memory access speed.

[0057] D2. Perform cross-period aggregation processing on the feature extraction results after word alignment processing to obtain aggregated data.

[0058] In some embodiments, a dual-port aggregation FIFO is designed inside the FPGA to buffer the feature extraction results after word alignment processing generated in multiple consecutive cycles. An aggregation page size S and an aggregation timeout timer T are preset. The hardware continuously pushes the feature extraction results from multiple consecutive cycles into the FIFO, sharing a single transmission header, until the amount of data in the FIFO reaches the preset aggregation page size S, or the aggregation timeout timer T times out, at which point aggregation stops and aggregated data is generated.

[0059] D3. Based on the preset message structure, add a large frame header and a subframe header to the aggregated data. The large frame header includes a reference absolute timestamp and a total length, and the subframe header includes a relative clock offset and a valid number of flips.

[0060] In some embodiments, a preset message structure, namely a nested structure of relative timestamps and subframes, is used to encapsulate the aggregated data. First, a large frame header is added, which includes a 16-bit MAGIC_WORD frame start identifier, a 32-bit reference absolute timestamp T0, and a 16-bit total payload length. Then, a subframe header is added for each measurement period with a valid flip event. The subframe header includes an 8-bit / 16-bit relative clock offset (the number of error-free periods skipped from the previous valid period), an 8-bit valid flip count, and the corresponding period's word-aligned feature extraction result immediately following the subframe header.

[0061] D4. Add a CRC32 checksum to the aggregated data to generate the target high bandwidth utilization aggregated message.

[0062] In some embodiments, after encapsulating the large frame header and all subframes, a 32-bit CRC32 checksum is added to the end of the message to verify data integrity during transmission. Finally, a target high-bandwidth utilization aggregated message is generated, triggering the bus controller to initiate a Burst transmission, sending the message to the host computer via a fixed-width block transmission bus, adapting to the bus transmission process of the processing system.

[0063] The method will be further illustrated below through another specific embodiment: An architecture with "data and computing power front-end" is applied to a superconducting quantum surface code error correction scenario that includes 1024 auxiliary bits of measurement. It utilizes the fully parallel computing capability of the FPGA inside the measurement and control instrument to complete the cleaning and compression before the data enters the high-speed bus.

[0064] The specific initial conditions for the scenario are set as follows: System scale: A certain measurement and control instrument board is responsible for the real-time reading of K=1024 auxiliary bits (channel index numbers are 0 to 1023); Measurement cycle: 1µs (i.e., the trigger frequency of the system feature processing pipeline is 1MHz); Physical conditions: The average physical error rate of the quantum bits is p=0.5%, among which channels 42 and 888 are in a high-frequency random flipping and high-noise state due to physical device degradation. The current cycle is n, and the previous cycle in which the flip occurred was n-2, that is, there is one cycle in the middle without effective flipping.

[0065] like Figure 2 As shown, the specific edge processing flow corresponding to the architecture includes the following steps T1 to T4: T1: Generate alignment state (clock cycle) And complete the XOR difference and defect extraction: During this cycle, 1024 channels completed state decisions and alignment. In addition to normal flips, channels 42 and 888, which were experiencing high noise, also experienced spurious flips, and the system register acquired a 1024-bit measurement vector. .

[0066] Hardware will Compared with the previous cycle Perform a 1024-way parallel XOR operation. Result There are 6 positions with a value of 1: channels 12, 42, 105, 512, 888, and 1003.

[0067] T2: Noise-resistant time-domain sliding window filter: The mask vectors of the six flip events are fed into the temporal evaluation module, where they undergo the following processing: Due to the frequent flipping of channels 42 and 888 over the past 16 observation windows, their noise scores... and Exceeded the set threshold .

[0068] The hardware silent gating forces the mask bits of channels 42 and 888 to be set to 0.

[0069] Output effective sparse feature vector In this case, only four true flip bits—12, 105, 512, and 1003—are retained. At this point, the effective flip number is... .

[0070] T3: such as Figure 3 Feature-first encoding: Priority coding tree scanning ,because The index requires 10 bits to represent. The hardware outputs the binary code corresponding to the four decimal values: 0000001100, 0001101001, 1000000000, 1111101011.

[0071] T4: Alignment and Dynamic Message Packaging The hardware pads the high-order bits of the aforementioned 10-bit data with 0s to expand it to 16 bits for memory alignment.

[0072] In aggregated FIFO, for this period Generate micro-messages: DELTA_TIME: 00000001, indicating that one error-free cycle has been skipped since the last valid cycle; DEFECT_COUNT: 00000100, current cycle valid flip count: 4; INDICES_ARRAY: 0000000000001100, 0000000001101001, 0000001000000000, 0000001111101011.

[0073] The specific message structure is shown in Table 1 below: Table 1 Example of message aggregation page structure

[0074] The following comparison between the above-described embodiments of this application and the traditional transparent transmission architecture will further illustrate the technical effects of the embodiments of this application: For traditional pass-through architectures, regardless of whether an error occurs, a fixed 1024 bits of payload data are uploaded per cycle. Including protocol overhead, the data throughput generated by the single-board unit is:

[0075] If this instrument is equipped with 10 boards, the backplane bandwidth will bear 10Gbps of redundant data. In practical applications, this number will increase further. Furthermore, the host computer handles the XOR operation of all data uploaded from the boards, which will increase decoding latency. Using the architecture provided in this application embodiment, in... Under normal operating conditions, an average of 5 valid flips are generated per cycle. Considering word alignment and protocol overhead, the average data volume per cycle is reduced to approximately 128 bits, meaning the data throughput of a single board is:

[0076] Furthermore, if decoding latency allows, increasing the size of the aggregated page can further reduce this throughput, such as... Figure 4 and 5 As shown.

[0077] Therefore, the architecture provided in this application reduces the bandwidth requirement of the measurement and control data link bus by nearly 8 times (compression ratio of 87.5%) while retaining the defect node information required for 100% core quantum error correction and eliminating high-noise dead bits. Furthermore, due to the direct output of aligned memory indexes, the memory loading time of the host computer's pathfinding algorithm is also reduced accordingly.

[0078] In summary, this application provides a method for processing quantum error correction syndrome data streams, enabling hardware-level compression and cleaning of massive quantum error correction syndrome data streams to reduce the bandwidth requirements of the measurement and control data link bus.

[0079] To better implement the above methods, this application also provides a processing device for quantum error correction syndrome data streams. This device can be integrated into an electronic device, such as a terminal or server. The terminal can be a mobile phone, tablet computer, smart Bluetooth device, laptop computer, or personal computer; the server can be a single server or a server cluster composed of multiple servers.

[0080] For example, in this embodiment, the method of this application embodiment will be described in detail by taking the processing device for quantum error correction syndrome data stream specifically integrated into the terminal as an example.

[0081] For example, such as Figure 6 As shown, the quantum error correction syndrome data stream processing device 600 may include a first unit 601, a second unit 602, a third unit 603 and a fourth unit 604; The quantum error correction syndrome data stream processing device 600 is applied to the processing system, which is deployed in the FPGA of the measurement and control instrument; The device includes: The first unit 601 is used to obtain a comprehensive feature vector based on the aligned state data corresponding to the measurement and control instrument, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream; The second unit 602 is used to perform dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector. The third unit 603 is used to perform sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain a defect index array. The fourth unit 604 is used to process the defect index group based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure to obtain the target high bandwidth utilization aggregated message, so as to adapt to the bus transmission process corresponding to the processing system.

[0082] In practice, each of the above units can be implemented as an independent entity or can be arbitrarily combined to be implemented as the same or several entities. For the specific implementation of each of the above units, please refer to the previous method embodiments, which will not be repeated here.

[0083] As can be seen from the above, the embodiments of this application can realize hardware-level compression and cleaning of massive quantum error correction syndrome data streams to reduce the bandwidth requirements of the measurement and control data link bus.

[0084] This application also provides an electronic device, which can be a terminal, a server, or other similar device. The terminal can be a mobile phone, tablet computer, smart Bluetooth device, laptop computer, personal computer, etc.; the server can be a single server or a server cluster composed of multiple servers, etc.

[0085] In some embodiments, the product processing device may also be integrated into multiple electronic devices, such as multiple servers, with multiple servers implementing the quantum error correction syndrome data stream processing method of this application.

[0086] In this embodiment, the electronic device will be described in detail as a terminal, for example, such as... Figure 7 As shown, it illustrates a structural schematic diagram of the terminal 700 involved in an embodiment of this application. Specifically: The terminal 700 may include components such as a processor 701 with one or more processing cores, a memory 702 with one or more media, a power supply 703, an input module 704, and a communication module 705. Those skilled in the art will understand that... Figure 7 The terminal 700 structure shown does not constitute a limitation on the terminal 700, and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 701 is the control center of the terminal 700. It connects various parts of the terminal 700 via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or modules stored in the memory 702, and by calling data stored in the memory 702, thereby providing overall monitoring of the terminal 700. In some embodiments, the processor 701 may include one or more processing cores; in some embodiments, the processor 701 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into the processor 701.

[0087] The memory 702 can be used to store software programs and modules. The processor 701 executes various functional applications and data processing by running the software programs and modules stored in the memory 702. The memory 702 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area can store data created according to the use of the terminal 700, etc. In addition, the memory 702 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 702 may also include a memory controller to provide the processor 701 with access to the memory 702.

[0088] The terminal 700 also includes a power supply 703 that supplies power to the various components. In some embodiments, the power supply 703 can be logically connected to the processor 701 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. The power supply 703 may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0089] The terminal 700 may also include an input module 704, which can be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control.

[0090] The terminal 700 may also include a communication module 705. In some embodiments, the communication module 705 may include a wireless module. The terminal 700 can perform short-range wireless transmission through the wireless module of the communication module 705, thereby providing users with wireless broadband internet access. For example, the communication module 705 can be used to help users send and receive emails, browse web pages, and access streaming media.

[0091] Although not shown, terminal 700 may also include a display unit, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 701 in terminal 700 loads the executable files corresponding to the processes of one or more applications into memory 702 according to the following instructions, and the processor 701 runs the applications stored in memory 702 to realize various functions, as follows: Based on the aligned state data corresponding to the measurement and control instrument, a comprehensive feature vector is obtained, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream; Based on a preset health threshold, the comprehensive feature vector is subjected to dead bit filtering to obtain a pure sparse feature vector. Based on a preset priority encoding tree, sparse feature extraction processing is performed on the pure sparse feature vector to obtain a defect index array; Based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure, the defect index group is processed to obtain the target high bandwidth utilization aggregated message, so as to adapt to the bus transmission process corresponding to the processing system.

[0092] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0093] As can be seen from the above, the embodiments of this application can realize hardware-level compression and cleaning of massive quantum error correction syndrome data streams to reduce the bandwidth requirements of the measurement and control data link bus.

[0094] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be accomplished by instructions, or by instructions controlling related hardware. These instructions can be stored in a medium and loaded and executed by a processor.

[0095] To this end, embodiments of this application provide a medium storing a plurality of instructions, which can be loaded by a processor to execute steps in any of the quantum error correction syndrome data stream processing methods provided in embodiments of this application. For example, the instructions can execute the following steps: Based on the aligned state data corresponding to the measurement and control instrument, a comprehensive feature vector is obtained, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream; Based on a preset health threshold, the comprehensive feature vector is subjected to dead bit filtering to obtain a pure sparse feature vector. Based on a preset priority encoding tree, sparse feature extraction processing is performed on the pure sparse feature vector to obtain a defect index array; Based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure, the defect index group is processed to obtain the target high bandwidth utilization aggregated message, so as to adapt to the bus transmission process corresponding to the processing system.

[0096] The medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0097] According to one aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a medium. A processor of a computer device reads the computer instructions from the medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations of the above embodiments.

[0098] Since the instructions stored in the medium can execute the steps in any of the quantum error correction syndrome data stream processing methods provided in the embodiments of this application, the beneficial effects that any of the quantum error correction syndrome data stream processing methods provided in the embodiments of this application can achieve can be realized, as detailed in the preceding embodiments, and will not be repeated here.

[0099] The above provides a detailed description of the processing method, apparatus, terminal, and medium for quantum error correction syndrome data streams provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for processing quantum error correction syndrome data streams, characterized in that, It is applied to a processing system, which is deployed in the FPGA of the measurement and control instrument; The method includes: Based on the aligned state data corresponding to the measurement and control instrument, a comprehensive feature vector is obtained, wherein the comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream; Based on a preset health threshold, the comprehensive feature vector is subjected to dead bit filtering to obtain a pure sparse feature vector. Based on a preset priority encoding tree, sparse feature extraction processing is performed on the pure sparse feature vector to obtain the feature extraction result; Based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure, the feature extraction results are processed to obtain the target high bandwidth utilization aggregated message to adapt to the bus transmission process corresponding to the processing system. The step of performing dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector includes: Based on the channel dimension of the comprehensive feature vector, a behavior history shift register is instantiated for the auxiliary bit to obtain the historical flip data corresponding to the auxiliary bit, wherein the behavior history shift register is used to record the flip history of the auxiliary bit; The noise penalty score for the channel is obtained by performing a weighted integral on the historical flipped data corresponding to the auxiliary bit. Based on the comparison result between the noise penalty score and the preset health threshold, a fully auxiliary bit mask vector is generated; Based on the fully auxiliary bit mask vector, the comprehensive feature vector is bit-silenced to obtain the pure sparse feature vector. The feature extraction result is either a defect index array or a pure sparse feature vector; The step of performing sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain feature extraction results includes: Using the pure sparse feature vector as input, all valid bits with a value of 1 are scanned from bottom to top through a preset priority coding tree to obtain the binary address index corresponding to the valid bits. The binary address index includes the binary address corresponding to the valid bits and the index value corresponding to the auxiliary bits that have been flipped. Based on the binary address index, the number of auxiliary bits that have been flipped is compared with a preset bypass threshold. If the number of auxiliary bits that have been flipped is not greater than the preset bypass threshold, the defect index array is obtained by outputting a preset priority coding tree. If the number of auxiliary bits that have been flipped is greater than the preset bypass threshold, the pure sparse feature vector is obtained by outputting a preset priority coding tree.

2. The method as described in claim 1, characterized in that, The aligned state data corresponding to the measurement and control instrument includes a global measurement vector; The comprehensive feature vector obtained based on the aligned state data corresponding to the measurement and control instrument includes: A set of high-speed registers is allocated inside the FPGA to cache the global measurement vector of the previous measurement cycle; The comprehensive feature vector is obtained by performing a bitwise Boolean XOR operation on the global measurement vector and the global measurement vector of the previous measurement cycle.

3. The method as described in claim 1, characterized in that, The step of performing a weighted integral calculation on the historical flipped data corresponding to the auxiliary bit to obtain the noise penalty score corresponding to the channel includes: The noise penalty score is calculated using the following formula: in, This represents the noise penalty score. Indicates the number of measurement cycles. Indicates the number of auxiliary bits. This indicates the depth corresponding to the behavior history shift register. This indicates the preset weighting coefficient. Indicates the first in the historical flipped data The auxiliary bit in the first The time dimension state flip event value for each measurement period This represents the time offset within the sliding window corresponding to the measurement period.

4. The method as described in claim 1, characterized in that, The fully auxiliary bit mask vector includes mask bits; The step of generating a fully auxiliary bitmask vector based on the comparison result between the noise penalty score and the preset health threshold includes: If the noise penalty score is less than or equal to the preset health threshold, the auxiliary bit signal is determined to be healthy, and a mask bit with a value of 1 is generated; If the noise penalty score is greater than the preset health threshold, the auxiliary bit is determined to be a dead bit, and a mask bit with a value of 0 is generated.

5. The method as described in claim 1, characterized in that, The bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure are used to process the feature extraction results to obtain a target high-bandwidth utilization aggregated message, including: Based on the bandwidth characteristics, the feature extraction results are subjected to word alignment processing to obtain the feature extraction results after word alignment processing; The feature extraction results after word alignment are subjected to cross-period aggregation processing to obtain aggregated data; Based on the preset message structure, a large frame header and a subframe header are added to the aggregated data. The large frame header includes a reference absolute timestamp and a total length, and the subframe header includes a relative clock offset and a valid number of flips. A CRC32 checksum is added to the aggregated data to generate the target high bandwidth utilization aggregated message.

6. A processing device for quantum error correction syndrome data stream, characterized in that, It is applied to a processing system, which is deployed in the FPGA of the measurement and control instrument; The device includes: The first unit is used to obtain a comprehensive feature vector based on the aligned state data corresponding to the measurement and control instrument. The comprehensive feature vector is used to characterize the time dimension state flip event of the auxiliary bit of the quantum error correction syndrome data stream. The second unit is used to perform dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector. The step of performing dead bit filtering on the comprehensive feature vector based on a preset health threshold to obtain a pure sparse feature vector includes: Based on the channel dimension of the comprehensive feature vector, a behavior history shift register is instantiated for the auxiliary bit to obtain the historical flip data corresponding to the auxiliary bit, wherein the behavior history shift register is used to record the flip history of the auxiliary bit; The noise penalty score for the channel is obtained by performing a weighted integral on the historical flipped data corresponding to the auxiliary bit. Based on the comparison result between the noise penalty score and the preset health threshold, a fully auxiliary bit mask vector is generated; Based on the fully auxiliary bit mask vector, the comprehensive feature vector is bit-silenced to obtain the pure sparse feature vector. The third unit is used to perform sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain the feature extraction result. The feature extraction result is either a defect index array or a pure sparse feature vector; The step of performing sparse feature extraction processing on the pure sparse feature vector based on a preset priority coding tree to obtain feature extraction results includes: Using the pure sparse feature vector as input, all valid bits with a value of 1 are scanned from bottom to top through a preset priority coding tree to obtain the binary address index corresponding to the valid bits. The binary address index includes the binary address corresponding to the valid bits and the index value corresponding to the auxiliary bits that have been flipped. Based on the binary address index, the number of auxiliary bits that have been flipped is compared with a preset bypass threshold. If the number of auxiliary bits that have been flipped is not greater than the preset bypass threshold, the defect index array is obtained by outputting a preset priority coding tree. If the number of auxiliary bits that have been flipped is greater than the preset bypass threshold, the pure sparse feature vector is obtained by outputting a preset priority coding tree. The fourth unit is used to process the feature extraction results based on the bandwidth characteristics of the fixed-width block transmission bus corresponding to the processing system and the preset message structure to obtain the target high-bandwidth utilization aggregated message, so as to adapt to the bus transmission process corresponding to the processing system.

7. A terminal, characterized in that, The method includes a processor and a memory, the memory storing multiple instructions; the processor loads instructions from the memory to perform the steps of the method as described in any one of claims 1 to 5.

8. A medium, characterized in that, The medium stores a plurality of instructions adapted for loading by a processor to execute the steps of the method according to any one of claims 1 to 5.

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