Pixel circuit and display panel

Abstract

The present application provides a pixel circuit and a display panel. The pixel circuit includes two switching transistors, a scanning line, two driving transistors, a signal source and a light emitting component. Each switching transistor has a channel, the gate-source voltage difference of each switching transistor has a level interval that makes the corresponding channel conductive, and the two level intervals do not overlap with each other. The scanning line is electrically connected to the gate of each switching transistor to transmit a selection signal, and the selection signal makes the gate-source voltage difference of one of the switching transistors be in its corresponding level interval. Under the saturation operating condition, the transfer characteristic curves of the two driving transistors have different tangent slopes at the same gate-source voltage difference. The signal source and the light emitting component are connected across the two driving transistors, or the light emitting component is connected between the signal source and the two driving transistors.

Description

Technical Field

[0001] This invention relates to a pixel circuit and a display panel, and more particularly to a pixel circuit and a display panel that can improve the brightness contrast performance of a display at low grayscale levels. Background Technology

[0002] Please refer to Figure 1 The curve showing the relationship between the brightness L and grayscale level of the pixel circuit display. Figure 1 In the diagram, the horizontal and vertical axes represent the grayscale values ​​of the integrated circuit (IC) and the corresponding brightness of the light-emitting chips it controls, respectively. Curves 110 to 130 correspond to different gamma values, with curve 110 being the standard gamma value curve (1.0). To improve the brightness difference performance of the display in low grayscale scenes, curves with higher gamma values, such as 120 and 130, are also available. The higher the gamma value setting used by the control IC, the smaller the brightness difference between each grayscale level is compressed, resulting in a more detailed dark-field contrast. However, such control technology places higher demands on the electronic control technology of light-emitting components, such as micro LEDs.

[0003] In actual pixel circuits, the display brightness of the light-emitting components is controlled by voltage. As the luminous efficiency of chips continues to improve, the brightness performance of chips in the low-voltage range has also significantly improved. This means that the voltage controlling the brightness needs to be more densely segmented to accurately represent subtle brightness differences, bringing new challenges to the control capabilities of the control IC. Especially for curves with higher gamma values, the voltage difference corresponding to each gray level in the low grayscale range is further reduced, making voltage calibration of the control IC even more difficult. Summary of the Invention

[0004] This invention relates to a pixel circuit and a display panel that can adjust the driving mode according to the display brightness to optimize the resulting display quality.

[0005] According to an embodiment of the present invention, the pixel circuit includes two switching transistors, a scan line, and two driving transistors. Each of the two switching transistors has a channel, a switching source, and a switching gate. A first level difference between the switching gate and the corresponding switching source has a level range that enables the corresponding channel to conduct, and the level ranges of the two switching transistors do not overlap. The scan line is electrically connected to the gate of each switching transistor and is used to transmit a selection signal, which enables the first level difference of one of the switching transistors to be within its corresponding level range. Each driving transistor has a driving source and a driving gate. Each driving gate is connected to the channel of the corresponding switching transistor, and each driving gate and the corresponding driving source have a second level difference. Under saturation operating conditions, the transfer characteristic curves of the two driving transistors have different tangent slopes corresponding to the same second level difference. The pixel circuit also includes a signal source and a light-emitting component. The signal source is electrically connected to one end of the common connection of the two driving transistors. The light-emitting component is electrically connected to the other end of the common connection of the two driving transistors, or electrically connected between the signal source and the two driving transistors.

[0006] The display panel of the present invention includes a substrate, a plurality of pixel circuits as described above, a plurality of control lines, and a plurality of control units. The control lines are electrically connected between the two channels of two switching transistors in one of the pixel circuits and are used to transmit control signals to two driving gates. Each control unit is electrically connected to a portion of the plurality of pixel circuits and controls the output of selection signals, control signals, and signal sources to these pixel circuits.

[0007] Based on the above, the pixel circuit of the present invention provides two transistors with different electrical characteristics to drive the same light-emitting component. By using driving transistors with different characteristics to drive the light-emitting component, different light emission brightness can be generated. Especially in low brightness conditions, the difficulty of controlling the voltage of the light-emitting component can be effectively reduced, and the dark field contrast performance of the display panel can be improved. Attached Figure Description

[0008] Figure 1 It is a curve showing the relationship between the brightness L of the pixel circuit display and the grayscale level;

[0009] Figure 2 A schematic diagram of a pixel circuit according to an embodiment of the present invention is shown;

[0010] Figure 3 The diagram shows the transfer characteristic curves of the driving transistor according to an embodiment of the present invention;

[0011] Figure 4 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown;

[0012] Figure 5A as well as Figure 5B The waveform diagram of the pixel circuit operation is shown.

[0013] Figure 6 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown;

[0014] Figure 7 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown;

[0015] Figure 8 A schematic diagram of a display panel according to an embodiment of the present invention is shown. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] Please refer to Figure 2 , Figure 2 This diagram illustrates a pixel circuit according to an embodiment of the present invention. The pixel circuit 200 includes switching transistors TA and TB, driving transistors T1 and T2, a storage capacitor C1, a scan line SL, a control line CL, level-holding switches SW1 and SW2, signal sources ELVDD1 and ELVDD2, and a light-emitting component LD. In this embodiment, each switching transistor TA and TB has a channel, a switching source, a switching drain, and a switching gate. The channel of switching transistor TA can be formed between its switching source and switching drain, and the channel of switching transistor TB can be formed between its switching source and switching drain. When the level difference between the switching gate level VgA and the corresponding switching source level VsA of switching transistor TA falls within a first level interval, the channel of switching transistor TA can be turned on. Similarly, when the level difference between the switching gate level VgB and the corresponding switching source level VsB of switching transistor TB falls within a second level interval, the channel of switching transistor TB can be turned on. Furthermore, the first and second level intervals do not overlap.

[0018] In this embodiment, the switching transistor TA and the switching transistor TB can be transistors with different conduction polarities. For example, the switching transistor TA can be a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the switching transistor TB can be an N-type metal-oxide-semiconductor field-effect transistor.

[0019] The scan line SL can be electrically connected to the gate switches of switching transistors TA and TB via a level-holding switch SW1, thereby transmitting the selection signal DSL to the gate switches of switching transistors TA and TB. The control line CL can be electrically connected to the two channels of switching transistors TA and TB via a level-holding switch SW2, thereby transmitting the control signal DCL to the channel of switching transistors TA and TB.

[0020] Storage capacitor C1 can be coupled between the switching gates of switching transistors TA and TB and the reference ground terminal VSS. In this embodiment, the switching gates of switching transistors TA and TB are coupled to each other. Storage capacitor C1 is used to maintain the level VC1 generated by the switching gates of switching transistors TA and TB based on the received selection signal DSL. In this embodiment, the level holding switch SW1 can be constructed by transistor T3. The channel of transistor T3 can be turned on or off according to the timing signal Sn-1. When the channel of transistor T3 is turned on, the selection signal DSL can be transmitted to the switching gates of switching transistors TA and TB, charging storage capacitor C1. When the level VC1 on storage capacitor C1 is equal to the level of the selection signal DSL, the channel of transistor T3 can be turned off according to the timing signal Sn-1.

[0021] Each driving transistor T1 and T2 may have a driving source, a driving drain, and a driving gate. The driving gate of driving transistor T1 is connected to the channel of switching transistor TA; the driving gate of driving transistor T2 is connected to the channel of switching transistor TB. There may be a voltage level difference between the driving gates and corresponding driving sources of each driving transistor T1 and T2. When driving transistors T1 and T2 operate in the saturation region, for the same voltage level difference, the transfer characteristic curves of driving transistors T1 and T2 have different tangent slopes. For example... Figure 3 The transfer characteristic curves of the driving transistor in an embodiment of the present invention are shown in the diagram. Figure 3 In the diagram, the horizontal axis represents the voltage difference VGS between the driving gate and the corresponding driving source, and the vertical axis represents the current of the driving drain. When driving transistor T1 operates in the saturation region, the corresponding transfer characteristic curve is 310; when driving transistor T2 operates in the saturation region, the corresponding transfer characteristic curve is 320.

[0022] Specifically, when corresponding to the same level difference VGS between the driving gate and the driving source, transfer characteristic curves 310 and 320 have significantly different tangent slopes. In this embodiment of the invention, when corresponding to the same level difference VGS between the driving gate and the driving source, the absolute value of the first slope of the tangent of the transfer characteristic curve 310 of driving transistor T1 can be lower than the absolute value of the second slope of the tangent of the transfer characteristic curve 320 of driving transistor T2. The second slope can be more than twice the first slope.

[0023] Please refer to the above again. Figure 2 In this embodiment, the driving sources of driving transistors T1 and T2 can be coupled to signal sources ELVDD1 and ELVDD2, respectively. Signal sources ELVDD1 and ELVDD2 can be the same voltage source (e.g., connected in parallel) or two independent voltage sources. The driving drains of driving transistors T1 and T2 can be coupled to the light-emitting element LD. In this embodiment, the light-emitting element LD is, for example, a light-emitting diode (e.g., an organic light-emitting diode, a miniature light-emitting diode, or any other form of light-emitting diode), or a light-emitting diode chip. The anode of the light-emitting element LD can be coupled to the driving drains of driving transistors T1 and T2, and the cathode of the light-emitting element LD is coupled to the reference ground terminal VSS.

[0024] The level-holding switch SW2 can be constructed using transistor T4. The channel of transistor T4 can be turned on or off according to the timing signal Sn. When the channel of transistor T4 is on, the control signal DCL can be transmitted to the channels of switching transistors TA and TB. When the level on the channels of switching transistors TA and TB is equal to the level of the control signal DCL, the channel of transistor T4 can be turned off according to the timing signal Sn.

[0025] In this embodiment, when either the switching transistors TA and TB are turned on, the level equal to that of the control signal DCL can be transmitted to the driving gate of the corresponding driving transistors T1 and T2 through the turned-on switching transistors TA and TB. Taking P-type metal-oxide-semiconductor field-effect transistors T1 and T2 as an example, when the level difference (Vgs) between the driving gate and driving source of either driving transistor T1 or T2 is less than the negative threshold voltage (Vth) of driving transistor T1 or T2, the channel of the corresponding driving transistor T1 or T2 can be turned on.

[0026] The driving transistors T1 and T2, whose channels are turned on, can provide driving levels Vd1 and Vd2 to the light-emitting element LD at their drain terminals, respectively. In this embodiment, driving levels Vd1 and Vd2 can be provided to the anode of the light-emitting element LD to drive it to emit light. Driving levels Vd1 and Vd2 can be equal to signal sources ELVDD1 and ELVDD2, respectively, and driving transistors T1 and T2 are used to write signal sources ELVDD1 and ELVDD2 into the light-emitting element LD.

[0027] Regarding the operational details of the pixel circuit 200, in this embodiment, the level-holding switch SW1 can be turned on before the level-holding switch SW2. Specifically, in the first time interval, the level-holding switch SW1 is turned on first according to the timing signal Sn-1, and is used to transmit the selection signal DSL to the switching gates of the switching transistors TA and TB. By charging the storage capacitor C1, the voltage levels VgA and VgB on the switching gates of the switching transistors TA and TB are both equal to the level of the selection signal DSL. Therefore, only one of the switching transistors TA and TB, which have non-overlapping conductable voltage levels, can be turned on, while the other remains off.

[0028] In this embodiment of the invention, when the target luminance of the light-emitting component LD is a relatively low first grayscale, the scanning line SL can turn on the switching transistor TA by transmitting the selection signal DSL during the first time interval. Conversely, when the target luminance of the light-emitting component LD is a relatively high second grayscale, the scanning line SL can turn on the switching transistor TB by transmitting the selection signal DSL during the first time interval.

[0029] In terms of design, the absolute values ​​of the threshold voltages of the switching transistors TA and TB can be made to be the same (but with different signs). This prevents the threshold voltages of the switching transistors TA and TB from overlapping due to drift in process parameters.

[0030] Incidentally, in this embodiment of the invention, a grayscale threshold can be preset. When the target luminance of the light-emitting component LD is not higher than the grayscale threshold, the channel of the switching transistor TA can be turned on; when the target luminance of the light-emitting component LD is higher than the grayscale threshold, the channel of the switching transistor TB can be turned on.

[0031] In the second time interval following the first time interval, switch SW2 can be turned on according to the timing signal Sn. The turned-on switch SW2 transmits the control signal DCL to the source of the coupled switching transistor TA and the drain of the switching transistor TB, making the level VsA at the source and the level VdB at the drain equal to the level of the control signal DCL. When switching transistor TA is turned on, the level on the drive gate of driving transistor T1 can be substantially equal to level VsA. When switching transistor TB is turned on, the level on the drive gate of driving transistor T2 can be substantially equal to level VdB. Thus, driving transistors T1 and T2 can determine the generated drive levels Vd1 and Vd2 respectively based on the levels on their drive gates, and drive the light-emitting element LD to emit light.

[0032] In other words, after the grayscale is determined based on the aforementioned threshold, the selection signal DSL determines whether the channel of the switching transistor TA or TB is turned on. Then, the voltage of the control signal DCL is determined by the grayscale of the target luminous intensity to be generated by the pixel circuit 200, and the level VgA (or VgB) of the gate of the currently turned-on switching transistor TA (or switching transistor TB). Specifically, when the grayscale of the target luminous intensity to be generated by the pixel circuit 200 falls within a lower first grayscale range, the pixel circuit 200 controls the channel of the switching transistor TA to be turned on according to the selection signal DSL, and controls the luminous intensity of the light-emitting component LD by driving transistor T1 according to the voltage of the control signal DCL. Conversely, when the grayscale of the target luminous intensity to be generated by the pixel circuit 200 falls within a higher second grayscale range, the channel of the switching transistor TB is turned on, and the driving transistor T2 controls the luminous intensity of the light-emitting component LD according to the voltage of the control signal DCL.

[0033] In this embodiment, taking a grayscale level of 256 levels as an example, the first grayscale range can be set between 0 and 100, and the second grayscale range can be set between 101 and 255. In this case, the grayscale level of the second grayscale range is approximately 1.5 times that of the first grayscale range. Alternatively, in other embodiments, the first grayscale range can be set between 0 and 64, and the second grayscale range can be set between 65 and 255. In this case, the grayscale level of the second grayscale range is 3 times that of the first grayscale range.

[0034] Please refer to Figure 4 , Figure 4 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. Pixel circuit 400 includes switching transistors TA and TB, driving transistors T1 and T2, storage capacitor C1, scan line SL, control line CL, level holding switches SW1 and SW2, signal sources ELVDD1 and ELVDD2, and light-emitting component LD. Pixel circuit 400 includes the same circuit components as pixel circuit 200, wherein the identical parts will not be described in detail. The difference from the previous embodiment is that in pixel circuit 400, scan line SL and control line CL share the same line. Under such conditions, selection signal DSL and control signal DCL can be transmitted through the above-mentioned shared line, via timing signals Sn-1 and Sn with different time intervals, respectively, when switches SW1 and SW2 are turned on.

[0035] For details regarding the operation of pixel circuit 400, please refer to [link / reference]. Figure 5A as well as Figure 5B . Figure 5A as well as Figure 5B The waveform diagram of the pixel circuit operation is shown. Figure 5A In the first time interval, the timing signal Sn-1 can be enabled and provides a positive pulse PS1. Correspondingly, switch SW1 is turned on, and the selection signal DSL provided on the scan line SL is transmitted to capacitor C1. When the selection signal DSL is at a relatively high level V2, the level VC1 on capacitor C1 is charged to level V2. Conversely, when the selection signal DSL is at a relatively low level V1, the level VC1 on capacitor C1 can be equal to level V1. Since the selection gates of switching transistors TA and TB are both coupled to capacitor C1, the switching gate levels VgA and VgB of switching transistors TA and TB can be the same as the level VC1.

[0036] Taking switching transistors TA and TB as examples, which are P-type and N-type metal-oxide-semiconductor field-effect transistors respectively. Here, when the voltage level VC1 on capacitor C1 is a relatively high level V2, switching transistor TB can be turned on. Conversely, when the voltage level VC1 on capacitor C1 is a relatively low level V1, switching transistor TA can be turned on.

[0037] Next, in Figure 5B In the second time interval, the timing signal Sn can be enabled and provide another positive pulse PS2. Correspondingly, switch SW2 is turned on, and the control signal DCL provided on control line CL is transmitted to the channel of switching transistor TA or TB.

[0038] Next, if the channel of switching transistor TA is in the ON state, switching transistor TA can provide the voltage level VsA at its switching source to the driving gate of driving transistor T1, causing driving transistor T1 to generate a corresponding driving signal Vd1 to drive the light-emitting component LD. If the channel of switching transistor TB is in the ON state, switching transistor TB can provide the voltage at its switching drain VdB to the driving gate of driving transistor T2, causing driving transistor T2 to generate a corresponding driving signal Vd2 to drive the light-emitting component LD. The driving signals Vd1 and Vd2 can be equal to signal sources ELVDD1 and ELVDD2, respectively. Signal sources ELVDD1 and ELVDD2 can be the same or different.

[0039] Please refer to the following: Figure 6 , Figure 6A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. Pixel circuit 600 includes switching transistors TA and TB, driving transistors T1 and T2, storage capacitor C1, scan line SL, control line CL, level holding switches SW1 and SW2, signal source ELVDD, and light-emitting component LD. Pixel circuit 600 has a similar circuit architecture to pixel circuit 200, and the same parts will not be described again here. Unlike the previous embodiment, pixel circuit 600 in this embodiment has only a single signal source ELVDD, which is simultaneously coupled to the driving sources of driving transistors T1 and T2.

[0040] Please refer to the following: Figure 7 , Figure 7 A schematic diagram of a pixel circuit according to another embodiment of the present invention is shown. Pixel circuit 700 includes switching transistors TA and TB, driving transistors T1 and T2, storage capacitor C1, scan line SL, control line CL, level holding switches SW1 and SW2, signal source ELVDD, and light-emitting component LD. Pixel circuit 600 has a similar circuit architecture to pixel circuit 700, and the same parts will not be described again here. Unlike the previous embodiment, in this embodiment, driving transistors T1 and T2 are N-type metal-oxide-semiconductor field-effect transistors, and the anode of the light-emitting component LD in pixel circuit 700 is coupled to the signal source ELVDD, while the cathode of the light-emitting component LD is coupled to the driving drain of driving transistors T1 and T2, which are coupled to each other. The driving sources of driving transistors T1 and T2 are jointly coupled to the reference ground terminal VSS.

[0041] It is worth noting that in the embodiments of the present invention, the switching transistors TA and TB can be implemented using transistors of different conduction types. Furthermore, in addition to enhancement-type transistors, at least one of the switching transistors TA and TB can also be a depletion-type transistor.

[0042] The types of switching transistors TA and TB are shown in the table below:

[0043] combination Switching transistor TA Switching transistor TB 1 N-type, enhanced P-type, vacancy type 2 P-type, enhanced N-type, vacancy type 3 N-type, enhanced P-type, enhanced 4 N-type, vacancy type N-type, vacancy type

[0044] In the configurations of combinations 1 and 2 above, the switching transistors TA and TB are enhancement-mode and depletion-mode, respectively. Assuming that switching transistors TA and TB have the same absolute threshold voltage value Vth, the voltage variation between the selected signal DSL transmitted to different pixel circuits can be reduced. Specifically, in combination 1, the conditions for switching transistors TA and TB to be turned on are that the gate-source voltage difference is greater than Vth and less than Vth, respectively; while in combination 2, the above conditions become less than -Vth and greater than -Vth, respectively. Therefore, the above configurations allow the voltage level of the selected signal DSL to be within the same polarity range, and one of the switching transistors TA and TB can still be turned on, simplifying the control circuit of the selected signal DSL. For example, in combination 1, the level of the selected signal DSL can be controlled to be 0 volts (i.e., off) or greater than Vth, thus turning on switching transistors TB and TA respectively.

[0045] Please refer to Figure 8 , Figure 8 A schematic diagram of a display panel according to an embodiment of the present invention is shown. The display panel 800 includes a plurality of pixel circuits 811-814 and a plurality of control units 821, 822. The pixel circuits 811-814 are arranged in a pixel array. Pixel circuits 811, 813 in the same row are coupled to scan line SL1 and control line CL1, and pixel circuits 812, 814 in another row are coupled to scan line SL2 and control line CL2. Pixel circuits 811, 812 in the same column receive timing signals Sn-1 and Sn, and pixel circuits 813, 814 in another column receive timing signals Sn+1 and Sn+2. Each of the pixel circuits 811-814 can be implemented using the pixel circuits of the foregoing embodiments, and the relevant details are not described here.

[0046] Control unit 821 is coupled to pixel circuits 811 and 812, and control circuit 822 is coupled to pixel circuits 813 and 814. Control circuits 821 and 822 can be used to execute timing control actions for the display panel's display operations. In this embodiment, control circuit 821 can generate a selection signal DSL1 and a control signal DCL1 according to the target luminance of each pixel circuit 811 and 812. Control circuit 822 can provide a selection signal DSL2 and a control signal DCL2 to pixel circuits 813 and 814 according to timing signals Sn+1 and Sn+2.

[0047] In this embodiment, the control units 821 and 822 can be constructed using digital circuits, and there are no specific limitations on the details of their circuit architecture.

[0048] In summary, the pixel circuit of this invention selects different switching transistors based on low and high grayscale levels, thereby switching between two driving transistors with different transfer characteristic curves. In this way, the pixel circuit can still achieve subtle voltage control for low grayscale display requirements, thereby improving the dark-field contrast performance of the display panel.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pixel circuit, comprising: Two switching transistors, each of the switching transistors having a channel, a switching source, and a switching gate, wherein a first level difference between each switching gate and the corresponding switching source has a level range that enables the corresponding channel to conduct, and the two level ranges of the two switching transistors do not overlap with each other. The scanning line is electrically connected to the switching gate of each of the switching transistors and is used to transmit a selection signal, wherein the selection signal causes one of the two first level differences to be within its corresponding level range. as well as Two driving transistors, each driving transistor having a driving source and a driving gate, each driving gate being connected to the channel of a corresponding switching transistor, and each driving gate and its corresponding driving source having a second voltage level difference. Under saturation operating conditions, the transfer characteristic curves of the two driving transistors have different tangent slopes corresponding to the same second level difference; At least one signal source is electrically connected to one end of the driving transistor described above; as well as The light-emitting component is electrically connected to the other end of the two driving transistors, or electrically connected between the signal source and the ends of the two driving transistors.

2. The pixel circuit according to claim 1, wherein the signal source comprises: Two voltage sources are respectively coupled to the terminals of the two driving transistors.

3. The pixel circuit according to claim 1, further comprising: A storage capacitor is coupled between the switching gate of the two switching transistors and a reference ground terminal, and the storage capacitor is used to maintain the level of the selection signal on the two switching gates.

4. The pixel circuit according to claim 3 further includes: At least one level-holding switch is used to transmit the selection signal when it is turned on and to be turned off when the level on the storage capacitor is equal to the level of the selection signal.

5. The pixel circuit according to claim 1, further comprising: A control circuit is coupled between the two channels of the two switching transistors to transmit control signals to the two driving gates.

6. The pixel circuit according to claim 5, wherein the control circuit and the scanning circuit are the same circuit.

7. The pixel circuit of claim 1, wherein the two switching transistors have the same absolute threshold voltage value.

8. The pixel circuit according to claim 1, wherein one of the two switching transistors is a P-type metal-oxide-semiconductor field-effect transistor and the other is an N-type metal-oxide-semiconductor field-effect transistor.

9. The pixel circuit according to claim 1, wherein one of the two switching transistors is an enhancement-mode metal-oxide-semiconductor field-effect transistor, and the other is a depletion-mode metal-oxide-semiconductor field-effect transistor.

10. The pixel circuit according to claim 1, wherein the selection signal controls the first level difference corresponding to the two channels to be turned on to have the same polarity, or one of the first level differences is zero.

11. The pixel circuit of claim 1, wherein the two driving transistors are divided into a first driving transistor and a second driving transistor, and during the period when the light-emitting component is enabled, only one of the first driving transistor and the second driving transistor receives a control signal from the correspondingly connected channel and is turned on, such that the signal source is written to the light-emitting component.

12. The pixel circuit according to claim 11, wherein the tangent slope of the first driving transistor is a first slope, the tangent slope of the second driving transistor is a second slope, and the absolute value of the second slope is greater than the absolute value of the first slope; wherein the signal source is written to the light-emitting component via the first driving transistor or the second driving transistor, causing the light-emitting component to emit light based on a first grayscale range or a second grayscale range, and the grayscale of the second grayscale range is higher than the grayscale of the first grayscale range.

13. The pixel circuit according to claim 12, wherein the grayscale level of the second grayscale range is more than 1.5 times the grayscale level of the first grayscale range; The pixel circuit of claim 12, wherein the absolute value of the second slope is more than twice the absolute value of the first slope.

14. A display panel, comprising: substrate; Multiple pixel circuits as described in claim 1; Multiple control lines are electrically connected between the two channels of the two switching transistors in one of the pixel circuits, and are used to transmit a control signal to the two driving gates. as well as Multiple control units, each of which is electrically connected to a portion of the multiple pixel circuits, and controls the output of the multiple selection signals, the multiple control signals, and the multiple signal sources.

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