Low-power-consumption and high-reliability under-voltage protection circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUIZHOU ZHENHUA FENGGUANG SEMICON
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-05
Smart Images
Figure CN122159142A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of undervoltage protection circuit technology, and specifically relates to a low-power, high-reliability undervoltage protection circuit. Background Technology
[0002] In the field of analog integrated circuits, undervoltage in chip power supply circuits often leads to malfunctions in the internal components, resulting in internal logic errors and posing a risk of burning out the chip and the entire circuit system. Therefore, it is necessary to incorporate undervoltage protection circuitry into the chip power supply circuit to shut down the chip when undervoltage occurs, preventing damage due to undervoltage.
[0003] See Figure 6 Traditional undervoltage protection circuits typically use resistor dividers to sample the supply voltage, compare the sampled voltage V1 with the reference voltage VREF, and when V1 is less than VREF, undervoltage occurs, the UVLO output jumps from low to high, and the UVLO signal is input to the chip control circuit to shut down the chip.
[0004] As can be seen from the traditional undervoltage protection circuit topology, the use of resistor-based voltage divider sampling is problematic in practical designs. Temperature drift and manufacturing process errors in the resistors can cause significant drift in the protection point and hysteresis, resulting in poor circuit stability. This structure also has high static power consumption; reducing power consumption requires increasing the resistors in the voltage divider network, which increases the chip area. Furthermore, traditional undervoltage protection circuits use comparators for logic control, and the comparator's offset error and propagation delay can affect the speed and accuracy of undervoltage shutdown. Summary of the Invention
[0005] In view of the above problems, this application proposes a low-power, high-reliability undervoltage protection circuit. It can effectively reduce the temperature drift of resistors in the circuit to improve the reliability of the undervoltage point. At the same time, it eliminates the effects of comparator offset error and propagation delay, improving the speed and accuracy of undervoltage shutdown.
[0006] This application provides a low-power, high-reliability undervoltage protection circuit, including:
[0007] Bias circuit, power supply voltage detection circuit, hysteresis generation circuit and undervoltage control circuit;
[0008] The bias circuit is connected to the input terminal of the power supply voltage detection circuit. The bias circuit is used to mirror the externally generated positive temperature coefficient PTAT current source to the power supply voltage detection circuit and the undervoltage control circuit as bias current.
[0009] The output terminal of the power supply voltage detection circuit is connected to the input terminal of the hysteresis generation circuit. The power supply voltage detection circuit is used to detect the power supply voltage. According to the set undervoltage point and undervoltage recovery point voltage, when the detected power supply voltage reaches the set voltage, the signal is transmitted to the undervoltage control circuit.
[0010] The output terminal of the hysteresis generation circuit is connected to the input terminal of the undervoltage control circuit to prevent the undervoltage protection circuit from being falsely triggered near the flip threshold.
[0011] The output of the undervoltage control circuit is used to acquire the power supply voltage detection signal. When an undervoltage signal is detected, the output undervoltage control signal undergoes a level flip.
[0012] Preferably, the bias circuit includes:
[0013] First current source IB1, first N-channel transistor MN1, and second N-channel transistor MN2;
[0014] The input terminal of the first current source IB1 is connected to the power supply VDD, the output terminal of the first current source IB1 is connected to the drain of the first N transistor MN1, and the drain of the first N transistor MN1 is connected to the gate.
[0015] The drain and gate of the first N-transistor MN1 are also connected to the gate of the second N-transistor MN2 to form a current mirror;
[0016] The sources of the first N-channel transistor MN1 and the second N-channel transistor MN2 are grounded.
[0017] Preferably, the bias circuit further includes:
[0018] First P-tube MP1 and sixth P-tube MP6
[0019] The source of the first P-tube MP1 is connected to the power supply, and the gate and drain of the first P-tube MP1 are connected and connected to the source of the sixth P-tube MP6.
[0020] The gate and drain of the first P-type transistor MP1 are connected and serve as the first gate output terminal of the bias circuit.
[0021] The gate and drain of the sixth P-transistor MP6 are connected and serve as the second gate output of the bias circuit;
[0022] The drain of the sixth P-type transistor MP6 is connected to the drain of the second N-type transistor MN2.
[0023] Preferably, the power supply voltage detection circuit includes:
[0024] The second P-tube MP2 and the seventh P-tube MP7;
[0025] The source of the second P transistor MP2 is connected to the power supply VDD, the drain of the second P transistor MP2 is connected to the source of the seventh P transistor MP7, and the gate of the second P transistor MP2 is connected to the first gate output terminal of the bias circuit.
[0026] The gate of the seventh P-transistor MP7 is connected to the second gate output terminal of the bias circuit.
[0027] Preferably, the power supply voltage detection circuit further includes:
[0028] Zener diode D1 and second resistor R2;
[0029] The negative terminal of Zener diode D1 is connected to the drain of the seventh P-transistor MP7, and the positive terminal of Zener diode D1 is connected to the first terminal of the second resistor R2.
[0030] The second terminal of the second resistor R2 is grounded.
[0031] Preferably, the hysteresis generation circuit includes:
[0032] The third P-tube MP3, the eighth P-tube MP8, and the third N-tube MN3;
[0033] The source of the third P-tube MP3 is connected to the power supply VDD, the drain of the third P-tube MP3 is connected to the source of the eighth P-tube MP8, and the gate of the third P-tube MP3 is connected to the first gate output terminal of the bias circuit.
[0034] The gate of the eighth P-transistor MP8 is connected to the second gate output terminal of the bias circuit;
[0035] The drain of the eighth P-type transistor MP8 is connected to the drain of the third N-type transistor MN3. The source of the third N-type transistor MN3 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit. The gate of the third N-type transistor MN3 is connected to the output signal UVLO.
[0036] Preferably, the undervoltage control circuit includes:
[0037] The fourth P-tube, MP4, and the ninth P-tube, MP9;
[0038] The source of the fourth P-transistor MP4 is connected to the power supply VDD, the drain of the fourth P-transistor MP4 is connected to the source of the ninth P-transistor MP9, and the gate of the fourth P-transistor MP4 is connected to the first gate output terminal of the bias circuit.
[0039] The gate of the ninth P-transistor MP9 is connected to the second gate output terminal of the bias circuit.
[0040] Preferably, the undervoltage control circuit further includes:
[0041] The fourth N-channel transistor MN4 and the first resistor R1;
[0042] The drain of the fourth N-channel transistor MN4 is connected to the drain of the ninth P-channel transistor MP9.
[0043] The drain of the fourth N-transistor MN4 is connected to its gate, and is also connected to the gate of the fifth N-transistor MN5.
[0044] The source of the fourth N-transistor MN4 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.
[0045] Preferably, the undervoltage control circuit further includes:
[0046] Fifth P-tube MP5, tenth P-tube MP10, and fifth N-tube MN5;
[0047] The source of the fifth P transistor MP5 is connected to the power supply VDD, the drain of the fifth P transistor MP5 is connected to the source of the tenth P transistor MP10, and the gate of the fifth P transistor MP5 is connected to the first gate output terminal of the bias circuit.
[0048] The gate of the tenth P transistor MP10 is connected to the second gate output terminal of the bias circuit, and the drain of the tenth P transistor MP10 is connected to the drain of the fifth N transistor MN5.
[0049] The gate of the fifth N-transistor MN5 is connected to the gate and drain of the fourth N-transistor MN4, and the source of the fifth N-transistor MN5 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit.
[0050] Preferably, the circuit further includes:
[0051] An inverter buffer, the input of which is connected between the drain of the tenth P transistor MP10 and the drain of the fifth N transistor MN5;
[0052] The output terminal of the inverter buffer outputs the signal UVLO.
[0053] The beneficial effects of this application are:
[0054] Based on the above technical solution, by using a power supply voltage detection circuit applied to the undervoltage protection circuit to determine whether the power supply voltage is undervoltage, the undervoltage protection function of the chip can be realized; the purpose of undervoltage protection is achieved through current mirror comparison. The current in this circuit is entirely provided by the mirror bias current, resulting in low and controllable overall power consumption. This solves the contradiction between overall power consumption and chip area caused by resistor voltage division, as well as the unreliability of the undervoltage protection threshold caused by resistor process drift and temperature drift. By introducing mutual compensation between positive temperature coefficient (PTAT) current and negative temperature coefficient (NTC) resistors, the temperature drift of resistors in the circuit can be effectively reduced, thereby improving the reliability of the undervoltage point. The fast response speed of current mirror comparison eliminates the influence of comparator offset error and propagation delay, improving the speed and accuracy of undervoltage turn-off.
[0055] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description
[0056] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0057] Figure 1 This paper illustrates a low-power, high-reliability undervoltage protection circuit topology according to an embodiment of this application.
[0058] Figure 2 This illustration shows a schematic diagram of one of the simulations based on the 0.18μm BCD process according to an embodiment of this application;
[0059] Figure 3 The diagram shows a second simulation of an embodiment of this application based on the 0.18μm BCD process;
[0060] Figure 4 The simulation transient curves based on the 0.18μm BCD process of the embodiments of this application are shown;
[0061] Figure 5 A schematic diagram of the DC curve simulation based on the 0.18μm BCD process of an embodiment of this application is shown;
[0062] Figure 6 The following diagram illustrates a conventional undervoltage protection circuit topology in the background art of this application. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0064] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.
[0065] This application provides a low-power, high-reliability undervoltage protection circuit. (See also...) Figure 1 ,include:
[0066] Bias circuit, power supply voltage detection circuit, hysteresis generation circuit and undervoltage control circuit;
[0067] The bias circuit is connected to the input terminal of the power supply voltage detection circuit. The bias circuit is used to mirror the externally generated positive temperature coefficient PTAT current source to the power supply voltage detection circuit and the undervoltage control circuit as bias current.
[0068] The output terminal of the power supply voltage detection circuit is connected to the input terminal of the hysteresis generation circuit. The power supply voltage detection circuit is used to detect the power supply voltage. According to the set undervoltage point and undervoltage recovery point voltage, when the detected power supply voltage reaches the set voltage, the circuit opens and transmits the signal to the undervoltage control circuit.
[0069] The output terminal of the hysteresis generation circuit is connected to the input terminal of the undervoltage control circuit to prevent the undervoltage protection circuit from being falsely triggered near the flip threshold.
[0070] The output of the undervoltage control circuit is used to acquire the power supply voltage detection signal. When an undervoltage signal is detected, the output undervoltage control signal undergoes a level flip.
[0071] Specifically, see Figure 1 The bias circuit includes:
[0072] First current source IB1, first N-channel transistor MN1, and second N-channel transistor MN2;
[0073] The input terminal of the first current source IB1 is connected to the power supply VDD, the output terminal of the first current source IB1 is connected to the drain of the first N transistor MN1, and the drain of the first N transistor MN1 is connected to the gate.
[0074] The drain and gate of the first N-transistor MN1 are also connected to the gate of the second N-transistor MN2 to form a current mirror;
[0075] The sources of the first N-channel transistor MN1 and the second N-channel transistor MN2 are grounded.
[0076] The bias circuit further includes:
[0077] First P-tube MP1 and sixth P-tube MP6
[0078] The source of the first P-tube MP1 is connected to the power supply, and the gate and drain of the first P-tube MP1 are connected and connected to the source of the sixth P-tube MP6.
[0079] The gate and drain of the first P-type transistor MP1 are connected and serve as the first gate output terminal of the bias circuit.
[0080] The gate and drain of the sixth P-transistor MP6 are connected and serve as the second gate output of the bias circuit;
[0081] The drain of the sixth P-type transistor MP6 is connected to the drain of the second N-type transistor MN2.
[0082] Specifically, see Figure 1 The first current source IB1 is mirrored by the first P transistor MP1 and the sixth P transistor MP6 to the second P transistor MP2 and the seventh P transistor MP7 in the power supply voltage detection circuit; the third P transistor MP3 and the eighth P transistor MP8 in the hysteresis generation circuit; the fourth P transistor MP4 and the ninth P transistor MP9 in the undervoltage control circuit; and the fifth P transistor MP5 and the tenth P transistor MP10, etc., which are common source and common gate current mirrors, generating bias currents IB2, IB3, IB4, IB5 and IB6. The undervoltage control circuit is activated. The bias current can be set by setting the size of the current mirror MOSFET. For example, in this embodiment, R1=2R2, IB5=IB6=0.5IB3=2IB4.
[0083] Specifically, see Figure 1 The power supply voltage detection circuit includes:
[0084] The second P-tube MP2 and the seventh P-tube MP7;
[0085] The source of the second P transistor MP2 is connected to the power supply VDD, the drain of the second P transistor MP2 is connected to the source of the seventh P transistor MP7, and the gate of the second P transistor MP2 is connected to the first gate output terminal of the bias circuit.
[0086] The gate of the seventh P-transistor MP7 is connected to the second gate output terminal of the bias circuit.
[0087] The power supply voltage detection circuit further includes:
[0088] Zener diode D1 and second resistor R2;
[0089] The negative terminal of Zener diode D1 is connected to the drain of the seventh P-transistor MP7, and the positive terminal of Zener diode D1 is connected to the first terminal of the second resistor R2.
[0090] The second terminal of the second resistor R2 is grounded.
[0091] Specifically, see Figure 1 The hysteresis generation circuit includes:
[0092] The third P-tube MP3, the eighth P-tube MP8, and the third N-tube MN3;
[0093] The source of the third P-tube MP3 is connected to the power supply VDD, the drain of the third P-tube MP3 is connected to the source of the eighth P-tube MP8, and the gate of the third P-tube MP3 is connected to the first gate output terminal of the bias circuit.
[0094] The gate of the eighth P-transistor MP8 is connected to the second gate output terminal of the bias circuit;
[0095] The drain of the eighth P-type transistor MP8 is connected to the drain of the third N-type transistor MN3. The source of the third N-type transistor MN3 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit. The gate of the third N-type transistor MN3 is connected to the output signal UVLO.
[0096] Specifically, see Figure 1 Undervoltage control circuit, including:
[0097] The fourth P-tube, MP4, and the ninth P-tube, MP9;
[0098] The source of the fourth P-transistor MP4 is connected to the power supply VDD, the drain of the fourth P-transistor MP4 is connected to the source of the ninth P-transistor MP9, and the gate of the fourth P-transistor MP4 is connected to the first gate output terminal of the bias circuit.
[0099] The gate of the ninth P-transistor MP9 is connected to the second gate output terminal of the bias circuit.
[0100] The undervoltage control circuit further includes:
[0101] The fourth N-channel transistor MN4 and the first resistor R1;
[0102] The drain of the fourth N-channel transistor MN4 is connected to the drain of the ninth P-channel transistor MP9.
[0103] The drain of the fourth N-transistor MN4 is connected to its gate, and is also connected to the gate of the fifth N-transistor MN5.
[0104] The source of the fourth N-transistor MN4 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.
[0105] The undervoltage control circuit further includes:
[0106] Fifth P-tube MP5, tenth P-tube MP10, and fifth N-tube MN5;
[0107] The source of the fifth P transistor MP5 is connected to the power supply VDD, the drain of the fifth P transistor MP5 is connected to the source of the tenth P transistor MP10, and the gate of the fifth P transistor MP5 is connected to the first gate output terminal of the bias circuit.
[0108] The gate of the tenth P transistor MP10 is connected to the second gate output terminal of the bias circuit, and the drain of the tenth P transistor MP10 is connected to the drain of the fifth N transistor MN5.
[0109] The gate of the fifth N-transistor MN5 is connected to the gate and drain of the fourth N-transistor MN4, and the source of the fifth N-transistor MN5 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit.
[0110] Specifically, see Figure 1 The circuit further includes:
[0111] An inverter buffer, the input of which is connected between the drain of the tenth P transistor MP10 and the drain of the fifth N transistor MN5;
[0112] The output terminal of the inverter buffer outputs the signal UVLO.
[0113] The circuit structure and principle of the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0114] See Figure 1 When the undervoltage protection circuit of this application is working normally, the Zener diode D1 in the embodiment of this specification is broken down, the UVLO output is high, the third N transistor MN3 is turned on, and the source voltage V of the fourth N transistor MN4 and the fifth N transistor MN5 is... NS4 and V NS5 They are respectively:
[0115] V NS4 =IB5×R1;
[0116] V NS5 = (IB3 + IB4 + IB6) × R2;
[0117] At this time, V NS4=IB5×R1 <V NS5 =1.75IB5×R1, at this time the gate-source voltage V of the fourth N transistor MN4 is... NGS4 The gate-source voltage V of the fifth N-transistor MN5 is greater than NGS5 Therefore, the overcurrent capability of the fourth N-transistor MN4 is greater than that of the fifth N-transistor MN5. The drain voltage of the fifth N-transistor MN5 is pulled high, and the output of the inverter buffer circuit UVLO is high. It should be noted that the parameter symbols in this application are all commonly used symbols in the art, for example: V... NS4 In this document, "V" represents voltage, "N" represents N-type MOSFET, "S" represents source, and "4" represents the fourth N-type MOSFET; and so on. This type of parameter will not be described again in the embodiments of this specification.
[0118] When the undervoltage protection circuit of this application experiences an undervoltage event, the Zener diode D1 in the circuit is not broken down, the UVLO output is low, and the source voltage V of the fourth N transistor MN4 is... NS4 As in normal operation, the source voltage V of the fifth N-transistor MN5 is... NS5 for:
[0119] V NS5 =IB6×R2;
[0120] At this time, V NS4 =IB5×R1>V NS5 =0.5IB5×R1, at this time the gate-source voltage V of the fourth N transistor MN4 is... NGS4 The gate-source voltage V of the fifth N transistor MN5 is less than NGS5 Therefore, the overcurrent capability of the fifth N transistor MN5 is greater than that of the fourth N transistor MN4. The drain voltage of the fifth N transistor MN5 is pulled low, and the output of the inverter buffer circuit UVLO is low.
[0121] See Figure 1 In the embodiments of this specification, according to the circuit working principle, the undervoltage protection is achieved by comparing the overcurrent capability of the fourth N transistor MN4 and the fifth N transistor MN5. The overcurrent capability is related to the gate-source voltage of the MOSFET. The fourth N transistor MN4 and the fifth N transistor MN5 form a current mirror, and their gate voltages are equal. Therefore, the overcurrent capability is actually compared by comparing the source voltages of the fourth N transistor MN4 and the fifth N transistor MN5. The reference voltage is VNS4 as analyzed above.
[0122] When the power supply voltage rises from low to high, the circuit is initially in an undervoltage state, and the source voltage V of the fifth N transistor MN5 is... NS5+ for:
[0123] V NS5+ =(IB6+ID+)×R2
[0124] Where ID+ is the leakage current of the Zener diode before breakdown, and when ID+=IB2, V NS5+ =V NS4 =IB5×R1, the positive undervoltage threshold V+ from low to high power supply voltage is:
[0125] V+=V NS5+ +V D+ +V PDS7+ +V PDS2+
[0126] In the above formula, V D+ V is the voltage difference for the Zener diode to break down before breakdown. PDS7+ and V PDS2+ The drain-source voltages of the seventh P-channel transistor MP7 and the second P-channel transistor MP2 are given a current of 0.5IB3. The positive undervoltage threshold V+ is adjusted by setting the current IB6 and the resistance value of the second resistor R2.
[0127] When the power supply voltage drops from high to low, the circuit is initially in a normal state, and the source voltage V of the fifth N transistor MN5 is... NS5- for:
[0128] V NS5- =(IB6+IB4+ID-)×R2
[0129] Where ID- is the leakage current before the Zener diode breaks down, and when ID- = 0.5IB2, V NS5- =V NS4 =IB5×R1, the negative undervoltage threshold V- from high to low power supply voltage is:
[0130] V-=V NS5- +V D- +V PDS7 -+V PDS2-
[0131] In the above formula, V D- V is the voltage difference at which the Zener diode D1 is pre-broken down. PDS7- and V PDS2- The drain-source voltage of the seventh P-channel transistor MP7 and the second P-channel transistor MP2 at a current of 0.25IB3. The negative undervoltage threshold V- is adjusted by setting the currents IB6 and IB4 and the resistance of the second resistor R2.
[0132] Based on the positive and negative flip thresholds, the hysteresis ΔV of undervoltage latch can be obtained as follows:
[0133] △V=V - -V +
[0134] As can be seen from the above analysis, the hysteresis can be set by adjusting the negative undervoltage threshold V- without affecting the positive undervoltage threshold V+ by setting the current IB4.
[0135] As shown in the above formula, the hysteresis ΔV is only related to the bias current IB5 and the second resistor R2, and the hysteresis can be flexibly set.
[0136] See Figure 2 , Figure 3 , Figure 4 and Figure 5 ,in, Figures 2 to 4 This is the transient curve simulated based on the 0.18μm BCD process in this embodiment. Figure 5 This is a DC curve simulated based on a 0.18μm BCD process. In the design, the reverse Zener diode can also be a forward-cascaded Schottky diode to facilitate setting a lower undervoltage lockout threshold. The first resistor R1 and the second resistor R2 are lightly doped poly resistors with a negative temperature coefficient, and a PTAT bias current with a positive temperature coefficient is introduced as temperature drift compensation for the resistors. From... Figure 4 The transient simulation curves show that, under a temperature drift of -55℃ to 125℃, the negative undervoltage protection threshold shifted by 326.4mV and the positive undervoltage protection threshold shifted by 422.8mV. The undervoltage protection threshold drift is greatly improved compared to the traditional circuit structure (drift greater than 1V), indicating that this embodiment has high reliability. Figure 5 The undervoltage protection hysteresis of this embodiment was simulated at temperatures of -55℃, 25℃, and 125℃. The hysteresis values were 157.8mV, 159.2mV, and 160.4mV, respectively. The simulation results show that the hysteresis drift is less than 3mV within the temperature range of -55℃ to 125℃, indicating good stability of the structure of this embodiment. Furthermore, this embodiment can still operate stably with a bias current of 1μA, achieving power consumption below μW, entirely determined by the bias current, which can be adjusted according to design requirements. Traditional architectures require voltage divider resistors of tens of MΩ plus a low-power comparator to achieve μW-level power consumption, resulting in excessively large chip area and reduced reliability. Therefore, this application meets the low-power requirements and offers advantages such as high reliability, simple structural design, and small area.
[0137] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A low-power, high-reliability undervoltage protection circuit, characterized in that, include: Bias circuit, power supply voltage detection circuit, hysteresis generation circuit and undervoltage control circuit; The bias circuit is connected to the input terminal of the power supply voltage detection circuit. The bias circuit is used to mirror the externally generated positive temperature coefficient PTAT current source to the power supply voltage detection circuit and the undervoltage control circuit as bias current. The output terminal of the power supply voltage detection circuit is connected to the input terminal of the hysteresis generation circuit. The power supply voltage detection circuit is used to detect the power supply voltage. According to the set undervoltage point and undervoltage recovery point voltage, when the detected power supply voltage reaches the set voltage, the signal is transmitted to the undervoltage control circuit. The output terminal of the hysteresis generation circuit is connected to the input terminal of the undervoltage control circuit to prevent the undervoltage protection circuit from being falsely triggered near the flip threshold. The output of the undervoltage control circuit is used to acquire the power supply voltage detection signal. When an undervoltage signal is detected, the output undervoltage control signal undergoes a level flip.
2. The circuit according to claim 1, characterized in that, The bias circuit includes: First current source IB1, first N-channel transistor MN1, and second N-channel transistor MN2; The input terminal of the first current source IB1 is connected to the power supply VDD, the output terminal of the first current source IB1 is connected to the drain of the first N transistor MN1, and the drain of the first N transistor MN1 is connected to the gate. The drain and gate of the first N-transistor MN1 are also connected to the gate of the second N-transistor MN2 to form a current mirror; The sources of the first N-channel transistor MN1 and the second N-channel transistor MN2 are grounded.
3. The circuit according to claim 2, characterized in that, The bias circuit further includes: First P-tube MP1 and sixth P-tube MP6 The source of the first P-tube MP1 is connected to the power supply, and the gate and drain of the first P-tube MP1 are connected and connected to the source of the sixth P-tube MP6. The gate and drain of the first P-type transistor MP1 are connected and serve as the first gate output terminal of the bias circuit. The gate and drain of the sixth P-transistor MP6 are connected and serve as the second gate output of the bias circuit; The drain of the sixth P-type transistor MP6 is connected to the drain of the second N-type transistor MN2.
4. The circuit according to claim 2 or 3, characterized in that, The power supply voltage detection circuit includes: The second P-tube MP2 and the seventh P-tube MP7; The source of the second P transistor MP2 is connected to the power supply VDD, the drain of the second P transistor MP2 is connected to the source of the seventh P transistor MP7, and the gate of the second P transistor MP2 is connected to the first gate output terminal of the bias circuit. The gate of the seventh P-transistor MP7 is connected to the second gate output terminal of the bias circuit.
5. The circuit according to claim 4, characterized in that, The power supply voltage detection circuit further includes: Zener diode D1 and second resistor R2; The negative terminal of Zener diode D1 is connected to the drain of the seventh P-transistor MP7, and the positive terminal of Zener diode D1 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is grounded.
6. The circuit according to claim 5, characterized in that, The hysteresis generation circuit includes: The third P-tube MP3, the eighth P-tube MP8, and the third N-tube MN3; The source of the third P-tube MP3 is connected to the power supply VDD, the drain of the third P-tube MP3 is connected to the source of the eighth P-tube MP8, and the gate of the third P-tube MP3 is connected to the first gate output terminal of the bias circuit. The gate of the eighth P-transistor MP8 is connected to the second gate output terminal of the bias circuit; The drain of the eighth P-type transistor MP8 is connected to the drain of the third N-type transistor MN3. The source of the third N-type transistor MN3 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit. The gate of the third N-type transistor MN3 is connected to the output signal UVLO.
7. The circuit according to claim 6, characterized in that, Undervoltage control circuit, including: The fourth P-tube, MP4, and the ninth P-tube, MP9; The source of the fourth P-transistor MP4 is connected to the power supply VDD, the drain of the fourth P-transistor MP4 is connected to the source of the ninth P-transistor MP9, and the gate of the fourth P-transistor MP4 is connected to the first gate output terminal of the bias circuit. The gate of the ninth P-transistor MP9 is connected to the second gate output terminal of the bias circuit.
8. The circuit according to claim 7, characterized in that, The undervoltage control circuit further includes: The fourth N-channel transistor MN4 and the first resistor R1; The drain of the fourth N-channel transistor MN4 is connected to the drain of the ninth P-channel transistor MP9. The drain of the fourth N-transistor MN4 is connected to its gate, and is also connected to the gate of the fifth N-transistor MN5. The source of the fourth N-transistor MN4 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.
9. The circuit according to claim 8, characterized in that, The undervoltage control circuit further includes: Fifth P-tube MP5, tenth P-tube MP10, and fifth N-tube MN5; The source of the fifth P transistor MP5 is connected to the power supply VDD, the drain of the fifth P transistor MP5 is connected to the source of the tenth P transistor MP10, and the gate of the fifth P transistor MP5 is connected to the first gate output terminal of the bias circuit. The gate of the tenth P transistor MP10 is connected to the second gate output terminal of the bias circuit, and the drain of the tenth P transistor MP10 is connected to the drain of the fifth N transistor MN5. The gate of the fifth N-transistor MN5 is connected to the gate and drain of the fourth N-transistor MN4, and the source of the fifth N-transistor MN5 is connected between the positive terminal of Zener diode D1 and the first terminal of the second resistor R2 in the power supply voltage detection circuit.
10. The circuit according to claim 9, characterized in that, The circuit also includes: An inverter buffer, the input of which is connected between the drain of the tenth P transistor MP10 and the drain of the fifth N transistor MN5; The output terminal of the inverter buffer outputs the signal UVLO.