A controller and control method for suppressing magnetic bias of an asymmetrical half-bridge converter

Abstract

The application relates to a controller and a control method for inhibiting magnetic bias of an asymmetric half-bridge converter. The application comprises a CS sampling / holding module for receiving a primary-side current sampling signal and outputting a holding value; a CS linear compensator for generating a first compensation quantity; a VCr asymmetric detection module for calculating the difference between two sampling values; a Ton nonlinear compensator for generating a second compensation quantity; a minimum arbitrator for selecting a smaller value from the first compensation quantity and the second compensation quantity and outputting a control correction quantity; a subtractor for generating a dynamic reference voltage signal for turning off a high-side switch according to the control correction quantity; and a PWM logic control module for comparing the primary-side current sampling signal and the dynamic reference voltage signal during the conduction of the high-side switch, and outputting a turn-off instruction for driving the high-side switch to turn off by a high-side drive module when the primary-side current sampling signal reaches the dynamic reference voltage signal. The application can eliminate the magnetic bias problem under the wide input range working condition.

Description

Technical Field

[0001] This invention relates to the field of power electronics control technology, and in particular to a controller for suppressing the bias magnetism of an asymmetrical half-bridge (AHB) converter. It is suitable for high-power-density AC / DC adapters and chargers with a wide input voltage range and a wide output voltage range, especially for power conversion scenarios that comply with USB Power Delivery 3.1 Extended Power Range (EPR). Background Technology

[0002] With the widespread adoption of the USB PD3.1 EPR standard, the charging power requirements of portable electronic devices have exceeded 100W, reaching a maximum of 240W, and the output voltage range has expanded to 5V–48V. Against this backdrop, the asymmetric half-bridge flyback converter, with its advantages of high power density and low switching losses, has become the mainstream topology for 100-watt AC / DC adapters.

[0003] The primary circuit of the AHB converter consists of a half-bridge structure formed by high-side and low-side switching transistors, with a resonant inductor Lr and a resonant capacitor Cr connected in series to form a resonant circuit. The resonant capacitor Cr plays a dual role in the circuit: firstly, it acts as a resonant element to participate in the implementation of zero-voltage switching (ZVS), enabling the switching transistors to turn on under zero-voltage conditions, significantly reducing switching losses; secondly, it acts as a DC blocking capacitor, blocking the DC bias current on the primary side of the transformer and preventing transformer core saturation.

[0004] In existing technologies, AHB converters commonly employ methods such as... Figure 1 The control architecture shown: secondary-side optocoupler feedback signal V FB With the primary current sampling signal V CS Both are fed into the comparator, when V CS Rise to V FB When the set threshold is reached, the comparator outputs a turn-off signal to the high-side switch, cutting off the excitation process for the current cycle. V FB With V CS The comparison result directly determines the single excitation energy transferred to the transformer during each conduction period of the high-side switch. However, there is an inherent structural contradiction between the two comparison signals in the above control architecture: V FB It is the secondary output voltage feedback signal after optocoupler transmission and error amplifier processing. Its bandwidth is limited by the crossover frequency of the outer voltage loop (usually less than 1 / 10 of the switching frequency), making it a slow-response signal that cannot track energy changes within each switching cycle; V CS It provides cycle-by-cycle peak information of the primary inductor current, offering a fast response, but essentially only reflects the energy stored in the inductor. The amplitude of this change is completely imperceptible to the voltage state of the resonant capacitor Cr. Slow V FB The signal response was too slow, and the fast V CS The signal also lacks capacitance information, and the combination of the two cannot accurately characterize the complete energy state of the resonant circuit.

[0005] The steady-state voltage balance of Cr requires strict conservation of charge and discharge during each complete switching cycle, meaning that the amount of charge flowing into Cr during the high-side conduction period must be equal to the amount of charge flowing out of Cr during the low-side conduction period. .

[0006] Under wide input voltage range operating conditions, when the input bus voltage V IN When a sudden change occurs, the rising slope of the primary inductor current changes drastically: .

[0007] Due to V CS Unable to detect the historical accumulation state of the resonant capacitor voltage VCr, the aforementioned charge-discharge conservation condition is broken. A net difference arises between the amount of charge flowing into and out of Cr in each cycle, causing VCr to drift unidirectionally cycle by cycle, i.e., DC bias occurs. The magnetic flux of the transformer core cannot be completely reset in each switching cycle, and eventually enters the saturation region as the bias accumulates. In the most severe case, this will lead to transformer burnout or overcurrent damage to the switching transistor.

[0008] Even with timely intervention from the outer voltage loop, the magnetization problem cannot be fundamentally eliminated. For example... Figure 2 As shown, when the input bus voltage V IN When a voltage drop occurs, VCr begins to drift unidirectionally, accumulating bias magnetism. The outer voltage loop senses the output voltage ripple and intervenes to regulate it, transforming the original unidirectional drift into subharmonic oscillations with alternating oscillations between adjacent cycles. This results in the output current and output voltage exhibiting large and small wave ripples with a beat time of twice the switching cycle. Long-term operation of the system in this large and small wave state will lead to output ripple exceeding specifications, decreased efficiency, and damage to the long-term reliability of the transformer and switching devices. The root cause of these problems lies in the fact that the two comparison signals used in the existing control architecture to determine the turn-off time of the high-side switch do not contain voltage state information of the resonant capacitor Cr. This prevents the controller from actively sensing and correcting the cycle-by-cycle asymmetric accumulation of VCr, resulting in an inherent bias magnetism suppression blind zone under wide input voltage range conditions. Summary of the Invention

[0009] To address the technical problem in existing AHB converter control architectures where neither the current sampling signal VCS nor the secondary-side feedback signal VFB contains information about the voltage state of the resonant capacitor Cr, resulting in a magnetic bias suppression blind zone under wide input voltage range conditions, this invention proposes a controller and control method to suppress magnetic bias in an asymmetric half-bridge converter. By introducing a VCr asymmetric detection mechanism and a dual-path compensation minimum value arbitration architecture, this invention actively senses and suppresses the cycle-by-cycle asymmetric accumulation of the resonant capacitor voltage without adding additional high-voltage sampling pins, fundamentally eliminating the magnetic bias problem under wide input range conditions.

[0010] To address the aforementioned technical problems, this invention provides a controller for suppressing the bias magnetization of an asymmetric half-bridge converter. This controller is integrated within a control chip, which drives the high-side and low-side switching transistors of the asymmetric half-bridge converter respectively through a high-side drive module and a low-side drive module. The controller includes: The CS sample / hold module is used to receive the primary current sampling signal V. CS (t), and trigger peak sampling at the turn-off edge of each high-side switch, capture the sampled voltage at the peak of the inductor current in the current cycle, and output the held value V. CS,pk ; A CS linear compensator, connected to the CS sample / hold module, is used to adjust the value V based on the hold value. CS,pk Generate the first compensation amount V CS,comp ; The VCr asymmetric detection module is used to receive the negative voltage signal generated by the auxiliary winding of the transformer during the conduction of the high-side switching transistor, and performs sample-and-hold for two consecutive high-side conduction cycles, calculating the difference between the two sampled values. The difference between the two sampled values The asymmetry is proportional to the voltage of the resonant capacitor in adjacent periods; The Ton nonlinear compensator, connected to the VCr asymmetric detection module, is used to calculate the difference between the two sampled values. Generate the second compensation quantity V TON,comp ; The minimum arbitrator, connected to the CS linear compensator and the Ton nonlinear compensator respectively, is used to obtain the first compensation amount V. CS,comp and the second compensation amount V TON,comp Select the smaller value and output the control correction amount V. Ctrl ; The subtractor, connected to the minimum arbitrator, is used to provide a voltage feedback signal V. FB Based on the base value, and according to the control correction amount V Ctrl Generates a dynamic reference voltage signal V for turning off the high-side switch. HS_off ; The PWM logic control module is connected to the subtractor, the CS sample / hold module, the high-side drive module, and the low-side drive module, respectively. The PWM logic control module is used to compare the primary-side current sampling signal V during the conduction period of the high-side switch. CS (t) and the dynamic reference voltage signal V HS_off and in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off When the high-side drive module is activated, a shutdown command is output to turn off the high-side switch transistor.

[0011] In one embodiment of the present invention, the asymmetric half-bridge converter further includes a transformer, a resonant inductor, a resonant capacitor, a rectifier diode, an output filter capacitor, and a load resistor; The transformer includes a primary winding, a secondary winding, and an auxiliary winding. The primary winding includes a primary inductor, the secondary winding includes a secondary inductor, and the auxiliary winding includes an auxiliary inductor. The primary inductor, the secondary inductor, and the auxiliary inductor are coupled through a magnetic core. The source of the high-side switch, the resonant inductor, the primary inductor, the resonant capacitor, and the source of the low-side switch are connected in sequence. One end of the secondary inductor is connected to the positive terminal of the rectifier diode. The negative terminal of the rectifier diode, one end of the output filter capacitor, and one end of the load resistor are connected to the output terminal of the secondary winding. The output terminal of the secondary winding can output the secondary output voltage V. OUT The other end of the secondary inductor, the other end of the output filter capacitor C209, and the other end of the load resistor are grounded; The source of the low-side switch is grounded through the primary-side current sampling resistor, which converts the primary-side current signal into a primary-side current sampling signal V. CS After (t), it is sent to the CS sample / hold module; The induced voltage of the auxiliary winding of the transformer is sent to the ZCD pin of the VCr asymmetric detection module after passing through the first current-limiting voltage divider resistor R207 and the second current-limiting voltage divider resistor.

[0012] In one embodiment of the present invention, a feedback signal generation module is further included, the feedback signal generation module being used to generate a feedback signal based on the secondary-side output voltage V. OUT Generate the voltage feedback signal V FB The feedback signal generation module includes an optocoupler, a controllable precision voltage regulator, an external voltage divider resistor network, and a filter capacitor bank. The external voltage divider resistor network includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, a fourth voltage divider resistor, and a fifth voltage divider resistor; The filter capacitor bank includes a first filter capacitor and a second filter capacitor; The two ends of the series connection between the first voltage divider resistor and the second voltage divider resistor are respectively connected to the output terminal of the secondary winding and the ground terminal. One end of the third voltage divider resistor is connected to the output terminal of the secondary winding, and the other end is connected to one end of the optocoupler's light-emitting side and one end of the fourth voltage divider resistor. The other end of the fourth voltage divider resistor is connected to the other end of the optocoupler's light-emitting side and the first end of the controllable precision voltage regulator, and the second end of the controllable precision voltage regulator is grounded; The third terminal of the controllable precision voltage regulator is connected between the first voltage divider resistor and the second voltage divider resistor; The two ends of the first filter capacitor and the fifth voltage divider resistor connected in series are respectively connected to the first end of the controllable precision voltage regulator and between the first voltage divider resistor and the second voltage divider resistor. The two ends of the second filter capacitor are respectively connected to the first end of the controllable precision voltage regulator and between the first voltage divider resistor and the second voltage divider resistor. The output of the optocoupler is connected to the input of the subtractor, and the output voltage feedback signal V is obtained through the optocoupler. FB .

[0013] In one embodiment of the present invention, the CS sampling / hold module includes a leading-edge effect shielding circuit and a peak sampling and holding circuit; The leading-edge effect shielding circuit is used for shielding time t after each turn-on of the high-side switch. blank Shielding the primary current sampling signal V CS The sampling input of (t) is used to filter out the current spikes caused by the charging and discharging of parasitic capacitance during the turn-on of the high-side switch. The peak sampling and holding circuit is used during the shielding time t blank After completion, the primary current sampling signal V is monitored. CS (t), and sample and hold the peak value triggered on the turn-off edge of the high-side switch, outputting the hold value V corresponding to the peak value of the inductor current in the current cycle. CS,pk And maintain it until the next sampling trigger edge.

[0014] In one embodiment of the present invention, the first compensation amount is: V CS,comp =K CS (V IN V OUT )×V CS,pk ; Wherein, the slope coefficient K CS Based on the input bus voltage V IN With output voltage V OUT Adaptive adjustment; V CS,pk To preserve the value.

[0015] In one embodiment of the present invention, the VCr asymmetric detection module includes a negative feedback transimpedance amplifier circuit, a current mirror, a sampling resistor, a Toggle trigger, a first sample-and-hold circuit, and a second sample-and-hold circuit. The negative feedback transimpedance amplifier circuit includes an on-chip operational amplifier and an NMOS transistor; The current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The non-inverting input of the on-chip operational amplifier is connected to a 0V reference, and the inverting input of the on-chip operational amplifier is connected to the source of the NMOS transistor. The output of the on-chip operational amplifier is connected to the gate of the NMOS transistor; The source of the NMOS transistor is connected between the first current-limiting voltage divider resistor and the second current-limiting voltage divider resistor; The gates of the second PMOS transistor and the fourth PMOS transistor are connected, and the gates of the first PMOS transistor and the third PMOS transistor are connected. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The source of the first PMOS transistor is connected to its own gate, and the source of the second PMOS transistor is connected to its own gate. The drains of the second and fourth PMOS transistors, as well as the control input of the Toggle flip-flop, are connected to the internal power supply; the clock input of the Toggle flip-flop is connected to the high-side switch drive signal HG. One end of the sampling resistor is connected to the source of the third PMOS transistor, and the other end of the sampling resistor is grounded. The source of the third PMOS transistor is connected to the data input terminal of the first sample-and-hold circuit and the data input terminal of the second sample-and-hold circuit, respectively. The positive output of the Toggle flip-flop is connected to the clock input of the first sample-and-hold circuit. The inverting output of the Toggle flip-flop is connected to the clock input of the second sample-and-hold circuit.

[0016] In one embodiment of the present invention, the minimum arbitrator adopts a digital domain arbitration structure, the digital domain arbitration structure comprising: The first analog-to-digital converter and the second analog-to-digital converter are used to respectively convert the first compensation amount V CS,comp and the second compensation amount V TON,comp Quantized into a first digital code and a second digital code; A digital comparator is used to compare the magnitudes of the first digital code and the second digital code, and outputs a selection signal; A digital multiplexer is used to select the digital code corresponding to the smaller value according to the selection signal; The digital-to-analog converter converts the digital code selected by the digital multiplexer into an analog voltage signal, which serves as the control correction quantity V. Ctrl .

[0017] In one embodiment of the present invention, the minimum arbitrator adopts an analog domain arbitration structure, which includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first diode, a second diode, and a pull-up resistor. The non-inverting input of the first operational amplifier is connected to the second compensation quantity V. TON,comp ; The output of the first operational amplifier is connected to a common output node via a first diode; The non-inverting input of the second operational amplifier is connected to the first compensation value V. CS,comp ; The output of the second operational amplifier is connected to a common output node via a second diode. The inverting inputs of the first and second operational amplifiers are each connected to a common output node. The common output node is connected to the internal power supply via a pull-up resistor; The non-inverting input of the third operational amplifier is connected to a common output node, and the inverting input is connected to its own output. The third operational amplifier can output a control correction value V. Ctrl .

[0018] In one embodiment of the present invention, the minimum arbitrator adopts a hybrid domain arbitration structure, which includes an analog comparator, a SEL inverter, a first CMOS transmission gate, and a second CMOS transmission gate. The non-inverting input of the analog comparator is connected to the first compensation quantity V. CS,comp The inverting input of the analog comparator is connected to the second compensation quantity V. TON,comp The analog comparator is used to compare the first compensation amount V. CS,comp With the second compensation amount V TON,comp The size of the signal is determined, and a digital control signal SEL is output. First compensation amount V CS,comp It is also connected to the signal input terminal of the first CMOS transmission gate, and the second compensation amount V TON,comp It is also connected to the signal input terminal of the second CMOS transmission gate; The output of the analog comparator is connected to the input of the inverter, the first control terminal of the first CMOS transmission gate, and the first control terminal of the second CMOS transmission gate, respectively. The output of the inverter is connected to the second control terminal of the first CMOS transmission gate and the second control terminal of the second CMOS transmission gate, respectively, to provide complementary gating signals to the first CMOS transmission gate and the second CMOS transmission gate. The output terminals of the first CMOS transmission gate and the second CMOS transmission gate are connected to the same output node and used to output the control correction value VCtrl; The first CMOS transmission gate and the second CMOS transmission gate are complementaryly turned on under the control of the digital control signal SEL; When the first compensation amount V CS,comp Less than the second compensation amount V TON,comp When the digital control signal SEL is low, the first CMOS transmission gate is turned on and the first compensation amount V is applied. CS,comp VCtrl serves as a control correction value; When the first compensation amount V CS,comp Greater than the second compensation amount V TON,comp At that time, the digital control signal SEL is high, the second CMOS transmission gate is turned on, and V... TON,comp VCtrl is used as a control correction variable.

[0019] The present invention also provides a control method for suppressing the bias magnetism of an asymmetric half-bridge converter, comprising: Receive primary current sampling signal V CS (t), and trigger peak sampling at the turn-off edge of each high-side switch, capture the sampled voltage at the peak of the inductor current in the current cycle, and output the held value V. CS,pk ; According to the retention value V CS,pk Generate the first compensation amount V CS,comp ; The system receives the negative voltage signal generated by the transformer auxiliary winding during the conduction of the high-side switch, performs sample-and-hold for two consecutive high-side conduction cycles, and calculates the difference between the two sample values. The difference between the two sampled values The asymmetry is proportional to the voltage of the resonant capacitor in adjacent periods; Based on the difference between the two sampled values Generate the second compensation quantity V TON,comp ; For the first compensation amount V CS,comp and the second compensation amount V TON,comp Perform minimum value arbitration, select the smaller of the two values, and output the control correction amount V. Ctrl ; Based on the voltage feedback signal VFB as the base value, and according to the control correction amount V Ctrl Generates a dynamic reference voltage signal V for turning off the high-side switch. HS_off ; The primary current sampling signal V is compared during the conduction of the high-side switch. CS (t) and the dynamic reference voltage signal V HS_offand in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off When the high-side drive module is activated, a shutdown command is output to turn off the high-side switch transistor.

[0020] The technical solution of the present invention has the following advantages compared with the prior art: Effect 1: The VCr asymmetry detection module indirectly senses the accumulation of asymmetry in the resonant capacitor voltage by utilizing the difference between adjacent cycles of the auxiliary winding clamping current, and the difference calculation naturally eliminates the input bus voltage V. IN The common-mode interference was eliminated, and the accurate sensing of the Cr voltage state was achieved without adding any additional high-voltage sampling pins, filling the blind spot of existing technology in sensing bias magnetism under wide input voltage range conditions.

[0021] Effect 2: The CS linear compensator and the Ton nonlinear compensator independently sense different types of bias magnetism in the amplitude and time domains, respectively—CS path sensing I pk Absolute value anomalies can cover VCr slow unidirectional drift-type bias. Ton path sensing of adjacent periods. The difference can cover alternating oscillating bias. The two paths complement each other's blind zones, and minimum value arbitration ensures that only one path is effective at any given time, fundamentally eliminating the risk of subharmonic oscillation caused by the superposition of gains from both paths.

[0022] Effect 3: After the bias magnetization occurs, the VCr asymmetry detection module quickly senses it. With the accumulation of power and the coordinated intervention of dual-path compensation, the system converges to a new steady-state operating point within several switching cycles, eliminating large and small ripples and restoring output voltage stability; after the bias converges... Approaching zero, the bias suppression inner loop is completely transparent to the voltage outer loop, and does not introduce additional steady-state error. Attached Figure Description

[0023] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the existing AHB converter architecture.

[0025] Figure 2 This is a timing diagram of the bias magnetization that occurs when the input voltage fluctuates in an existing AHB converter.

[0026] Figure 3 This is the overall block diagram of the AHB converter system of the present invention.

[0027] Figure 4 This is a timing diagram of the AHB converter bias suppression process of the present invention.

[0028] Figure 5 This is a schematic diagram of the structure of the suppression AHB converter CS sample / hold module and CS linear compensator of the present invention.

[0029] Figure 6 This is a schematic diagram of the structure of the AHB converter VCr asymmetric detection module and the Ton nonlinear compensator of the present invention.

[0030] Figure 7 This is a schematic diagram of the minimum arbiter for suppressing AHB converters of the present invention implemented in the pure digital domain.

[0031] Figure 8 This is a schematic diagram of the AHB converter suppression minimum arbiter of the present invention implemented through a pure analog domain.

[0032] Figure 9 This is a schematic diagram of the AHB converter suppression minimum arbiter implemented through a hybrid domain according to the present invention.

[0033] Explanation of reference numerals in the instruction manual: 100. Control chip; 101. CS sample / hold module; 102. CS linear compensator; 103. VCr asymmetric detection module; 104. Ton nonlinear compensator; 105. Minimum arbitrator; 106. Subtractor; 107. PWM logic control module; 108. High-side drive module; 109. Low-side drive module; N201, High-side switching transistor; N202, Low-side switching transistor; T203, Transformer; D204, Rectifier diode; C205, Resonant capacitor; R206, Primary-side current sampling resistor; R207, First current-limiting voltage divider resistor; R208, Second current-limiting voltage divider resistor; C209, Output filter capacitor; Lr, resonant inductance; Lpr, primary inductance; Lsec, secondary inductance; Laux, auxiliary inductance; Rload, load resistance; R210, First voltage divider resistor; R211, Second voltage divider resistor; R212, Third voltage divider resistor; R213, Fourth voltage divider resistor; R214, Fifth voltage divider resistor; C215, First filter capacitor; C216, Second filter capacitor; O217, Optocoupler; T217, Controllable precision voltage regulator; O301, On-chip operational amplifier; N302, NMOS transistor; P303, First PMOS transistor; P304, Second PMOS transistor; P305, Third PMOS transistor; P306, Fourth PMOS transistor; F307, Toggle flip-flop; F308, First sample-and-hold circuit; F309, Second sample-and-hold circuit; R310, Sampling resistor; O401, First operational amplifier; O402, Second operational amplifier; O403, Third operational amplifier; D404, First diode; D405, Second diode; R406, Pull-up resistor; C501, Analog Comparator; I502, Inverter; T503, First CMOS Transmission Gate; T504, Second CMOS Transmission Gate. Detailed Implementation

[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0035] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0036] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0037] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0038] Example 1

[0039] Reference Figure 3 As shown, this embodiment provides a controller for suppressing the bias magnetization of an asymmetric half-bridge converter. This controller is integrated within a control chip 100. The control chip 100 drives the high-side and low-side switching transistors of the asymmetric half-bridge converter respectively through a high-side driving module 108 and a low-side driving module 109. The controller includes: CS sample / hold module 101 is used to receive the primary current sampling signal V. CS(t), and trigger peak sampling at the turn-off edge of each high-side switch, capture the sampled voltage at the peak of the inductor current in the current cycle, and output the held value V. CS,pk The CS sampling / holding module 101 has an internal shielding time t. blank After the high-side switch N201 is turned on, t blank The sampling input is shielded within a certain time period to filter out the current spikes caused by the charging and discharging of parasitic capacitance during the turn-on of the high-side switch N201; CS linear compensator 102, connected to the CS sample / hold module 101, is used to calculate the hold value V. CS,pk Generate the first compensation amount V CS,comp ; The VCr asymmetric detection module 103 is used to receive the negative voltage signal generated by the auxiliary winding of the transformer during the conduction of the high-side switching transistor, and to perform sample-and-hold for two consecutive high-side conduction cycles, calculating the difference between the two sampled values. The difference between the two sampled values The asymmetry is proportional to the voltage of the resonant capacitor in adjacent periods; The Ton nonlinear compensator 104 is connected to the VCr asymmetric detection module 103 and is used to calculate the difference between the two sampled values. Generate the second compensation quantity V TON,comp Specifically, the Ton nonlinear compensator 104 receives the output from the VCr asymmetric detection module 103. The normalized second compensation quantity V is mapped to a piecewise linear function of three segments. TON,comp The first section is the high-gain fine-tuning correction region, the second section is the accelerated convergence transition region, and the third section is the saturation limiting protection region. The second compensation quantity V... TON,comp After normalization, it has the same properties as the first compensation quantity V. CS,comp The same dimensional space is used to support the minimum arbitration at the subsequent level.

[0040] The minimum arbitrator 105 is connected to the CS linear compensator 102 and the Ton nonlinear compensator 104 respectively, and is used to obtain the first compensation amount V CS,comp and the second compensation amount V TON,comp Select the smaller value and output the control correction amount V. Ctrl Specifically, the minimum arbitrator 105 selects the first compensation amount V in real time. CS,comp Second compensation amount V TON,comp Output the smaller of the two: V Ctrl =min(V CS,comp V TON,compMinimum value arbitration ensures that, under any operating condition, the two compensation loops do not simultaneously superimpose on the turn-off control of the high-side switch. The equivalent open-loop gain is reduced from the product of the two gains to the maximum value of the two, fundamentally eliminating the subharmonic oscillations caused by the superposition of the two gains.

[0041] Subtractor 106, connected to the minimum arbitrator 105, is used to provide a voltage feedback signal V. FB Based on the base value, and according to the control correction amount V Ctrl Generates a dynamic reference voltage signal V for turning off the high-side switch. HS_off Subtractor 106 outputs the correction value V obtained by full-scale conversion using the minimum arbitrator 105. Ctrl To reduce the load, the dynamic reference voltage V that the high-side switch N201 is turned off is synthesized. HS_off ; The PWM logic control module 107 is connected to the subtractor 106, the CS sample / hold module 101, the high-side drive module 108, and the low-side drive module 109, respectively. The PWM logic control module 107 is used to compare the primary-side current sampling signal V during the conduction period of the high-side switch. CS (t) and the dynamic reference voltage signal V HS_off and in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off At that time, a turn-off command is output to enable the high-side drive module 108 to drive the high-side switch transistor to turn off, and the low-side switch transistor N202 is driven to turn on and off by the low-side drive module 109 according to the corresponding signal.

[0042] Through the above structure, the VCr asymmetry detection module 103 indirectly senses the asymmetry accumulation of the resonant capacitor voltage by utilizing the difference between adjacent cycles of the auxiliary winding clamping current, and the difference calculation naturally eliminates the input bus voltage V IN The common-mode interference was eliminated, and the accurate sensing of the Cr voltage state was achieved without adding any additional high-voltage sampling pins, filling the blind spot of existing technology in sensing bias magnetism under wide input voltage range conditions.

[0043] The CS linear compensator 102 and the Ton nonlinear compensator 104 independently sense different types of bias magnetism in the amplitude domain and time domain, respectively—the CS path senses the peak current I. pk Absolute value anomalies can cover VCr slow unidirectional drift-type bias. Ton path sensing of adjacent periods. The difference can cover alternating oscillating bias. The two paths complement each other's blind zones, and minimum value arbitration ensures that only one path is effective at any given time, fundamentally eliminating the risk of subharmonic oscillation caused by the superposition of gains from both paths.

[0044] like Figure 4As shown, the VCr asymmetry detection module 103 quickly senses the occurrence of bias magnetization. With the accumulation of power and the coordinated intervention of dual-path compensation, the system converges to a new steady-state operating point within several switching cycles, eliminating large and small ripples and restoring output voltage stability; after the bias converges... Approaching zero, the bias suppression inner loop is completely transparent to the voltage outer loop, and does not introduce additional steady-state error.

[0045] Specifically, refer to Figure 3 As shown, the asymmetric half-bridge converter also includes a transformer T203, a resonant inductor Lr, a resonant capacitor C205 (i.e., Cr), a rectifier diode D204, an output filter capacitor C209, and a load resistor Rload. The transformer T203 includes a primary winding, a secondary winding, and an auxiliary winding. The primary winding includes a primary inductance L. pr The secondary winding includes the secondary inductor L sec The auxiliary winding includes the auxiliary inductor L aux Primary inductance L pr Secondary inductor L sec and auxiliary inductor L aux Coupled via magnetic core; The source, resonant inductance Lr, and primary inductance L of the high-side switching transistor pr The resonant capacitor C205 and the source of the low-side switching transistor are connected in sequence. Secondary inductor L sec One end of the capacitor is connected to the positive terminal of the rectifier diode D204. The negative terminal of the rectifier diode D204, one end of the output filter capacitor C209, and one end of the load resistor Rload are connected to the output terminal of the secondary winding. The output terminal of the secondary winding can output the secondary output voltage V. OUT Secondary inductor L sec The other end of the output filter capacitor C209 and the other end of the load resistor Rload are grounded; The source of the low-side switching transistor is grounded through the primary-side current sampling resistor R206. The primary-side current sampling resistor R206 converts the primary-side current signal into a primary-side current sampling signal V. CS (t) is then sent to the CS sample / hold module 101; The induced voltage of the auxiliary winding of transformer T203 is sent to the ZCD pin of VCr asymmetry detection module 103 after passing through the first current-limiting voltage divider resistor R207 and the second current-limiting voltage divider resistor R208. It should be noted that the VCr asymmetric detection module 103 uses the negative voltage generated by the auxiliary winding during the conduction of the high-side switching transistor N201 to form a clamping current I at the ZCD pin via the external first current-limiting voltage divider resistor R207. clampThe on-chip negative feedback clamping circuit forces the ZCD pin potential to be maintained at the 0V reference. The clamping current is replicated as the mirror current I by the on-chip current mirror with a scaling factor M. mirror The signal is then converted into a voltage signal by the sampling resistor R310. The VCr asymmetric detection module 103 performs sampling and holding for two consecutive high-side conduction cycles N, and calculates the difference between the two sampled values. : ; The difference operation makes the input bus voltage V IN As the common modulus is completely eliminated The asymmetry is directly proportional to the resonant capacitor voltage of adjacent periods. It has an inherent ability to suppress bus voltage fluctuations over a wide input voltage range.

[0046] Specifically, it also includes a feedback signal generation module, which is used to generate a feedback signal based on the secondary output voltage V. OUT Generate the voltage feedback signal V FB The feedback signal generation module includes an optocoupler O217, a controllable precision voltage regulator T217, an external voltage divider resistor network, and a filter capacitor bank. The external voltage divider resistor network includes a first voltage divider resistor R210, a second voltage divider resistor R211, a third voltage divider resistor R212, a fourth voltage divider resistor R213, and a fifth voltage divider resistor R214. The filter capacitor bank includes a first filter capacitor C215 and a second filter capacitor C216. Among them, the two ends of the series connection of the first voltage divider resistor R210 and the second voltage divider resistor R211 are respectively connected to the output terminal of the secondary winding and the ground terminal; One end of the third voltage divider resistor R212 is connected to the output terminal of the secondary winding, and the other end is connected to one end of the light-emitting side of the optocoupler O217 and one end of the fourth voltage divider resistor R213. The other end of the fourth voltage divider resistor R213 is connected to the other end of the light-emitting side of the optocoupler O217 and the first end of the controllable precision voltage regulator T217, and the second end of the controllable precision voltage regulator T217 is grounded. The third terminal of the controllable precision voltage regulator T217 is connected between the first voltage divider resistor R210 and the second voltage divider resistor R211; The two ends of the first filter capacitor C215 and the fifth voltage divider resistor R214 connected in series are respectively connected to the first end of the controllable precision voltage regulator T217 and between the first voltage divider resistor R210 and the second voltage divider resistor R211. The two ends of the second filter capacitor C216 are respectively connected to the first end of the controllable precision voltage regulator T217 and between the first voltage divider resistor R210 and the second voltage divider resistor R211. The output of optocoupler O217 is connected to the input of subtractor 106, and the output voltage feedback signal V is obtained through optocoupler O217. FB .

[0047] With the above setup, the controllable precision voltage regulator T217 (such as the TL431 device), the external voltage divider resistor network R210~R214, and the filter capacitor group C215~C216 form a voltage feedback signal V. FB The signal is fed into the subtractor 106 module of the control chip 100, which then generates a dynamic reference voltage signal V. HS_off It is then sent to the PWM logic control module 107.

[0048] like Figure 4 As shown in the normal steady-state phase, at the input voltage V IN Under stable, constant load conditions, the system operates in continuous resonance mode. During each switching cycle, the high-side switch N201 is turned on under ZVS conditions, and the magnetizing current i... Lr Starting from the negative peak -Ineg, it rises through resonance to the positive peak +Ipk. When the CS sample / hold module 101 detects V... CS (t) rises to the dynamic reference voltage signal V HS_off At this time, the PWM logic control module 107 outputs a turn-off signal for the high-side switch, and N201 turns off. Subsequently, after a dead time, the low-side switch N202 turns on under ZVS conditions, and the excitation current decreases from its positive peak, passing through zero to its negative peak before turning off, completing one full switching cycle. During this phase, the auxiliary winding clamping current is equal in two adjacent high-side switch conduction cycles. Dynamic reference voltage signal V HS_off =V FB .

[0049] Continue to refer to Figure 4 As shown, when the input voltage suddenly drops, the slope of the primary inductor current rises with V IN As the voltage decreases, the amount of charge flowing into the resonant capacitor Cr (C205) during the high-side switch conduction period decreases, while the amount of charge flowing out of Cr during the low-side switch conduction period does not decrease synchronously, resulting in a net charge difference in each cycle. Subsequently, the outer voltage loop responds slowly due to bandwidth limitations, and the system V in the next cycle... FB The voltage rises rapidly, inducing significant large and small waves during the bias generation phase. Subsequently, during the third cycle of these large and small waves, the VCr asymmetric detection module 103 of this invention activates to rapidly pull VCr. FB The signal. After ten cycles of slow adjustment, V... FB The signal eventually reaches a new stable operating state, V HG / V LG Timing rules, excitation current i LrThe waveform is symmetrical, VCr returns to the equilibrium point, V FB and V OUT Once equilibrium is restored, the large and small wavelets completely disappear, and at this point V HS_off V FB With the inner bias suppression loop withdrawing its intervention, the outer voltage loop once again fully dominates the output voltage regulation.

[0050] like Figure 5 As shown, the CS sampling / hold module 101 includes a leading-edge effect shielding circuit and a peak sampling and holding circuit; The leading-edge effect shielding circuit is used for shielding time t after each turn-on of the high-side switch. blank Shielding the primary current sampling signal V CS The sampling input of (t) is used to filter out the current spikes caused by the charging and discharging of parasitic capacitance during the turn-on of the high-side switch. The peak sampling and holding circuit is used during the shielding time t blank After completion, the primary current sampling signal V is monitored. CS (t), and sample and hold the peak value triggered on the turn-off edge of the high-side switch, outputting the hold value V corresponding to the peak value of the inductor current in the current cycle. CS,pk And maintain it until the next sampling trigger edge.

[0051] Specifically, the CS sample / hold module 101 receives the primary-side current sampling signal V from the primary-side sampling resistor R206. CS (t). The CS sample / hold module 101 has an internal leading-edge effect shielding circuit, which provides shielding for the high-side switch N201 for the shielding time t after each turn-on. blank , shield V CS The sampling input (t) is used to filter out current spikes caused by the charging and discharging of parasitic capacitance during the turn-on of the high-side switch N201. After the shielding time ends, the CS sample / hold module 101 continuously monitors V. CS (t) triggers peak sampling and holding on the turn-off edge of the high-side switch N201, outputting the holding voltage V corresponding to the peak inductor current of the current cycle. CS,pk And maintain it until the next sampling trigger edge.

[0052] like Figure 5 As shown, the CS linear compensator 102 receives V CS,pk After being multiplied by the slope coefficient K CS Perform linear amplification and output the first compensation value V. CS,comp Slope coefficient K CS It is an adaptive adjustment unit based on the input bus voltage V IN Using the sampled value and the output voltage feedback value VOUT as indices, K is refreshed at the beginning of each switching cycle via an on-chip lookup table. CSTo compensate for the charge integral Q during the high-side conduction period at different operating points. HS to I pk Changes in sensitivity.

[0053] Specifically, the CS linear compensator 102 receives the hold value V output by the CS sample / hold module 101. CS,pk The first compensation quantity V is generated through linear mapping. CS,comp for: V CS,comp =K CS (V IN V OUT )×V CS,pk ; Wherein, the slope coefficient K CS Based on the input bus voltage V IN With output voltage V OUT Adaptive adjustment; V CS,pk To maintain the value. First compensation amount V CS,comp Reflecting the absolute value of the peak inductor current in the current cycle, when VCr undergoes slow unidirectional drift and the difference between adjacent cycles approaches zero, the CS linear compensator 102 can respond via I... pk Abnormal changes in absolute value indirectly indicate the overall offset of VCr, serving as a safety net for the Ton compensation path.

[0054] like Figure 6 As shown, the VCr asymmetric detection module 103 includes a negative feedback transimpedance amplifier circuit, a current mirror, a sampling resistor R310, a Toggle trigger F307, a first sample-and-hold circuit F308, and a second sample-and-hold circuit F309. The negative feedback transimpedance amplifier circuit includes an on-chip operational amplifier O301 and an NMOS transistor N302; The current mirror includes a first PMOS transistor P303, a second PMOS transistor P304, a third PMOS transistor P305, and a fourth PMOS transistor P306; The non-inverting input of the on-chip operational amplifier O301 is connected to a 0V reference, and the inverting input of the on-chip operational amplifier O301 is connected to the source of the NMOS transistor N302. The output of the on-chip operational amplifier O301 is connected to the gate of the NMOS transistor N302; The source of NMOS transistor N302 is connected between the first current-limiting voltage divider resistor R207 and the second current-limiting voltage divider resistor R208. The gates of the second PMOS transistor P304 and the fourth PMOS transistor P306 are connected, and the gates of the first PMOS transistor P303 and the third PMOS transistor P305 are connected. The drain of the first PMOS transistor P303 is connected to the source of the second PMOS transistor P304, and the drain of the third PMOS transistor P305 is connected to the source of the fourth PMOS transistor P306. The source of the first PMOS transistor P303 is connected to its own gate, and the source of the second PMOS transistor P304 is connected to its own gate. The drains of the second PMOS transistor P304 and the fourth PMOS transistor P306, as well as the control input of the Toggle flip-flop F307, are connected to the internal power supply; the clock input of the Toggle flip-flop F307 is connected to the high-side switch drive signal HG. One end of the sampling resistor R310 is connected to the source of the third PMOS transistor P305, and the other end of the sampling resistor R310 is grounded. The source of the third PMOS transistor P305 is connected to the data input terminal of the first sample-and-hold circuit F308 and the data input terminal of the second sample-and-hold circuit F309, respectively. The positive output of the Toggle flip-flop F307 is connected to the clock input of the first sample-and-hold circuit F308; The inverting output of the Toggle flip-flop F307 is connected to the clock input of the second sample-and-hold circuit F309.

[0055] Specifically, the input to the VCr asymmetry detection module 103 comes from the induced voltage Vc of the auxiliary winding of transformer T203. AUX The auxiliary winding is connected to the ZCD pin of the control chip 100 via external first current-limiting voltage divider resistor R207 and second current-limiting voltage divider resistor R208. The auxiliary winding is wound with the opposite polarity to the primary side of the transformer. During the high-side switch conduction, the auxiliary winding induces a negative voltage V. AUX,HS : V AUX,HS =-N aux (V IN -V Cr ).

[0056] The on-chip operational amplifier O301 and NMOS transistor N302 form a negative feedback transimpedance amplifier circuit, forcing the ZCD pin potential to be maintained at 0V reference. The negative voltage of the auxiliary winding forms a clamping current at the ZCD pin through the second current-limiting voltage divider resistor R208. : .

[0057] The clamping current is replicated as a mirror current I via a scaling factor M through a current mirror consisting of the first PMOS transistor P303, the second PMOS transistor P304, the third PMOS transistor P305, and the fourth PMOS transistor P306. mirrorThe signal is then converted into a voltage signal by sampling resistor R310. The Toggle flip-flop F307 is triggered by the falling edge of the high-side switch drive signal HG, toggling once with each falling edge of the high-side switch drive signal HS. The Q and QN terminals of the Toggle flip-flop F307 generate alternating enable signals for odd and even periods, respectively, controlling the first sample-and-hold circuit F308 and the second sample-and-hold circuit F309 to sample alternately. The first sample-and-hold circuit F308 samples and holds the signal when the high-side switch drive signal HG is turned off during odd periods. mirror [N], The second sample-and-hold circuit F309 samples and holds I when the high-side switch drive signal HG is turned off during even-numbered cycles. mirror [N-1], I mirror [N] and I mirror [N-1] The mirror current of a given cycle and the previous cycle, respectively; the two held values ​​are output after difference calculation: .

[0058] Due to the input bus voltage V IN In the difference operation, it is completely eliminated as a common modulus. Only reflects the resonant capacitor voltage V of adjacent cycles Cr The change in voltage, relative to the input bus voltage V IN The absolute value is irrelevant. The Ton nonlinear compensator 104 receives... After three pieces of linear function f TON Mapping generates the second compensation quantity V TON,comp The function has the following form: .

[0059] The first segment is the high-gain fine-tuning correction region, with a slope... The larger value enables fine bias correction even with slight magnetic bias. The second section is the accelerated convergence transition region, where b2 is the intercept and slope. To prevent overshoot when compensating for large deviations, the third segment is a saturation limiting protection zone, clamping the output to the upper limit. Piece boundary parameters , and slope coefficient , It is stored in an on-chip programmable register and can be configured via OTP according to external power stage parameters.

[0060] Specifically, the minimum arbitrator 105 has three implementation methods: pure digital domain implementation, pure analog domain implementation, and hybrid domain implementation, all of which can realize the first compensation amount V. CS,comp Second compensation amount V TON,comp The real-time minimum value is selected.

[0061] Reference Figure 7As shown, the minimum arbitrator 105 adopts a digital domain arbitration structure, which includes: The first analog-to-digital converter and the second analog-to-digital converter are used to respectively convert the first compensation amount V CS,comp and the second compensation amount V TON,comp Quantized into a first digital code and a second digital code; A digital comparator is used to compare the magnitudes of the first digital code and the second digital code, and outputs a selection signal; A digital multiplexer is used to select the digital code corresponding to the smaller value according to the selection signal; The digital-to-analog converter converts the digital code selected by the digital multiplexer into an analog voltage signal, which serves as the control correction quantity V. Ctrl .

[0062] Specifically, the first compensation amount V CS,comp Second compensation amount V TON,comp The first digital code Ncs and the second digital code Nton are quantized into n-bit first digital code Ncs and second digital code Nton respectively by two analog-to-digital converters (ADCs). A digital comparator compares the size of the first digital code Ncs and the second digital code Nton, and outputs a 1-bit selection signal SEL to control a 2-to-1 digital multiplexer (MUX) to select the digital code corresponding to the smaller value. The output of the MUX is reconstructed into an analog voltage signal V by a digital-to-analog converter (DAC). Ctrl The data is fed into subtractor 106. This method offers high precision, programmable parameters, and easy integration with digital control cores, but it introduces additional latency due to ADC / DAC conversion.

[0063] Reference Figure 8 As shown, the minimum arbiter 105 adopts an analog domain arbitration structure, which includes a first operational amplifier O401, a second operational amplifier O402, a third operational amplifier O403, a first diode D404, a second diode D405, and a pull-up resistor R406. The non-inverting input of the first operational amplifier O401 is connected to the second compensation quantity V. TON,comp ; The output of the first operational amplifier O401 is connected to a common output node through the first diode D404; The non-inverting input of the second operational amplifier O402 is connected to the first compensation value V. CS,comp ; The output of the second operational amplifier O402 is connected to the common output node through the second diode D405; The inverting inputs of the first operational amplifier O401 and the second operational amplifier O402 are each connected to a common output node; The common output node is connected to the internal power supply via pull-up resistor R406; The non-inverting input of the third operational amplifier O403 is connected to a common output node, and the inverting input of the third operational amplifier O403 is connected to its own output. The third operational amplifier O403 can output a control correction value V. Ctrl .

[0064] Specifically, the first operational amplifier O401 and the second operational amplifier O402 form a minimum voltage follower network: the inverting input terminals of both operational amplifiers are connected to a common output node, forming negative feedback; the operational amplifier with the lower input voltage is in normal amplification mode, while the operational amplifier with the higher input voltage is saturated and cut off due to the inverting diode at its negative terminal, and the common node naturally outputs the lower of the two input voltages. The third operational amplifier O403 forms a voltage follower, and after eliminating the load effect, outputs the final control correction quantity V. Ctrl This method offers the fastest response time and eliminates quantization error, but the operational amplifier offset voltage introduces system errors, requiring temperature drift compensation.

[0065] Reference Figure 9 As shown, the minimum arbiter 105 adopts a hybrid domain arbitration structure, which includes an analog comparator C501, a SEL inverter I502, a first CMOS transmission gate T503, and a second CMOS transmission gate T504. The non-inverting input of analog comparator C501 is connected to the first compensation quantity V. CS,comp The inverting input of analog comparator C501 is connected to the second compensation quantity V. TON,comp The analog comparator C501 is used to compare the first compensation amount V. CS,comp With the second compensation amount V TON,comp The size of the signal is determined, and a digital control signal SEL is output. First compensation amount V CS,comp It is also connected to the signal input terminal of the first CMOS transmission gate T503, and the second compensation amount V TON,comp It is also connected to the signal input terminal of the second CMOS transmission gate T504; The output of analog comparator C501 is connected to the input of inverter I502, the first control terminal of the first CMOS transmission gate T503, and the first control terminal of the second CMOS transmission gate T504, respectively. The output terminal of inverter I502 is connected to the second control terminal of the first CMOS transmission gate T503 and the second control terminal of the second CMOS transmission gate T504, respectively, so as to provide complementary gating signals to the first CMOS transmission gate T503 and the second CMOS transmission gate T504. The output of the first CMOS transmission gate T503 and the output of the second CMOS transmission gate T504 are connected to the same output node and used to output the control correction value VCtrl; Among them, the first CMOS transmission gate T503 and the second CMOS transmission gate T504 are complementaryly turned on under the control of the digital control signal SEL; When the first compensation amount V CS,comp Less than the second compensation amount V TON,comp When the digital control signal SEL is low, the first CMOS transmission gate T503 is turned on and the first compensation amount V is applied. CS,comp VCtrl serves as a control correction value; When the first compensation amount V CS,comp Greater than the second compensation amount V TON,comp At this time, the digital control signal SEL is high, the second CMOS transmission gate T504 is turned on, and V... TON,comp VCtrl is used as a control correction variable.

[0066] This method features a fast comparator response, outputs a continuous analog signal with no quantization error, and the CMOS transmission gates naturally support bidirectional conduction, making it the preferred solution for IC mass production.

[0067] Example 2

[0068] Based on the same inventive concept, this embodiment provides a control method for suppressing the bias magnetization of an asymmetric half-bridge converter. The principle of solving the problem is similar to that of the controller for suppressing the bias magnetization of an asymmetric half-bridge converter, and the repeated parts will not be described again.

[0069] This embodiment provides a control method for suppressing the bias magnetism of an asymmetric half-bridge converter, including: Receive primary current sampling signal V CS (t), and trigger peak sampling at the turn-off edge of each high-side switch, capture the sampled voltage at the peak of the inductor current in the current cycle, and output the held value V. CS,pk ; According to the retention value V CS,pk Generate the first compensation amount V CS,comp ; The system receives the negative voltage signal generated by the transformer auxiliary winding during the conduction of the high-side switch tube, and performs sampling and holding for two consecutive high-side conduction cycles. The difference between the two sampled values ​​is calculated to obtain the resonant capacitor voltage asymmetry detection quantity. The difference between the two sampled values ​​is proportional to the asymmetry of the resonant capacitor voltage in adjacent cycles. The second compensation value V is generated based on the difference between the two sampled values. TON,comp ; For the first compensation amount V CS,comp and the second compensation amount V TON,comp Perform minimum value arbitration, select the smaller of the two values, and output the control correction amount V. Ctrl ; Based on the voltage feedback signal VFB as the base value, and according to the control correction amount V Ctrl Generates a dynamic reference voltage signal V for turning off the high-side switch. HS_off ; The primary current sampling signal V is compared during the conduction of the high-side switch. CS (t) and the dynamic reference voltage signal V HS_off and in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off At that time, a shutdown command is output to turn off the high-side switch transistor driven by the high-side drive module 108.

[0070] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0072] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0073] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0074] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A controller for suppressing bias magnetization in an asymmetric half-bridge converter, the controller being integrated within a control chip (100), the control chip (100) driving the high-side switch (N201) and low-side switch (N202) of the asymmetric half-bridge converter respectively via a high-side drive module (108) and a low-side drive module (109), characterized in that, include: The CS sample / hold module (101) is used to receive the primary current sampling signal V. CS (t), and trigger peak sampling on the turn-off edge of each high-side switch (N201), capture the sampled voltage at the peak moment of the current cycle inductor current, and output the held value V. CS,pk ; A CS linear compensator (102), connected to the CS sample / hold module (101), is used to adjust the value V based on the held value V. CS,pk Generate the first compensation amount V CS,comp ; The VCr asymmetric detection module (103) is used to receive the negative voltage signal generated by the auxiliary winding of the transformer (T203) during the conduction of the high-side switching transistor (N201), and to perform sampling and holding for two consecutive high-side conduction cycles, calculating the difference between the two sampled values. The difference between the two sampled values The asymmetry is proportional to the voltage of the adjacent periodic resonant capacitor (C205); The Ton nonlinear compensator (104), connected to the VCr asymmetric detection module (103), is used to calculate the difference between the two sampled values. Generate the second compensation quantity V TON,comp ; The minimum arbitrator (105), connected to the CS linear compensator (102) and the Ton nonlinear compensator (104) respectively, is used to obtain the first compensation amount V CS,comp and the second compensation amount V TON,comp Select the smaller value and output the control correction amount V. Ctrl ; Subtractor (106), connected to the minimum arbitrator (105), is used to provide a voltage feedback signal V. FB Based on the base value, and according to the control correction amount V Ctrl The dynamic reference voltage signal V generated when the high-side switch (N201) is turned off. HS_off ; The PWM logic control module (107) is connected to the subtractor (106), the CS sample / hold module (101), the high-side drive module (108), and the low-side drive module (109), respectively. The PWM logic control module (107) is used to compare the primary-side current sampling signal V during the conduction of the high-side switch (N201). CS (t) and the dynamic reference voltage signal V HS_off and in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off When the high-side drive module (108) drives the high-side switch (N201) to turn off, a shutdown command is output.

2. The controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The asymmetric half-bridge converter also includes a transformer (T203), a resonant inductor (Lr), a resonant capacitor (C205), a rectifier diode (D204), an output filter capacitor (C209), and a load resistor (Rload). The transformer (T203) includes a primary winding, a secondary winding, and an auxiliary winding. The primary winding includes a primary inductance (L... pr The secondary winding includes the secondary inductor (L). sec The auxiliary winding includes an auxiliary inductor (L...). aux ), primary inductance (L pr ), secondary inductor (L) sec ) and auxiliary inductor (L aux Coupling via magnetic core; The source, resonant inductor (Lr), and primary inductor (L) of the high-side switch (N201) pr The sources of the resonant capacitor (C205) and the low-side switch (N202) are connected in sequence; Secondary inductor (L) sec One end of the capacitor is connected to the positive terminal of the rectifier diode (D204). The negative terminal of the rectifier diode (D204), one end of the output filter capacitor (C209), and one end of the load resistor (Rload) are connected to the output terminal of the secondary winding. The output terminal of the secondary winding can output the secondary output voltage V. OUT Secondary inductor (L) sec The other end of the output filter capacitor (C209) and the other end of the load resistor (Rload) are grounded; The source of the low-side switching transistor (N202) is grounded through the primary-side current sampling resistor (R206). The primary-side current sampling resistor (R206) converts the primary-side current signal into a primary-side current sampling signal V. CS After (t), it is sent to the CS sample / hold module (101). The induced voltage of the auxiliary winding of the transformer (T203) is sent to the ZCD pin of the VCr asymmetric detection module (103) after passing through the first current-limiting voltage divider resistor (R207) and the second current-limiting voltage divider resistor (R208).

3. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 2, characterized in that, It also includes a feedback signal generation module, which is used to generate a feedback signal based on the secondary output voltage V. OUT Generate the voltage feedback signal V FB The feedback signal generation module includes an optocoupler (O217), a controllable precision voltage regulator (T217), an external voltage divider resistor network, and a filter capacitor bank. The external voltage divider resistor network includes a first voltage divider resistor (R210), a second voltage divider resistor (R211), a third voltage divider resistor (R212), a fourth voltage divider resistor (R213), and a fifth voltage divider resistor (R214). The filter capacitor bank includes a first filter capacitor (C215) and a second filter capacitor (C216). Among them, the two ends of the series connection between the first voltage divider resistor (R210) and the second voltage divider resistor (R211) are respectively connected to the output terminal of the secondary winding and the ground terminal; One end of the third voltage divider resistor (R212) is connected to the output terminal of the secondary winding, and the other end is connected to one end of the light-emitting side of the optocoupler (O217) and one end of the fourth voltage divider resistor (R213); The other end of the fourth voltage divider resistor (R213) is connected to the other end of the light-emitting side of the optocoupler (O217) and the first end of the controllable precision voltage regulator (T217), and the second end of the controllable precision voltage regulator (T217) is grounded; The third terminal of the controllable precision voltage regulator (T217) is connected between the first voltage divider resistor (R210) and the second voltage divider resistor (R211); The two ends of the first filter capacitor (C215) and the fifth voltage divider resistor (R214) connected in series are respectively connected to the first end of the controllable precision voltage regulator (T217) and between the first voltage divider resistor (R210) and the second voltage divider resistor (R211); The two ends of the second filter capacitor (C216) are respectively connected to the first end of the controllable precision voltage regulator (T217) and between the first voltage divider resistor (R210) and the second voltage divider resistor (R211); The output of the optocoupler (O217) is connected to the input of the subtractor (106), and the output voltage feedback signal V is obtained through the optocoupler (O217). FB .

4. The controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The CS sampling / hold module (101) includes a leading-edge effect shielding circuit and a peak sampling and holding circuit; The leading-edge effect shielding circuit is used for shielding time t after each turn-on of the high-side switch (N201). blank Shielding the primary current sampling signal V CS The sampling input of (t) is used to filter out the current spikes caused by the charging and discharging of parasitic capacitance during the turn-on of the high-side switch (N201); The peak sampling and holding circuit is used during the shielding time t blank After completion, the primary current sampling signal V is monitored. CS (t), and triggers peak sampling and holding on the turn-off edge of the high-side switch (N201), outputting the holding value V corresponding to the peak inductor current of the current cycle. CS,pk And maintain it until the next sampling trigger edge.

5. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The first compensation amount is: V CS,comp =K CS (V IN ,V OUT )×V CS,pk ; Wherein, the slope coefficient K CS Based on the input bus voltage V IN With output voltage V OUT Adaptive adjustment; V CS,pk To preserve the value.

6. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 2, characterized in that, The VCr asymmetric detection module (103) includes a negative feedback transimpedance amplifier circuit, a current mirror, a sampling resistor (R310), a Toggle trigger (F307), a first sample-and-hold circuit (F308), and a second sample-and-hold circuit (F309). The negative feedback transimpedance amplifier circuit includes an on-chip operational amplifier (O301) and an NMOS transistor (N302). The current mirror includes a first PMOS transistor (P303), a second PMOS transistor (P304), a third PMOS transistor (P305), and a fourth PMOS transistor (P306). The non-inverting input of the on-chip operational amplifier (O301) is connected to a 0V reference, and the inverting input of the on-chip operational amplifier (O301) is connected to the source of the NMOS transistor (N302). The output of the on-chip operational amplifier (O301) is connected to the gate of the NMOS transistor (N302); The source of the NMOS transistor (N302) is connected between the first current-limiting voltage divider resistor (R207) and the second current-limiting voltage divider resistor (R208); The gates of the second PMOS transistor (P304) and the fourth PMOS transistor (P306) are connected, and the gates of the first PMOS transistor (P303) and the third PMOS transistor (P305) are connected. The drain of the first PMOS transistor (P303) is connected to the source of the second PMOS transistor (P304), and the drain of the third PMOS transistor (P305) is connected to the source of the fourth PMOS transistor (P306). The source of the first PMOS transistor (P303) is connected to its own gate, and the source of the second PMOS transistor (P304) is connected to its own gate. The drains of the second PMOS transistor (P304) and the fourth PMOS transistor (P306), as well as the control input of the Toggle flip-flop (F307), are connected to the internal power supply; the clock input of the Toggle flip-flop (F307) is connected to the high-side switch drive signal HG. One end of the sampling resistor (R310) is connected to the source of the third PMOS transistor (P305), and the other end of the sampling resistor (R310) is grounded. The source of the third PMOS transistor (P305) is connected to the data input terminal of the first sample-and-hold circuit (F308) and the data input terminal of the second sample-and-hold circuit (F309), respectively. The positive output of the Toggle flip-flop (F307) is connected to the clock input of the first sample-and-hold circuit (F308); The inverting output of the Toggle flip-flop (F307) is connected to the clock input of the second sample-and-hold circuit (F309).

7. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The minimum arbitrator (105) adopts a digital domain arbitration structure, which includes: The first analog-to-digital converter and the second analog-to-digital converter are used to respectively convert the first compensation amount V CS,comp and the second compensation amount V TON,comp Quantized into a first digital code and a second digital code; A digital comparator is used to compare the magnitudes of the first digital code and the second digital code, and outputs a selection signal; A digital multiplexer is used to select the digital code corresponding to the smaller value according to the selection signal; The digital-to-analog converter converts the digital code selected by the digital multiplexer into an analog voltage signal, which serves as the control correction quantity V. Ctrl .

8. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The minimum arbiter (105) adopts an analog domain arbitration structure, which includes a first operational amplifier (O401), a second operational amplifier (O402), a third operational amplifier (O403), a first diode (D404), a second diode (D405), and a pull-up resistor (R406). The non-inverting input of the first operational amplifier (O401) is connected to the second compensation value V. TON,comp ; The output of the first operational amplifier (O401) is connected to the common output node through the first diode (D404); The non-inverting input of the second operational amplifier (O402) is connected to the first compensation value V. CS,comp ; The output of the second operational amplifier (O402) is connected to the common output node via the second diode (D405); The inverting inputs of the first operational amplifier (O401) and the second operational amplifier (O402) are each connected to a common output node; The common output node is connected to the internal power supply via a pull-up resistor (R406); The non-inverting input of the third operational amplifier (O403) is connected to the common output node, and the inverting input of the third operational amplifier (O403) is connected to its own output. The third operational amplifier (O403) can output a control correction value V. Ctrl .

9. A controller for suppressing bias magnetism in an asymmetric half-bridge converter according to claim 1, characterized in that, The minimum arbiter (105) adopts a hybrid domain arbitration structure, which includes an analog comparator (C501), a SEL inverter (I502), a first CMOS transmission gate (T503), and a second CMOS transmission gate (T504). The non-inverting input of the analog comparator (C501) is connected to the first compensation quantity V. CS,comp The inverting input of the analog comparator (C501) is connected to the second compensation quantity V. TON,comp The analog comparator (C501) is used to compare the first compensation amount V. CS,comp With the second compensation amount V TON,comp The size of the signal is determined, and a digital control signal SEL is output. First compensation amount V CS,comp It is also connected to the signal input terminal of the first CMOS transmission gate (T503), and the second compensation amount V TON,comp It is also connected to the signal input terminal of the second CMOS transmission gate (T504); The output of the analog comparator (C501) is connected to the input of the inverter (I502), the first control terminal of the first CMOS transmission gate (T503), and the first control terminal of the second CMOS transmission gate (T504), respectively. The output of the inverter (I502) is connected to the second control terminal of the first CMOS transmission gate (T503) and the second control terminal of the second CMOS transmission gate (T504) respectively, so as to provide complementary gating signals to the first CMOS transmission gate (T503) and the second CMOS transmission gate (T504); The output of the first CMOS transmission gate (T503) and the output of the second CMOS transmission gate (T504) are connected to the same output node and used to output the control correction value VCtrl; Among them, the first CMOS transmission gate (T503) and the second CMOS transmission gate (T504) are complementaryly turned on under the control of the digital control signal SEL; When the first compensation amount V CS,comp Less than the second compensation amount V TON,comp When the digital control signal SEL is low, the first CMOS transmission gate (T503) is turned on and the first compensation amount V is applied. CS,comp VCtrl serves as a control correction value; When the first compensation amount V CS,comp Greater than the second compensation amount V TON,comp At this time, the digital control signal SEL is high, the second CMOS transmission gate (T504) is turned on, and V... TON,comp VCtrl is used as a control correction variable.

10. A control method for suppressing bias magnetism in an asymmetric half-bridge converter, characterized in that, include: Receive primary current sampling signal V CS (t), and trigger peak sampling on the turn-off edge of each high-side switch (N201), capture the sampled voltage at the peak moment of the current cycle inductor current, and output the held value V. CS,pk ; According to the retention value V CS,pk Generate the first compensation amount V CS,comp ; The system receives the negative voltage signal generated by the auxiliary winding of the transformer (T203) during the conduction of the high-side switching transistor (N201), performs sample-and-hold for two consecutive high-side conduction cycles, and calculates the difference between the two sample values. The difference between the two sampled values The asymmetry is proportional to the voltage of the adjacent periodic resonant capacitor (C205); Based on the difference between the two sampled values Generate the second compensation quantity V TON,comp ; For the first compensation amount V CS,comp and the second compensation amount V TON,comp Perform minimum value arbitration, select the smaller of the two values, and output the control correction amount V. Ctrl ; With voltage feedback signal V FB Based on the base value, and according to the control correction amount V Ctrl The dynamic reference voltage signal V generated when the high-side switch (N201) is turned off. HS_off ; The primary current sampling signal V is compared during the conduction of the high-side switch (N201). CS (t) and the dynamic reference voltage signal V HS_off and in the primary side current sampling signal V CS (t) reaches the dynamic reference voltage signal V HS_off When the high-side drive module (108) drives the high-side switch (N201) to turn off, a shutdown command is output.

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