A current limiting control circuit, a buck converter, and a current limiting control method

Abstract

This application provides a current-limiting control circuit, a buck converter, and a current-limiting control method. The circuit includes: a bias generation module that generates a control voltage in response to real-time operating information of the voltage converter and outputs a bias current accordingly; an isolation detection module connected to the bias generation module, configured to turn on or off in response to the voltage state of the switching node, and outputting a detection voltage based on the bias current and the voltage of the switching node; and a control intervention module connected to the isolation detection module and the voltage converter, configured to adjust the duty cycle of the voltage converter in response to the comparison result of the detection voltage and a preset reference voltage. This application achieves current detection by superimposing the bias current and the voltage of the switching node, and achieves dynamic adjustment of the current-limiting threshold through an adjustable bias current, enabling the voltage converter to adaptively adjust the overcurrent protection point according to real-time operating conditions.

Description

Technical Field

[0001] This application relates to the field of current limiting protection, and in particular to a current limiting control circuit, a buck converter, and a current limiting control method. Background Technology

[0002] Voltage converters are widely used in portable energy storage, industrial control, and high-power power management systems for voltage conversion and battery charge / discharge management. During system operation, dynamic changes in load or short circuits at the output can easily lead to uncontrolled inductor current, thereby damaging the power switching transistors. Therefore, overcurrent protection is an indispensable component of voltage converters. Among these, valley current limiting is a commonly used protection strategy for high-power voltage converters because it is detected during the conduction period of the lower transistor and does not produce leading-edge blanking.

[0003] However, most existing voltage converters use an internally fixed current source matched with an external current sensing resistor to set the current limiting threshold. Once the hardware circuit is finalized, the current limiting threshold is physically locked. In complex battery energy storage systems, the system controller often needs to dynamically adjust the upper limit of charging and discharging power based on the battery's real-time state of charge, ambient temperature, or fluctuations in front-end input power. Traditional purely hardware-based current limiting architectures cannot meet the requirements of adaptive dynamic adjustment.

[0004] Furthermore, valley current detection requires measuring the weak negative voltage signal at the switching node when the lower transistor is on. However, this node jumps to a high input voltage when the upper transistor is on, and ordinary external low-voltage analog devices directly connected to this node will be instantly damaged. Existing technologies typically rely on isolation amplifiers or magnetic isolation devices to achieve external detection, which greatly increases the system cost and size. Summary of the Invention

[0005] This application aims to solve the problem that the overcurrent protection threshold of existing voltage converters is fixed in hardware and cannot be dynamically adjusted.

[0006] In a first aspect, this application provides a current limiting control circuit, comprising: a bias generation module configured to generate a control voltage in response to real-time operating information of a voltage converter, and output a bias current according to the control voltage; an isolation detection module connected to the bias generation module and the switching node of the voltage converter, configured to turn on or off in response to the voltage state of the switching node; the isolation detection module is further configured to detect the voltage of the switching node in response to the bias current, and output a detection voltage; and a control intervention module connected to the isolation detection module and the voltage converter, configured to adjust the duty cycle of the voltage converter in response to a comparison result between the detection voltage and a preset reference voltage.

[0007] Secondly, this application also provides a buck converter, comprising: a main power module including an upper transistor, a lower transistor, and an inductor, wherein the source of the upper transistor and the drain of the lower transistor are connected to form a switching node, a first end of the inductor is connected to the switching node, and a second end of the inductor is connected to a load; a current limiting control circuit as described in the first aspect; a buck controller for controlling the switching of the upper transistor and the lower transistor; and a feedback compensation module connected to the output terminal of the main power module, the feedback terminal of the buck controller, and an error compensation terminal, wherein, in response to the output voltage of the main power module, a feedback voltage is output to the buck controller, such that when the detected voltage rises to a level higher than the preset reference voltage, the buck controller raises the voltage at the error compensation terminal cycle by cycle.

[0008] Thirdly, this application also provides a current limiting control method applied to a voltage converter including an inductor. The method includes: generating a control voltage based on real-time operating information of the voltage converter, and generating a bias current based on the control voltage; detecting the voltage of the switching node of the voltage converter, and generating a detection voltage in combination with the bias current; and adjusting the duty cycle of the voltage converter based on the comparison result between the detection voltage and a preset reference voltage.

[0009] At least one advantage of the current limiting control circuit, buck converter, and current limiting control method provided in this application is that, by using a bias generation module to output an adjustable bias current in response to real-time operating condition information, the overcurrent protection threshold can be dynamically adjusted according to the system operating state, thus overcoming the limitation of the fixed current limiting threshold in traditional hardware; and by using a control intervention module to adjust the duty cycle of the voltage converter in response to the comparison result between the detected voltage and the preset reference voltage, a fast overcurrent response cycle by cycle and smooth recovery after protection is released are achieved. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0011] Figure 1 A schematic diagram of a current limiting control circuit provided for an embodiment of the present invention; Figure 2 A schematic diagram of the structure of an offset generation module provided for an embodiment of the present invention; Figure 3 The specific circuit structure of the bias generation module is shown. Figure 4 The specific circuit structure of the isolation detection module is shown; Figure 5The specific circuit structure of the control intervention module is shown; Figure 6 A circuit schematic diagram of a buck converter provided for an embodiment of the present invention; Figure 7 for Figure 6 The diagram shows the current limiting timing diagram of the buck converter during operation. Figure 8 This is a flowchart illustrating a current limiting control method provided for an embodiment of the present invention. Detailed Implementation

[0012] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0013] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0014] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0015] Please see Figure 1 , Figure 1 This is a schematic diagram of a current limiting control circuit provided in an embodiment of this application. Figure 1 As shown, the current limiting control circuit 100 is applied to the voltage converter.

[0016] In this application, a switching node refers to a circuit node in a voltage converter that periodically switches between different voltage levels as the switching transistor is turned on and off. The specific location of the switching node varies in different voltage converter topologies: in a buck converter, the switching node is the connection point between the upper and lower transistors; in a boost converter, the switching node is the connection point between the switching transistor and a freewheeling diode. A common characteristic of switching nodes is that their voltage switches between high and low levels at different stages of the switching cycle, and at specific stages, the inductor current flowing through the on-resistance of the switching transistor generates a voltage signal at that node proportional to the inductor current.

[0017] In this embodiment, a buck converter is used as an example for illustration. The buck converter 200 includes an upper transistor Q1, a lower transistor Q2, an inductor LD1, and a buck controller 220. The source of the upper transistor Q1 is connected to the drain of the lower transistor Q2 and the first terminal of the inductor LD1, forming a switching node SW.

[0018] The second terminal of inductor LD1 is connected to the output terminal VOUT, supplying power to the load Rload. The buck controller 220 drives the upper transistor Q1 and the lower transistor Q2 alternately to conduct via the high-side drive signal HO and the low-side drive signal LO, respectively, to achieve voltage conversion. The buck controller 220 has an error compensation terminal; the voltage at this terminal is driven by the internal error amplifier of the buck controller 220, and its voltage level directly determines the duty cycle of the PWM output.

[0019] The current limiting control circuit 100 includes a bias generation module 110, an isolation detection module 120, and a control intervention module 130. The current limiting control circuit 100 interacts with the buck converter 200 through two interfaces: the isolation detection module 120 is connected to the switching node SW, and the control intervention module 130 is connected to the error compensation terminal of the buck controller 220. The connection node between the isolation detection module 120 and the bias generation module 110 forms the detection node DET.

[0020] Specifically, the bias generation module 110 is configured to generate a control voltage in response to real-time operating information of the buck converter 200, and output a bias current based on the control voltage. In this embodiment, the control voltage is an analog voltage signal.

[0021] Real-time operating information refers to system parameters that reflect the current operating status of the buck converter 200, including but not limited to input power, battery state of charge, and ambient temperature.

[0022] The bias current is proportional to the control voltage; when the control voltage increases, the bias current increases accordingly, and when the control voltage decreases, the bias current decreases accordingly. By changing the magnitude of the control voltage, the bias current can be adjusted in real time, thereby dynamically changing the current limiting threshold.

[0023] The isolation detection module 120 is connected to the switching node SW and the bias generation module 110 respectively. The isolation detection module 120 is configured to turn on or off in response to the voltage state of the switching node SW.

[0024] During each switching cycle of the buck converter 200, the voltage at the switching node SW changes with the alternating conduction of the upper transistor Q1 and the lower transistor Q2. Specifically, when the upper transistor Q1 is turned on, the voltage at the switching node SW jumps instantaneously to the input voltage BAT+, and this high voltage is conducted through one end of the isolation detection module 120. Upon sensing the high voltage jump at the switching node SW, the isolation detection module 120 automatically turns off, isolating the high voltage on the side closest to the switching node SW. This ensures that the detection node DET, as well as the bias generation module 110 and the control intervention module 130 connected to it, are always in a safe low-voltage environment and will not be damaged by breakdown.

[0025] When the lower transistor Q2 is turned on, the inductor current freewheels through Q2, and the switching node SW presents a negative voltage. The isolation detection module 120 then automatically turns on, connecting the detection loop from the bias generation module 110 through the isolation detection module 120 to the switching node SW. This adaptive turn-on and turn-off behavior requires no external control signal and is entirely achieved by the physical characteristics of the isolation detection module 120 itself.

[0026] Furthermore, during the conduction of the isolation detection module 120, the isolation detection module 120 detects the voltage generated by the inductor current on the switching node SW, and combines this with the bias current output by the bias generation module 110 to output a detection voltage at the detection node DET. In this current path, the bias current flows through the isolation detection module 120 to the switching node SW, generating a positive voltage drop as it flows through the sampling resistor inside the isolation detection module 120. Simultaneously, a negative voltage is present on the switching node SW due to the inductor current flowing through the on-resistance of the lower transistor Q2.

[0027] The detection voltage at the detection node DET is the sum of the aforementioned positive voltage drop and the negative voltage at the switching node. During normal operation, the positive voltage drop generated by the bias current flowing through the sampling resistor dominates, and the detection voltage is positive. As the inductor current increases, the negative voltage at the switching node deepens, and the detection voltage gradually decreases. When the inductor current exceeds the current limiting threshold determined by the bias current and the sampling resistor, the negative voltage exceeds the positive voltage drop, and the detection voltage becomes negative.

[0028] The control intervention module 130 is connected to the detection node DET and the buck converter 200 respectively, and is configured to adjust the duty cycle of the switching cycle of the buck converter 200 in response to the comparison result of the detection voltage and the preset reference voltage.

[0029] Specifically, the control intervention module 130 is connected to the detection node DET and the error compensation terminal COMP of the step-down controller 220, continuously monitors the detection voltage on the detection node DET, and intervenes in the error compensation terminal COMP according to the comparison result of the detection voltage and the preset reference voltage.

[0030] The so-called preset reference voltage refers to the reference voltage used inside the control intervention module 130 for comparison with the detection voltage.

[0031] Taking a buck converter as an example, the duty cycle refers to the proportion of the on-time of the upper transistor Q1 in the PWM signal output by the buck controller 220 to the entire switching cycle. Adjusting the duty cycle means adjusting the on-time of the upper transistor Q1 in each switching cycle. When the duty cycle decreases, the on-time of the upper transistor Q1 is shortened, the energy injected into the inductor LD1 decreases, and the inductor current decreases accordingly; when the duty cycle is zero, the upper transistor Q1 does not conduct during the entire switching cycle, and the inductor current only decays in the freewheeling circuit of the lower transistor Q2.

[0032] During the operating period when the inductor current of the buck converter 200 is within a safe range, the detected voltage remains higher than the preset reference voltage. At this time, the output of the control intervention module 130 remains in a high-impedance state, neither injecting current into nor drawing current from the error compensation terminal, thus having no effect on the voltage at the error compensation terminal. The error amplifier inside the buck controller 220 autonomously controls the voltage at the error compensation terminal, and the buck converter 200 operates in normal working condition.

[0033] When the detected voltage is lower than the preset reference voltage, it indicates that the inductor current has exceeded the currently set current limiting threshold. The control intervention module 130 then pulls down the voltage at the error compensation terminal. After the voltage at the error compensation terminal is pulled down, the PWM comparator inside the buck controller 220 outputs zero duty cycle because the voltage at the error compensation terminal is lower than the sawtooth wave. The effective conduction pulse of the upper transistor Q1 in subsequent switching cycles is blocked, and the upper transistor Q1 no longer conducts. Since no new energy is injected into the inductor LD1 from the input terminal, the inductor current continues to decay in the freewheeling circuit of the lower transistor Q2.

[0034] When the inductor current decays below the current limiting threshold, the negative voltage at the switching node decreases, and the detection voltage rises back above the preset reference voltage. At this point, the control intervention module 130 stops pulling down the voltage at the error compensation terminal. The output of the error amplifier inside the buck controller 220 is no longer suppressed, the voltage at the error compensation terminal gradually rises, the duty cycle gradually recovers from its extremely narrow range, the effective conduction pulse of the upper transistor Q1 gradually recovers, and the inductor current smoothly recovers to the normal operating level.

[0035] In other embodiments, the current limiting control circuit 100 is also applicable to the boost converter. The boost converter also has a switching node that is close to ground when the switching transistor is on and jumps to a high output voltage when the freewheeling transistor is on. During the on-state of the switching transistor, the inductor current flowing through the on-resistance of the transistor causes the switching node to exhibit a negative voltage, a characteristic that is physically identical to the negative voltage at the switching node during the on-state of the lower transistor in a buck converter.

[0036] Therefore, by connecting the isolation detection module 120 of the current limiting control circuit 100 to the switching node of the boost converter and the control intervention module 130 to the error compensation terminal of the boost controller, the same dynamic valley current limiting protection function as that of the buck converter can be realized in the boost converter.

[0037] The above embodiments use a buck converter as an example to illustrate the working principle of the current limiting control circuit 100 in detail. Those skilled in the art will understand that the current limiting control circuit 100 is also applicable to other voltage converter topologies that regulate power through duty cycle, such as boost converters.

[0038] In a boost converter, there is also a switching node, which is the connection point between the switching transistor and the freewheeling diode. During the conduction of the switching transistor, the inductor current flows through the on-resistance of the switching transistor, generating a voltage signal at the switching node that is proportional to the inductor current.

[0039] By connecting the isolation detection module 120 of the current limiting control circuit 100 to the switching node of the boost converter and the control intervention module 130 to the error compensation terminal of the boost controller, the same dynamic current limiting protection function as that of the buck converter can be achieved in the boost converter.

[0040] The isolation detection module 120 adaptively turns on or off according to the voltage state of the switching node. It turns off when the switching node presents high voltage to isolate the high voltage, and turns on when the voltage of the switching node decreases to connect the detection circuit. The working mechanism is the same as that in the buck converter, and will not be described in detail here.

[0041] In a boost converter, the duty cycle refers to the proportion of the on-time of the switching transistor to the entire switching cycle. Adjusting the duty cycle is equivalent to adjusting the on-time of the switching transistor.

[0042] It should be noted that the polarity of the voltage generated by the inductor current at the switching node may differ in different voltage converter topologies. The detection principle of this application lies in the superposition and opposition between the voltage drop generated by the bias current and the voltage generated by the inductor current at the detection node. A comparator is used to determine whether the superposition result exceeds the reference voltage to decide whether to trigger protection.

[0043] When the polarity of the voltage generated by the inductor current at the switching node is opposite to that in the buck converter, it can be adapted by adjusting the injection direction of the bias current or swapping the input connection of the comparator, while the detection principle remains unchanged. Therefore, the current limiting control circuit of this application is applicable to any voltage converter topology where power is adjusted by duty cycle and a voltage signal proportional to the inductor current exists at the switching node.

[0044] The isolation detection module 120 automatically shuts off to isolate the high voltage when the freewheeling tube is turned on and the switching node jumps to the output high voltage. When the switching tube is turned on and the switching node presents a negative voltage, it automatically turns on to connect the detection circuit. The working mechanism is completely the same as that in the buck converter, so it will not be described in detail.

[0045] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a bias generation module provided in an embodiment of this application. Figure 2 As shown, the bias generation module 110 includes a generation unit 111, a conversion unit 112, and a current mirror unit 113.

[0046] The generation unit 111 is configured to generate a control voltage in response to real-time operating condition information. As described in the previous embodiment, the real-time operating condition information refers to system parameters reflecting the current operating state of the buck converter 200. The generation unit 111 receives these parameters, processes them internally, and outputs a control voltage V_DAC corresponding to the currently required current limiting threshold. When the system operating condition requires tightening the current limiting threshold, the generation unit 111 decreases V_DAC; when the system operating condition allows for relaxing the current limiting threshold, the generation unit 111 increases V_DAC.

[0047] The conversion unit 112 is connected to the generation unit 111, and the conversion unit 112 is configured to output a conversion current I_ref that is precisely proportional to the control voltage V_DAC in response to the control voltage V_DAC.

[0048] The so-called conversion current refers to the reference current generated by the conversion unit 112 according to the control voltage, which will serve as the input reference for the subsequent current mirror unit 113.

[0049] The current mirror unit 113 is connected to the conversion unit 112 and the isolation detection module 120. The current mirror unit 113 is configured to output a bias current I_LIM in response to the conversion current I_ref.

[0050] The so-called current mirror refers to the current mirror unit 113 copying the conversion current I_ref output by the conversion unit 112 into the bias current I_LIM according to a preset ratio.

[0051] In one embodiment, the preset ratio is 1:1, i.e., I_LIM = I_ref. The output terminal of the current mirror unit 113 is connected to the input terminal of the isolation detection module 120, and the bias current I_LIM flows out from the output terminal and is injected into the switching node SW through the isolation detection module 120.

[0052] Another function of the current mirror unit 113 is to achieve electrical isolation between the conversion unit 112 and the isolation detection module 120. The conversion unit 112 operates on the reference side, and the isolation detection module 120 operates on the mirror side. The two sides are coupled through the mirror relationship of the current mirror unit 113 and do not directly interfere with each other.

[0053] Assuming that the generation unit 111 outputs V_DAC = 1V according to the current system operating conditions, the conversion unit 112 converts the 1V control voltage into a conversion current I_ref = 1V / Rset. Assuming Rset = 10kΩ, then I_ref = 100μA. The current mirror unit 113 replicates I_ref into a bias current I_LIM = 100μA with a 1:1 mirror ratio.

[0054] The bias current flows through the sampling resistor RLIM in the isolation detection module 120 and establishes a positive bias voltage at the detection node DET. When the inductor current exceeds the current limiting threshold, causing the negative voltage at the switching node to exceed the positive bias voltage, the detection voltage drops below the preset reference voltage, triggering the protection action of the control intervention module 130.

[0055] If the system operating conditions change, such as the battery temperature rising and requiring derating, the generation unit 111 will reduce V_DAC to 0.5V, I_ref will become 50μA, I_LIM will be reduced to 50μA, the forward bias voltage of the detection node DET will decrease, and the current limiting threshold will be tightened to achieve dynamic adjustment of the current limiting point.

[0056] Please see Figure 3 , Figure 3 The specific circuit structure of the bias generation module is shown, such as... Figure 3 As shown, the generation unit 111 includes a processor 1111 and a digital-to-analog converter 1112.

[0057] The processor 1111 is configured to generate digital control signals in response to real-time operating condition information.

[0058] The so-called digital control signal refers to the digital quantity that represents the target current limiting threshold, calculated by the processor 1111 based on the current operating conditions. The processor 1111 collects real-time operating condition information through its peripheral sensor interface or communication bus, determines the current current limiting target that should be set after internal calculation, and encodes the target as a digital control signal for output.

[0059] In one embodiment, the processor 1111 is a microcontroller unit (MCU), which integrates an analog-to-digital converter for acquiring analog sensor signals and a communication interface for receiving scheduling instructions from a host system.

[0060] The input terminal of the digital-to-analog converter 1112 is connected to the signal output terminal of the processor 1111, and the output terminal is connected to the input terminal of the conversion unit 112. The digital-to-analog converter 1112 is used to convert the digital control signal output by the processor 1111 into a control voltage V_DAC.

[0061] In one embodiment, the digital-to-analog converter 1112 is integrated inside the processor 1111, that is, the MCU has a built-in DAC. The processor 1111 can update the output value of V_DAC by writing to the DAC register, which has a fast response speed and does not require additional external devices.

[0062] In another embodiment, the digital-to-analog converter 1112 may also be an external DAC chip independent of the processor 1111, communicating with the processor 1111 via an interface such as SPI or I2C.

[0063] Real-time operating condition information refers to system parameters that reflect the current operating status of the buck converter 200. In this embodiment, the real-time operating condition information includes the input power of the buck converter 200, the state of charge of the battery connected to the buck converter 200, and the ambient temperature.

[0064] Input power refers to the available output power of the power supply connected to the input terminal of the buck converter 200. In battery energy storage systems, the front-end input source is typically a photovoltaic panel, adapter, or other power supply equipment, and its available output power fluctuates with external conditions. When the front-end input power is insufficient to support the current charging current, if the current limiting threshold is not lowered in time, the system will draw power from the front end exceeding its supply capacity, which may cause the input voltage to drop or even cause the front-end power supply to enter a protection state.

[0065] The State of Charge (SOC) of a battery refers to the percentage of its total capacity remaining when connected to the buck converter 200. During charging, when the SOC is low, the battery can accept a larger charging current, resulting in high charging efficiency. As the SOC gradually increases, the electrochemical polarization inside the battery intensifies, and continuing to charge with a large current will accelerate battery aging and even pose safety risks. Therefore, the system needs to actively reduce the upper limit of the charging current when the SOC is high.

[0066] Ambient temperature includes the battery temperature and / or the power device temperature of the buck converter 200. Battery temperature directly affects the battery's acceptable charge and discharge capacity. At low temperatures, the battery's internal resistance increases, the lithium-ion diffusion rate decreases, and high-current charging easily causes lithium plating, requiring a reduction in charging current. At high temperatures, battery side reactions intensify, also necessitating derating protection. Power device temperature refers to the operating temperature of power semiconductor devices such as the upper transistor Q1 and lower transistor Q2 in the buck converter 200. When the device temperature approaches its maximum junction temperature, the output power needs to be reduced to prevent thermal damage to the devices.

[0067] Provided the output voltage of the buck converter 200 is stabilized at the target value by the feedback loop, the output power is proportional to the inductor current. Therefore, limiting the charging and discharging power is essentially limiting the upper limit of the inductor current, which is achieved by setting the control voltage V_DAC. The logic for generating the control voltage and the logic for scheduling the charging and discharging power are synchronous and correspond; the control voltage is generated according to the operating condition information, just as the charging and discharging power is scheduled based on the operating condition information.

[0068] Specifically, the processor 1111 maintains the mapping relationship between operating parameters and power limits, and determines the corresponding V_DAC value accordingly. When the battery SOC is close to full charge, the processor 1111 reduces V_DAC to tighten the current limiting threshold, and the charging power decreases accordingly. When the battery temperature or power device temperature exceeds the preset derating temperature threshold, the processor 1111 reduces V_DAC to operate under derating to prevent overheating damage. When the front-end input power decreases, the processor 1111 reduces V_DAC to limit the charging current, so that the input power demand of the buck converter 200 matches the supply capacity of the front end. Conversely, when the SOC is low, the temperature is within a safe range, and the front-end input power is sufficient, the processor 1111 increases V_DAC to relax the current limiting threshold, so that the buck converter 200 operates at higher power, improving charging and discharging efficiency.

[0069] When multiple operating parameters change simultaneously, the processor 1111 takes the minimum value of V_DAC corresponding to each parameter as the final output, ensuring that the system remains within the safe operating range under the most stringent operating constraints.

[0070] Please see Figure 3 The conversion unit 112 includes a first operational amplifier U1A, a third transistor T3, and a setting resistor Rset.

[0071] In this configuration, the non-inverting input of the first operational amplifier U1A is connected to the output of the generation unit 111, receiving the control voltage V_DAC. The inverting input of the first operational amplifier U1A is connected to the emitter of the third transistor T3 and the first terminal of the setting resistor Rset. The output of the first operational amplifier U1A is connected to the base of the third transistor T3. The positive power supply terminal of the first operational amplifier U1A is connected to the power supply VCC, and the negative power supply terminal is connected to the first reference ground GND.

[0072] The collector of the third transistor T3 is connected to the input terminal of the current mirror unit 113. The second terminal of the setting resistor Rset is connected to the first reference ground GND. In this embodiment, the third transistor T3 is an NPN transistor.

[0073] The non-inverting input of the first operational amplifier U1A receives V_DAC, and its output drives the base of the third transistor T3. When the output voltage of the first operational amplifier U1A increases, the base current of the third transistor T3 increases, T3 conducts more deeply, the current from collector to emitter increases, the current flowing through the setting resistor Rset increases accordingly, the voltage drop across Rset increases, and thus the voltage at the inverting input increases. Conversely, when the output voltage of the first operational amplifier U1A decreases, the conduction of T3 decreases, the voltage drop across Rset decreases, and the voltage at the inverting input decreases.

[0074] Because the first operational amplifier U1A has a very high open-loop gain, under the effect of negative feedback, the voltage difference between its non-inverting and inverting input terminals approaches zero. Therefore, the voltage at the inverting input terminal is controlled to be equal to the voltage at the non-inverting input terminal, that is, the voltage across the setting resistor Rset is equal to V_DAC. Thus, the current flowing through the setting resistor Rset can be obtained as:

[0075] This current is the emitter current of the third transistor T3. Due to the collector current of the NPN transistor... With emitter current The relationship is Where α is close to 1 (typically above 0.99), therefore the collector current of the third transistor T3 is approximately equal to its emitter current, i.e., the switching current. .

[0076] The accuracy of the conversion current I_ref depends entirely on the control voltage V_DAC and the setting resistor Rset, and is independent of the parameters of the third transistor T3 itself (such as the current amplification factor β, the base-emitter turn-on voltage Vbe, etc.). Even if the β value of T3 changes with temperature, or there are parameter discrepancies between different batches of devices, as long as the open-loop gain of the first operational amplifier U1A is high enough, the negative feedback loop can automatically adjust the base drive of T3, so that the voltage on Rset always accurately follows V_DAC, ensuring that the conversion accuracy of I_ref is not affected by transistor parameter drift.

[0077] Please see Figure 3 The current mirror unit 113 includes a first transistor T1, a second transistor T2, a first resistor R1, and a second resistor R2. In this embodiment, both the first transistor T1 and the second transistor T2 are PNP type transistors and are a transistor pair with highly matched characteristics.

[0078] The collector of the first transistor T1 is connected to the base of the first transistor T1, the base of the second transistor T2, and the output terminal of the conversion unit 112. The emitter of the first transistor T1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the power supply VCC.

[0079] The emitter of the second transistor T2 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the power supply VCC. The collector of the second transistor T2 is connected to the input terminal of the isolation detection module 120.

[0080] In the above connection, the collector of the first transistor T1 is shorted to its base, forming a diode connection. A diode connection means that the collector and base of the transistor are connected together, making it equivalent to a diode, retaining only the unidirectional conduction characteristic from the emitter to the collector.

[0081] Transistor T1, connected in diode configuration, serves as the reference side of the current mirror, and its collector current is the conversion current I_ref output from the collector of the third transistor T3 in conversion unit 112. Transistor T2 serves as the mirror side of the current mirror, and its collector current is the output bias current I_LIM.

[0082] The conversion current I_ref flows from conversion unit 112 into the collector of the first transistor T1. Since T1 is connected in a diode configuration, the inflow of I_ref causes the base-emitter junction of T1 to conduct in the forward direction, establishing a conduction voltage Vbe1 between the base and emitter of T1. Because the base of T1 is directly connected to the base of T2, the base-emitter voltage Vbe2 of T2 is equal to Vbe1. Assuming T1 and T2 are a matched transistor pair, the same Vbe will drive both transistors to produce the same emitter current density.

[0083] The first resistor R1 and the second resistor R2 are respectively connected in series between the emitters of the first transistor T1 and the second transistor T2 and the power supply VCC, and serve as the emitter resistors of the first transistor T1 and the second transistor T2 respectively.

[0084] The proportional relationship between the bias current I_LIM and the conversion current I_ref is determined by the resistance ratio of the first resistor R1 and the second resistor R2. Denote this proportional relationship as the mirror ratio K, then I_LIM = K × I_ref. When R1 = R2, the emitter currents of the two transistors are equal, K = 1, that is, I_LIM = I_ref; when R2 < R1, the voltage drop across the emitter resistor of T2 is smaller, and the emitter current of T2 is greater than that of T1 under the same Vbe drive, K > 1, that is, I_LIM > I_ref; when R2 > R1, vice versa, K < 1.

[0085] By selecting the ratio of R1 and R2, the range of the bias current can be flexibly adjusted without changing the circuit parameters of the conversion unit 112.

[0086] After introducing the emitter resistors, the emitter current of each transistor generates an additional voltage drop across the corresponding resistor, and this voltage drop introduces local series negative feedback. Under the condition of R1 = R2, when there is a slight offset in Vbe2 of T2 caused by the difference between Vbe1 and Vbe2, this offset is offset by the change in the voltage drop across R2, reducing the error of the mirror current from an exponential relationship to an approximately linear relationship, and significantly improving the mirror accuracy.

[0087] At the same time, the series negative feedback effect of the emitter resistors increases the equivalent output impedance on the mirror side of the current mirror, making I_LIM maintain higher stability when the operating state of the isolation detection module 120 changes, and being closer to the characteristics of an ideal current source.

[0088] Combined with the conversion relationship of the conversion unit 112 , the input-output relationship of the bias generation module 110 is:

[0089] This relationship shows that there is an exact linear proportional relationship between the bias current I_LIM and the control voltage V_DAC, and the proportional coefficient is only determined by the resistance value of the set resistor Rset.

[0090] Please refer to Figure 4 , Figure 4 shows the specific circuit structure of the isolation detection module. The isolation detection module 120 includes a isolation switch tube Q3, a third resistor R3, and a sampling resistor RLIM. In this embodiment, the isolation switch tube Q3 is a high-voltage N-channel enhancement-mode field-effect transistor.

[0091] In this configuration, the source of the isolating switch Q3 is connected to the output of the bias generation module 110, forming a detection node DET. The detection node DET is the connection point between the isolation detection module 120 and the bias generation module 110, specifically the connection point between the source of the isolating switch Q3 and the collector of the second transistor T2. The gate of the isolating switch Q3 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the power supply VCC. The drain of the isolating switch Q3 is connected to the first terminal of the sampling resistor RLIM, and the second terminal of the sampling resistor RLIM is connected to the switching node SW.

[0092] In the above connection, the gate of the isolating switch Q3 is connected to a fixed low-voltage power supply VCC through a third resistor R3, and the gate voltage is constantly biased at the VCC level. The function of the third resistor R3 is to limit the gate charging and discharging current and protect the gate oxide layer from transient current surges. The isolating switch Q3 and the sampling resistor RLIM are connected in series between the detection node DET and the switching node SW. The bias current I_LIM flows out from the output of the bias generation module 110, through the source and drain of Q3, and then through RLIM into the switching node SW.

[0093] When the buck controller 220 drives the upper transistor Q1 to conduct, the input power supply BAT+ charges the inductor LD1 through Q1, and the voltage at the switching node SW jumps instantaneously to near the input voltage BAT+. This high voltage is conducted to the drain of the isolation switch Q3 through the sampling resistor RLIM.

[0094] The gate of Q3 is fixed to VCC via a third resistor R3, typically 5V. When the switching node SW jumps to a high voltage, the high voltage reaches the drain of Q3 via RLIM and is instantaneously coupled to the source of Q3 (i.e., the sensing node DET) through the body diode or parasitic capacitance of Q3, causing the source potential to rise. Since the gate voltage of Q3 is fixed at VCC, the gate-source voltage Vgs of Q3 decreases as the source potential rises. When Vgs drops below the turn-on threshold voltage Vth of Q3, the conduction channel of Q3 turns off.

[0095] After Q3 is turned off, the high voltage on the switching node SW is isolated on the drain side of Q3 and cannot continue to be conducted to the sensing node DET on the source side. The voltage of the sensing node DET is clamped at a safe low voltage level. The second transistor T2 in the bias generation module 110 connected to the sensing node DET and the comparator in the control intervention module 130 will not come into contact with the high voltage, thus obtaining physical protection.

[0096] The isolation process described above is fully adaptive. Q3 automatically turns on and off the conduction channel based on the comparison between its own Vgs and the threshold voltage, without the need for any external control logic or timing signals. Regardless of whether the input voltage BAT+ is 30V, 60V, or 100V, as long as the drain-source withstand voltage rating of Q3 is higher than that of BAT+, the isolation effect can be guaranteed.

[0097] When the buck controller 220 turns off the upper transistor Q1 and drives the lower transistor Q2 to turn on, the energy stored in inductor LD1 drives the inductor current to continue flowing. The inductor current flows from the source (GND_BAT) of the lower transistor Q2 to its drain (switching node SW), generating a voltage drop across the on-resistance Rds_on(Q2), thus lowering the voltage at switching node SW. Become a negative value:

[0098] Where I_inductor is the current inductor current value.

[0099] At this point, the drain of Q3 is connected to the negative voltage switching node SW via RLIM, and the drain potential of Q3 is lower than the source potential. The body diode inherent in Q3 (directed from source to drain) is forward biased and conducts, momentarily pulling the potential of the source (detection node DET) down. After the source potential drops, the gate-source voltage of Q3 rises again. When Vgs exceeds the threshold voltage Vth, the conduction channel of Q3 opens, and Q3 enters a fully conducting state, exhibiting extremely low on-resistance Rds_on(Q3).

[0100] After Q3 is turned on, the bias current I_LIM output by the bias generation module 110 flows from the detection node DET into the source of Q3, reaches the drain through the extremely low internal resistance conduction channel of Q3, and is then injected into the switching node SW through the sampling resistor RLIM.

[0101] In this current path, the voltage drop generated by I_LIM flowing through the sampling resistor RLIM is the forward voltage drop V_RLIM = I_LIM × RLIM (the direction is high potential on the detection node DET side and low potential on the switching node SW side). The voltage drop on the Q3 conduction channel can be ignored because Rds_on(Q3) is extremely small.

[0102] At this time, the detection voltage V_DET on the detection node DET is the superposition of the negative voltage of the switching node SW and the positive voltage drop across the sampling resistor:

[0103] This superposition relationship is the specific mathematical expression of the statement in the aforementioned implementation that "the detection voltage is the sum of the positive voltage drop generated by the bias current flowing through the sampling resistor and the negative voltage caused by the inductor current on the switching node".

[0104] As can be seen from the above formula, the detection voltage V_DET consists of two opposing components: I_LIM × RLIM is the positive component, determined by the bias current, representing the setting of the current limiting threshold; I_inductor × Rds_on(Q2) is the negative component, determined by the inductor current, representing the magnitude of the actual load current.

[0105] When the inductor current I_inductor is small, the negative component is less than the positive component, V_DET is positive, and the system is within a safe range. As the inductor current increases, the negative component gradually increases, and V_DET gradually decreases. When V_DET = 0, the corresponding inductor current is the current limiting threshold I_limit.

[0106] When the inductor current exceeds I_limit, V_DET becomes negative, and the control intervention module 130 will trigger a protection action accordingly.

[0107] Combined with the input-output relationship of the bias generation module 110 The current limiting threshold can be further expressed as:

[0108] The expression clearly shows that the current limiting threshold is proportional to the control voltage V_DAC. The processor 1111 can adjust the current limiting threshold in real time by changing V_DAC to achieve dynamic current limiting function.

[0109] Please see Figure 5 , Figure 5 The specific circuit structure of the control intervention module is shown. The control intervention module 130 includes a comparator U2A. In this embodiment, the comparator U2A is a voltage comparator with open-drain output characteristics.

[0110] In this configuration, the non-inverting input of comparator U2A is connected to the detection node DET, receiving the detection voltage V_DET as described in Embodiment Six. The inverting input of comparator U2A is connected to the first reference ground GND. The output of comparator U2A is connected to the error compensation terminal of the buck controller 220. The positive power supply terminal of comparator U2A is connected to the power supply VCC, and the negative power supply terminal is connected to the first reference ground GND.

[0111] In the above connection, the inverting input of comparator U2A is grounded, meaning the preset reference voltage is ground level (0V). Comparator U2A continuously compares the detected voltage V_DET at the non-inverting input with the ground level at the inverting input, and intervenes in the error compensation terminal through its open-drain output based on the comparison result.

[0112] Open-drain output means that the output stage of comparator U2A contains only one open-drain field-effect transistor (or open-collector transistor). This output stage can only actively pull the output terminal low, and cannot actively drive the output terminal high. When the transistor in the output stage is turned off, the output terminal presents a high impedance state, neither pulled high nor pulled low, and has no effect on external circuits.

[0113] When the inductor current is within a safe range, the forward voltage drop generated by the bias current I_LIM flowing through the sampling resistor RLIM is greater than the negative voltage amplitude caused by the inductor current at the switching node SW. The detected voltage V_DET is positive and higher than the ground level at the inverting input. At this time, comparator U2A determines that the voltage at the non-inverting input is higher than the voltage at the inverting input, the output stage transistor is turned off, and the output terminal exhibits a high impedance state.

[0114] In the high-impedance state, although the output of comparator U2A is physically connected to the error compensation terminal, it neither injects current into nor draws current from the error compensation terminal, and has no effect on the voltage of the error compensation terminal. The error amplifier inside the buck controller 220 completely and autonomously controls the voltage of the error compensation terminal, and outputs a normal PWM signal by comparing it with the internal sawtooth wave, driving the upper transistor Q1 and the lower transistor Q2 to conduct alternately according to the set duty cycle, and the buck converter 200 is in normal working condition.

[0115] If comparator U2A adopts a push-pull output structure, its output will be actively driven to a high level during normal operation. This high level is directly superimposed on the error compensation terminal through the connection between the output terminal and the error compensation terminal, interfering with the normal control of the error amplifier on the voltage of the error compensation terminal, causing the buck converter 200 to fail to work stably.

[0116] When the inductor current exceeds the current limiting threshold I_limit as described in the aforementioned embodiment, the negative voltage amplitude on the switching node SW exceeds the positive voltage drop generated by the bias current flowing through the sampling resistor, and the detected voltage V_DET becomes negative, lower than the ground level of the inverting input. At this time, comparator U2A determines that the voltage at the non-inverting input is lower than the voltage at the inverting input, and the output stage transistor turns on, pulling down the voltage at the error compensation terminal through the open-drain output terminal.

[0117] After the voltage at the error compensation terminal is pulled low, the PWM comparator inside the buck controller 220 compares the voltage at the error compensation terminal with the internal sawtooth wave. When the voltage at the error compensation terminal is pulled low below the valley of the internal sawtooth wave, the COMP voltage remains below the sawtooth wave throughout the entire sawtooth wave cycle. The PWM comparator outputs a constant low level, the buck controller 220 outputs zero duty cycle, and the effective turn-on pulse of the upper transistor in subsequent switching cycles is completely shielded, so the upper transistor Q1 no longer conducts.

[0118] After the upper transistor Q1 is shielded, no new energy is injected into the inductor LD1 from the input power supply BAT+. The inductor current flows only in the freewheeling circuit of the lower transistor Q2 and continues to decay. During this period, during each conduction phase of the lower transistor Q2, the isolation switch Q3 conducts to connect the detection circuit, and the comparator U2A continuously monitors the detection voltage V_DET. If the inductor current is still higher than the current limiting threshold, V_DET remains negative, the comparator U2A continues to maintain a low output level, the voltage at the error compensation terminal is continuously pulled low, and the upper transistor Q1 remains shielded.

[0119] As the inductor current continues to decay in the freewheeling circuit of the lower transistor, the negative voltage amplitude at the switching node SW gradually decreases. When the inductor current decays below the current limiting threshold, the detection voltage V_DET rises back to a positive value, once again exceeding the ground level of the inverting input. Comparator U2A determines that the voltage at the non-inverting input is higher than the voltage at the inverting input, the output stage transistor turns off, the output returns to a high-impedance state, and the pull-down of the error compensation terminal stops.

[0120] After the error compensation terminal is released, the output of the internal error amplifier of the buck controller 220 is no longer suppressed and begins to charge the COMP pin through the compensation network. The voltage at the error compensation terminal gradually rises, the duty cycle gradually recovers, and the effective conduction pulse of the upper transistor Q1 gradually recovers.

[0121] Please see Figure 6 , Figure 6 This is a circuit schematic diagram of a buck converter provided in an embodiment of this application. Figure 6 As shown, the buck converter 200 includes a main power module 210, a buck controller 220, a feedback compensation module 230, and a current limiting control circuit 100 as described in the foregoing embodiments.

[0122] The main power module 210 includes an upper transistor Q1, a lower transistor Q2, and an inductor LD1. The drain of the upper transistor Q1 is connected to the input power supply BAT+, and the source of the upper transistor Q1 is connected to the drain of the lower transistor Q2 and the first terminal of the inductor LD1, forming a switching node SW. The source of the lower transistor Q2 is connected to the battery ground GND_BAT. The second terminal of the inductor LD1 is connected to the output terminal VOUT to supply power to the load Rload.

[0123] On the input side, capacitors C1 and CE1 are connected in parallel between the input power supply BAT+ and the battery ground GND_BAT to decouple and filter the input power supply and suppress the input voltage ripple caused by the switching action of the upper transistor Q1.

[0124] On the output side, capacitors C2 and CE2 are connected in parallel between the output terminal VOUT and the battery ground GND_BAT, forming an LC low-pass filter together with inductor LD1 to filter the high-frequency square wave on the switching node SW into a smooth DC output voltage.

[0125] When the buck converter 200 is operating normally, the buck controller 220 drives the upper transistor Q1 and the lower transistor Q2 to conduct alternately. During the conduction of the upper transistor Q1, the input power supply BAT+ charges the inductor LD1 through Q1, the inductor current rises linearly, and the voltage at the switching node SW is close to BAT+. During the conduction of the lower transistor Q2, the magnetic field energy stored in the inductor LD1 drives the inductor current to continue flowing. The current freewheels through the lower transistor Q2, the inductor current decreases linearly, and the voltage at the switching node SW is the negative voltage drop across the on-resistance of the lower transistor Q2.

[0126] The buck controller 220 is implemented using an integrated control chip U3. The VIN pin (Pin 1) of U3 is connected to the input power supply BAT+ to power the internal circuitry. A bypass capacitor C3 is connected between the VIN pin and battery ground GND_BAT for power supply decoupling. The EN pin (Pin 2) of U3 is connected to the input power supply BAT+ through a resistor R6 to obtain the enable voltage for controlling the chip's startup and shutdown. The PGND pin (Pin 3) of U3 is connected to battery ground GND_BAT, serving as the return path for the power stage.

[0127] The LO pin (Pin 4) of U3 outputs a low-side drive signal, which is connected to the gate of the lower transistor Q2 to control the on / off state of Q2. The HO pin (Pin 5) of U3 outputs a high-side drive signal, which is connected to the gate of the upper transistor Q1 to control the on / off state of Q1. The high-side drive signal HO requires a floating power supply. The CBOOT pin (Pin 8) of U3 is connected to the switching node SW (Pin 7) through the bootstrap capacitor C7. When the lower transistor Q2 is turned on and the potential of the switching node SW is close to GND_BAT, the internal bootstrap charging circuit of the chip charges C7. When the upper transistor Q1 is turned on and the potential of the switching node SW jumps to BAT+, the charge stored in C7 provides a floating power supply for the high-side drive circuit, driving the gate of Q1.

[0128] The EPAD exposed pad (Pin 6) of U3 is connected to the battery ground GND_BAT, serving as a heat dissipation path for the chip. The SW pin (Pin 7) of U3 is connected to the switching node SW, serving as the connection point for detecting the switching node voltage and the high-side drive circuit reference point inside the chip. The AGND pin (Pin 9) of U3 is connected to the first reference ground GND, serving as the signal reference ground for the internal analog circuitry of the chip. The NC pin (Pin 12) of U3 is unconnected.

[0129] The FB pin (Pin 10) of U3 is the feedback input pin, which receives the feedback voltage from the feedback compensation module 230. The COMP pin (Pin 11) of U3 is the error compensation pin, i.e., the error compensation terminal mentioned in the aforementioned embodiment. This pin is the output terminal of the internal error amplifier of U3, connected to an external compensation network, and also connected to the open-drain output terminal of the comparator U2A of the control intervention module 130 in the current limiting control circuit 100.

[0130] The feedback compensation module 230 is connected to the output terminal VOUT of the main power module 210, the FB and COMP terminals of the buck controller 220. The feedback compensation module 230 consists of two parts: a feedback voltage divider network 231 and a compensation network 232.

[0131] The feedback voltage divider network 231 is used to proportionally divide the output voltage VOUT and feed it back to the FB of the buck controller 220, so that the buck controller 220 can sense the actual value of the output voltage and compare it with the internal reference voltage.

[0132] The feedback voltage divider network 231 includes resistor R8, capacitor C4, resistor R9, and resistor R10. The first terminal of resistor R8 is connected to the output terminal VOUT, and the second terminal is connected to FB. The first terminal of capacitor C4 is connected to the output terminal VOUT, and the second terminal is connected to the first terminal of resistor R9. The second terminal of resistor R9 is connected to FB. Resistor R8 provides a direct DC feedback path from VOUT to FB. C4 and R9 are connected in series from VOUT to FB to form a high-frequency feedforward branch, providing additional phase boost at high frequencies and improving the transient response speed of the loop.

[0133] The first terminal of resistor R10 is connected to FB, and the second terminal is connected to the first reference ground GND. The output voltage VOUT is divided by R8 (connected in series with C4 and in parallel with R9) and R10, generating a feedback voltage V_FB at FB. The error amplifier inside the buck controller 220 compares V_FB with the internal reference voltage and outputs an error signal to COMP.

[0134] Compensation network 232 is connected between COMP and FB to shape the closed-loop frequency response characteristics of the error amplifier, ensuring the stability of the voltage loop. Compensation network 232 includes resistor R7, capacitor C5, and capacitor C6. The first terminal of resistor R7 is connected to COMP, and the second terminal is connected to the first terminal of capacitor C6. The second terminal of capacitor C6 is connected to FB. The first terminal of capacitor C5 is connected to the COMP pin, and the second terminal is connected to the FB pin.

[0135] R7 and C6 are connected in series to form a series RC branch from COMP to FB. This branch has a frequency... A zero is introduced at the resonant frequency of the power stage LC circuit to compensate for the phase lag and improve the phase margin of the loop at the crossover frequency. C5 is directly connected between COMP and FB, introducing a high-frequency pole at frequency f_p = 1 / (2π× R7 × C5) (where C5 is much smaller than C6) to attenuate the effect of high-frequency switching noise on the loop.

[0136] The current limiting control circuit 100 interacts with the buck converter 200 through two interfaces. The second terminal of the sampling resistor RLIM in the isolation detection module 120 is connected to the switching node SW. The bias current I_LIM is injected into the switching node SW through the isolation switch Q3 and the sampling resistor RLIM. The open-drain output terminal of the comparator U2A in the control intervention module 130 is connected to the error compensation terminal of the buck controller 220 (i.e., the COMP pin 11 of the U3 chip). When overcurrent is triggered, the comparator U2A pulls the COMP voltage low through its open-drain output.

[0137] During the current limiting protection period, comparator U2A forcibly pulls down the COMP voltage through its open-drain output, resulting in zero duty cycle output of buck controller 220 and the upper transistor Q1 not conducting. Since no new energy is injected into inductor LD1, the output voltage VOUT drops as the load continues to consume energy, and the feedback voltage V_FB of buck controller 220 is correspondingly lower than its internal reference voltage.

[0138] After the error amplifier inside the buck controller 220 detects this deviation, it attempts to increase the duty cycle by outputting a higher voltage through its output terminal (COMP pin) to compensate for the drop in output voltage. However, during the protection period, COMP is controlled to a low level by comparator U2A, and the output of the error amplifier is suppressed.

[0139] Once the inductor current decays below the current-limiting threshold, comparator U2A returns to a high-impedance state, releasing control of COMP. The output of the error amplifier inside the buck controller 220 is no longer suppressed and begins to output current to COMP. This output current flows into capacitors C5 and C6 in the compensation network (through R7), charging these capacitors. Because the capacitor charging process follows the RC time constant, the COMP voltage does not instantaneously step back to the normal operating level, but rather rises gradually with a smooth curve.

[0140] During the rise of the COMP voltage, the PWM comparator inside the buck controller 220 continuously compares the COMP voltage with the internal sawtooth wave. When the COMP voltage just exceeds the valley of the sawtooth wave, the PWM comparator outputs a high level only for a very short time when the sawtooth wave approaches the valley, resulting in a very narrow duty cycle. The upper transistor Q1 is only briefly turned on, and the inductor current rises slightly.

[0141] As the compensation capacitor continues to charge, the COMP voltage increases further, the duty cycle gradually increases, and the inductor current gradually recovers. This process repeats in each switching cycle, with the duty cycle gradually recovering and the inductor current smoothly returning to normal operating levels.

[0142] If the COMP voltage returns to normal, the duty cycle will suddenly jump from zero to a large value, causing the inductor current to rise sharply and potentially exceed the current limiting threshold again, triggering protection. The system then enters a "hiccup" oscillation of repeated triggering and recovery. The gradual recovery cycle avoids this instantaneous current rebound. In addition, the smooth recovery of the inductor current allows the output voltage to recover smoothly to the target value, preventing excessive voltage overshoot on the output capacitor due to sudden current changes, thus protecting the downstream load circuit.

[0143] Please see Figure 7 , Figure 7 The current limiting timing logic diagram provided for the embodiments of this application is as follows: Figure 7 As shown, the timing logic diagram contains waveforms for three channels from top to bottom.

[0144] The first channel shows the inductor current waveform, exhibiting a typical triangular wave shape, reflecting the alternating rise and fall of the current in inductor LD1 during the switching cycle. The inductor current rises linearly during the conduction of the upper transistor Q1 and decreases linearly during the conduction of the lower transistor Q2. A horizontal dashed line is also marked in the figure, representing the valley current limiting point, which is the inductor current value corresponding to the current limiting threshold jointly set by the bias current I_LIM and the sampling resistor RLIM. This current limiting threshold... The position of the valley current limiting point moves up and down as the control voltage V_DAC changes.

[0145] The second channel is the drive signal for the upper transistor Q1, which presents a rectangular pulse waveform. A high level indicates that the upper transistor Q1 is turned on, and a low level indicates that the upper transistor Q1 is turned off. The red dashed line in the figure marks the drive pulse that is pulled low after triggering the current limiting detection, indicating that the upper transistor drive signal is shielded in this cycle.

[0146] The third channel shows the voltage waveform of the error compensation pin COMP, reflecting the changes in COMP voltage during normal operation, overcurrent protection, and soft recovery.

[0147] After the buck converter 200 is powered on, the processor 1111 calculates the initial current limiting target value based on the current real-time operating information and outputs the corresponding control voltage V_DAC through the digital-to-analog converter 1112. V_DAC is converted into a conversion current I_ref by the conversion unit 112, and then mirrored into a bias current I_LIM by the current mirror unit 113. The bias generation module 110 then enters the ready state.

[0148] At the same time, the buck controller 220 starts normally, driving the upper tube Q1 and the lower tube Q2 to conduct alternately through HO and LO, and the output voltage VOUT is gradually established and stabilized at the target value through the feedback compensation module 230. Figure 7 The position of the dashed line at the mid-valley value flow limit point is determined by the I_LIM and RLIM established at this stage.

[0149] The valley of the inductor current triangular wave (the lowest point of the inductor current in each switching cycle) is always higher than the valley current limiting point dashed line, indicating that the inductor current is within the safe range.

[0150] During each switching cycle, while the upper transistor Q1 is on, the voltage at the switching node SW jumps to BAT+. The isolation switch Q3 automatically turns off as its gate-source voltage drops below the threshold, isolating the high voltage at the drain side of Q3. This protects the detection node DET and subsequent circuitry. In the second channel, the upper transistor drive signal exhibits a regular high-level pulse.

[0151] During the conduction of the lower diode Q2, the switching node SW exhibits a negative voltage. The body diode Q3 conducts first, and then the channel is fully turned on. The bias current I_LIM is injected into the switching node SW through Q3 and RLIM, forming a detection voltage V_DET at the detection node DET. Since the inductor current is within the safe range, V_DET is positive and higher than the preset reference voltage (ground level). Comparator U2A outputs a high-impedance state, which has no effect on COMP. In the third channel, the COMP voltage remains at a steady-state level maintained by the error amplifier and the compensation network, and the buck converter 200 outputs normally.

[0152] When the load changes abruptly (such as a sudden increase) or a short circuit occurs at the output, the inductor current rises rapidly. During the conduction phase of the lower transistor Q2 in a certain switching cycle, the inductor current exceeds the current limiting threshold I_limit, the negative voltage amplitude on the switching node SW exceeds the positive voltage drop generated by the bias current flowing through the sampling resistor, and the detection voltage V_DET drops below ground level.

[0153] Comparator U2A detects that the voltage at the non-inverting input is lower than the ground level at the inverting input, and the output stage turns on, pulling the COMP voltage low through the open-drain output. A sharp drop in the COMP voltage can be observed in the third channel at this moment. The COMP voltage is pulled down below the sawtooth trough value inside the buck controller 220, and the buck controller 220 outputs zero duty cycle. The corresponding next upper transistor drive pulse in the second channel disappears; this pulse is marked with a red dashed line to indicate that it was masked.

[0154] After the upper transistor Q1 is disabled, Q1 no longer conducts, and no new energy is injected into inductor LD1 from the input power supply BAT+. The inductor current flows only in the freewheeling loop of the lower transistor Q2. Since the voltage across the inductor is negative (VOUT is higher than the voltage at the switching node SW), the inductor current decreases linearly. In the first channel, a continuous decreasing trend of the inductor current can be observed in this range, with no rising segment.

[0155] During this period, during each conduction phase of the lower transistor Q2, the isolating switch Q3 conducts to connect the detection circuit, and comparator U2A continuously monitors the detection voltage V_DET. If the inductor current is still higher than the current limiting threshold, V_DET remains negative, comparator U2A continues to maintain a low output level, COMP remains controlled at a low level, and the effective conduction pulse of the upper transistor Q1 continues to be shielded. This cycle-by-cycle continuous detection ensures the reliability of the protection; as long as the overcurrent condition is not eliminated, the upper transistor will not falsely reset.

[0156] As the inductor current continues to decay in the freewheeling circuit of the lower transistor, when the inductor current drops below the current limiting threshold, the negative voltage of the switching node decreases, the detection voltage V_DET rises back to above ground level, the comparator U2A output returns to the high impedance state, and releases control over COMP.

[0157] After COMP is released, the error amplifier inside the buck controller 220 detects that the output voltage is lower than the target value and begins to charge COMP through capacitors C5 and C6 in the compensation network. In the third channel, the COMP voltage can be observed to rise smoothly from a low level, rather than a step recovery. When the COMP voltage just exceeds the internal sawtooth trough value, the upper transistor drive pulse reappears in the second channel, but the pulse width is extremely narrow.

[0158] As the COMP voltage continues to rise, the width of the drive pulse gradually increases cycle by cycle, corresponding to a gradual increase in the duty cycle. The inductor current in the first channel gradually recovers as the duty cycle gradually increases, the rising segment reappears but with increasing amplitude, and the inductor current smoothly recovers to the normal operating level.

[0159] The time span of this gradual recovery process is determined by the time constants of R7, C5, and C6 in the compensation network. This soft recovery mechanism avoids repeated protection triggers caused by instantaneous current rebound, and also avoids overshoot in the output voltage due to sudden current changes.

[0160] Throughout the entire operational lifecycle of the buck converter 200, the processor 1111 continuously monitors changes in real-time operating conditions and updates the output value of V_DAC as needed. After each V_DAC update, the bias current I_LIM changes within microseconds. Figure 7 The position of the dashed line at the mid-valley value flow limit point moves up or down accordingly, and the flow limit threshold takes effect in real time.

[0161] Please see Figure 8 , Figure 8 This is a flowchart illustrating a current limiting control method provided in an embodiment of this application. The current limiting control method is applied to a voltage converter including an upper transistor Q1, a lower transistor Q2, and an inductor LD1. The upper transistor Q1 and the lower transistor Q2 are connected to form a switching node SW.

[0162] The following explanation still uses a buck converter as an example, but as described in the previous implementation method, this current limiting control method is also applicable to other voltage converter topologies such as boost converters.

[0163] like Figure 8 As shown, the current limiting control method includes the following steps: Step S100: Generate a control voltage based on the real-time operating information of the voltage converter, and generate a bias current based on the control voltage.

[0164] During operation, the voltage converter system needs to dynamically adjust the upper limit of charging and discharging power based on real-time operating conditions. Assuming the output voltage is stabilized at the target value by the feedback loop, limiting the charging and discharging power essentially means limiting the upper limit of the inductor current.

[0165] Specifically, the processor determines the current allowable upper limit of charging and discharging power based on real-time operating information and generates a control voltage V_DAC accordingly. The control voltage is an analog voltage signal, the amplitude of which corresponds to the required current limiting threshold.

[0166] Real-time operating condition information includes the input power of the voltage converter, the state of charge (SOC) of the battery connected to the voltage converter, and the ambient temperature (battery temperature and / or power device temperature). When the battery SOC is close to full charge, V_DAC is reduced to tighten the current limiting threshold and reduce the charging power; when the battery temperature or power device temperature is too high, V_DAC is reduced to derating and prevent overheating damage; when the front-end input power is insufficient, V_DAC is reduced to limit the charging current and match the supply capacity. When multiple operating parameters change simultaneously, the minimum V_DAC value corresponding to each parameter is taken as the final output, ensuring that the system remains within a safe operating range even under the most stringent operating constraints.

[0167] After the control voltage V_DAC is generated, it is converted into a bias current I_LIM through a voltage-to-current conversion circuit.

[0168] In some embodiments of this application, the voltage-to-current conversion circuit includes a negative feedback closed loop consisting of an operational amplifier, transistors, and a set resistor Rset, and a current mirror circuit consisting of a pair of matched transistors. The operational amplifier controls the conduction level of the transistors through deep negative feedback, ensuring that the voltage across the set resistor is precisely equal to V_DAC, and the current flowing through the set resistor is the conversion current I_ref = V_DAC / Rset. The current mirror circuit replicates the conversion current into a bias current I_LIM = K × V_DAC / Rset according to a mirror ratio K. Due to the presence of the negative feedback closed loop, the accuracy of the bias current depends entirely on V_DAC and Rset, and is unaffected by transistor parameter drift and temperature changes.

[0169] Step S200: Detect the voltage of the switching node of the voltage converter and generate a detection voltage by combining it with the bias current.

[0170] In each switching cycle of the voltage converter, the upper transistor Q1 and the lower transistor Q2 are alternately turned on, and the voltage at the switching node SW changes with the alternation of the turn-on of the upper transistor Q1 and the lower transistor Q2. Specifically, when the lower transistor Q2 is turned on, the energy stored in the inductor LD1 drives the inductor current to continue flowing. The inductor current flows from the source to the drain of the lower transistor Q2, generating a voltage drop across the on-resistance Rds_on of the lower transistor Q2, causing the switching node SW to exhibit a negative voltage V_SW = -I_inductor × Rds_on(Q2). The larger the inductor current, the deeper the negative voltage amplitude at the switching node.

[0171] During the conduction of the lower transistor Q2, the bias current I_LIM is injected into the switching node SW through the sampling resistor RLIM. The bias current flowing through the sampling resistor generates a positive voltage drop V_RLIM = I_LIM × RLIM. An isolating switch is installed in the bias current injection path. This isolating switch automatically turns on when the lower transistor Q2 is on and the switching node SW presents a negative voltage, thus connecting the bias current injection path; and automatically turns off when the upper transistor Q1 is on and the switching node SW jumps to the input high voltage, isolating the high voltage on one side of the switching node and protecting the low voltage detection circuit from being broken down.

[0172] After the bias current is injected into the switching node SW through the isolating switch and sampling resistor, a detection voltage V_DET is formed at the detection node DET between the isolating switch and the bias current output terminal. The detection voltage is the sum of the positive voltage drop generated by the bias current flowing through the sampling resistor and the negative voltage caused by the inductor current on the switching node: V_DET = I_LIM × RLIM - I_inductor × Rds_on(Q2) The detection voltage consists of two opposing components: I_LIM × RLIM is the positive component, determined by the bias current, representing the current limiting threshold setting; I_inductor × Rds_on(Q2) is the negative component, determined by the inductor current, representing the magnitude of the actual load current. When the inductor current is small, the positive component dominates, and the detection voltage is positive; as the inductor current increases, the negative component gradually increases, and the detection voltage gradually decreases; when the detection voltage is equal to zero, the corresponding inductor current is the current limiting threshold I_limit = (I_LIM × RLIM) / Rds_on(Q2) = (K × V_DAC × RLIM) / (Rset ×Rds_on(Q2)).

[0173] Step S300: Adjust the duty cycle of the voltage converter based on the comparison result between the detected voltage and the preset reference voltage.

[0174] The detected voltage V_DET is compared with a preset reference voltage. Taking a buck converter as an example, the duty cycle refers to the proportion of the on-time of the upper transistor Q1 to the entire switching cycle. In other voltage converter topologies, the duty cycle refers to the proportion of the on-time of the corresponding active switching transistor.

[0175] In some embodiments of this application, the preset reference voltage is ground level, the comparison is performed by a comparator with open-drain output, the non-inverting input is connected to the detection node DET, the inverting input is connected to ground level, and the open-drain output is connected to the error compensation terminal COMP of the voltage converter controller.

[0176] For most of the voltage converter's operation, the inductor current remains within a safe range, and the sensed voltage V_DET remains positive, exceeding the preset reference voltage. The comparator output maintains a high impedance state, neither injecting nor drawing current into the error compensation terminal, thus having no effect on the voltage at the error compensation terminal. The voltage converter is in normal operating condition.

[0177] When the inductor current exceeds the current limiting threshold, the detection voltage V_DET is lower than the preset reference voltage, the comparator outputs a low level, and pulls down the voltage of the error compensation terminal COMP through the open-drain output. After the voltage at the error compensation terminal is pulled down below the valley of the sawtooth wave inside the controller, the controller outputs zero duty cycle, the effective conduction pulse of the upper transistor Q1 is shielded, and the upper transistor Q1 no longer conducts.

[0178] Since no new energy is injected into the inductor from the input, the inductor current continues to decay in the freewheeling circuit of the lower transistor Q2. During the decay period, detection and judgment are continuously performed during each conduction phase of the lower transistor. If the inductor current is still higher than the current limiting threshold and the detection voltage is still lower than the preset reference voltage, the comparator continues to maintain a low output level, the error compensation terminal is continuously pulled low, and the effective conduction pulse of the upper transistor continues to be shielded, thus achieving continuous protection cycle by cycle.

[0179] Once the inductor current decays below the current-limiting threshold, the detection voltage V_DET rises back to a positive value, exceeding the preset reference voltage. The comparator output returns to a high-impedance state, ceasing to pull down the error compensation terminal voltage and releasing control over the error compensation terminal. The output of the controller's internal error amplifier is no longer suppressed and begins charging the error compensation terminal through the capacitor in the compensation network.

[0180] Because the capacitor charging process follows an RC time constant, the voltage at the error compensation terminal does not recover instantaneously with a step, but rather rises smoothly. When the voltage at the error compensation terminal just exceeds the sawtooth trough value inside the controller, the duty cycle is extremely narrow, the upper transistor is only briefly turned on, and the inductor current rises slightly. As the voltage at the error compensation terminal continues to rise, the duty cycle gradually increases cycle by cycle, and the inductor current smoothly recovers to the normal operating level. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit it; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A current limiting control circuit, characterized in that, include: The bias generation module is configured to generate a control voltage in response to real-time operating information of the voltage converter, and output a bias current according to the control voltage; An isolation detection module is connected to both the bias generation module and the switching node of the voltage converter, and is configured to turn on or off in response to the voltage state of the switching node; the isolation detection module includes an isolation switch. The isolation detection module is turned off when the switching node presents a high voltage and turned on when the voltage of the switching node decreases; the high voltage is achieved by coupling to raise the source potential of the isolation switch, thereby reducing the gate-source voltage to a level lower than the turn-on threshold voltage of the isolation switch. The isolation detection module is also configured to detect the voltage of the switching node in response to the bias current and output the detection voltage. The control intervention module, connected to the isolation detection module and the voltage converter, is configured to adjust the duty cycle of the voltage converter in response to the comparison result of the detected voltage and the preset reference voltage.

2. The circuit according to claim 1, characterized in that, The bias generation module includes: The generation unit is configured to generate the control voltage in response to the real-time operating condition information; A conversion unit, connected to the generation unit, is configured to output a conversion current in response to a control voltage; The current mirror unit, which is connected to both the conversion unit and the isolation detection module, is configured to output the bias current in response to the conversion current.

3. The circuit according to claim 2, characterized in that, The generation unit includes: The processor is configured to generate digital control signals in response to the real-time operating information; A digital-to-analog converter, wherein the input terminal of the digital-to-analog converter is connected to the signal output terminal of the processor, and the output terminal of the digital-to-analog converter is connected to the input terminal of the conversion unit; The digital-to-analog converter is used to convert the digital control signal into the control voltage.

4. The circuit according to claim 3, characterized in that, The real-time operating information includes the input power of the voltage converter, the state of charge of the battery connected to the voltage converter, and the ambient temperature; the ambient temperature includes the battery temperature and / or the power device temperature of the voltage converter.

5. The circuit according to claim 2, characterized in that, The conversion unit includes a first operational amplifier, a third transistor, and a setting resistor; The non-inverting input of the operational amplifier is connected to the output of the generating unit, the inverting input of the operational amplifier is connected to the emitter of the third transistor and the first end of the set resistor, the output of the operational amplifier is connected to the base of the third transistor, the positive power supply of the operational amplifier is connected to the power supply, and the negative power supply of the operational amplifier is connected to the first reference ground. The collector of the third transistor is connected to the input terminal of the current mirror unit, and the second terminal of the set resistor is connected to the first reference ground.

6. The circuit according to claim 2, characterized in that, The current mirror unit includes a first transistor, a second transistor, a first resistor, and a second resistor; The collector of the first transistor is connected to the base of the first transistor, the base of the second transistor, and the output terminal of the conversion unit. The emitter of the first transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the power supply. The emitter of the second transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the power supply, and the collector of the second transistor is connected to the input terminal of the isolation detection module.

7. The circuit according to claim 1, characterized in that, The voltage converter includes an upper transistor and a lower transistor, and the switching node is the connection node between the upper transistor and the lower transistor; The isolation detection module is configured to turn off in response to the upper pipe being turned on, and to turn on when the lower pipe is turned on, with the switching node presenting a negative voltage. The isolation detection module is also configured to detect the voltage generated by the inductor current on the switching node in response to the bias current, and output the detection voltage; the detection voltage is output at the detection node formed by the connection between the isolation detection module and the bias generation module.

8. The circuit according to claim 7, characterized in that, The isolation detection module also includes a third resistor and a sampling resistor; The source of the isolating switch is connected to the output of the bias generation module to form the detection node. The gate of the isolating switch is connected to the first end of the third resistor. The drain of the isolating switch is connected to the first end of the sampling resistor. The second end of the third resistor is connected to the power supply. The second end of the sampling resistor is connected to the switching node. The detection voltage is the sum of the negative voltage caused by the inductor current on the switching node when the lower transistor is turned on, and the positive voltage drop generated by the bias current flowing through the sampling resistor.

9. The circuit according to claim 1, characterized in that, The control intervention module is connected to the error compensation terminal of the controller of the voltage converter. The control intervention module is configured to pull down the voltage of the error compensation terminal in response to the detection voltage being lower than the preset reference voltage, so as to reduce the duty cycle. And in response to the detection voltage rising back to above the preset reference voltage, stop pulling down the error compensation terminal voltage to restore the duty cycle.

10. The circuit according to claim 9, characterized in that, The voltage converter includes an upper transistor and a lower transistor; in response to the detection voltage being lower than the preset reference voltage, when the control intervention module pulls down the error compensation terminal voltage to less than the preset threshold, the controller outputs a zero duty cycle to shield the upper transistor drive signal in subsequent switching cycles. In response to the detection voltage rising back to above the preset reference voltage, the control intervention module stops pulling down the error compensation terminal voltage, and the controller raises the error compensation terminal voltage cycle by cycle to restore the duty cycle in order to restore the upper transistor drive signal for subsequent switching cycles; The preset threshold is the valley value of the internal sawtooth wave of the controller.

11. The circuit according to claim 9, characterized in that, The control intervention module includes a comparator. The non-inverting input of the comparator is connected to the isolation detection module, the inverting input of the comparator is connected to a first reference ground, the output of the comparator is connected to the error compensation terminal of the controller, the positive power supply terminal of the comparator is connected to the power supply, and the negative power supply terminal of the comparator is connected to the first reference ground.

12. A buck converter, characterized in that, include: The main power module includes an upper transistor, a lower transistor, and an inductor. The source of the upper transistor and the drain of the lower transistor are connected to form a switching node. The first end of the inductor is connected to the switching node, and the second end of the inductor is connected to the load. The current limiting control circuit as described in any one of claims 1-11; A step-down controller is used to control the on / off state of the upper pipe and the lower pipe; The feedback compensation module is connected to the output terminal of the main power module, the feedback terminal of the buck controller, and the error compensation terminal. In response to the output voltage of the main power module, it outputs a feedback voltage to the buck controller, so that when the detected voltage rises back to a level higher than the preset reference voltage, the buck controller raises the voltage of the error compensation terminal cycle by cycle.

13. A current limiting control method, applied to a voltage converter including an inductor and a current limiting control circuit as described in any one of claims 1-11, characterized in that, include: A control voltage is generated based on the real-time operating information of the voltage converter, and a bias current is generated based on the control voltage. The voltage of the switching node of the voltage converter is detected, and a detection voltage is generated by combining it with the bias current; The duty cycle of the voltage converter is adjusted based on the comparison result between the detected voltage and the preset reference voltage.

14. The method according to claim 13, wherein the voltage converter comprises an upper transistor, a lower transistor, and a sampling resistor, characterized in that, The bias current is injected into the switching node through the sampling resistor; During the conduction of the lower transistor, the bias current is injected into the switching node through the sampling resistor; The detection voltage is the sum of the negative voltage caused by the inductor current on the switching node when the lower transistor is turned on, and the positive voltage drop generated by the bias current on the sampling resistor.

15. The method according to claim 13, wherein the voltage converter further comprises a controller, characterized in that, The step of adjusting the duty cycle of the voltage converter based on the comparison result between the detected voltage and the preset reference voltage includes: When the detected voltage is lower than the preset reference voltage, the voltage at the error compensation terminal of the controller is lowered to reduce the duty cycle; When the detection voltage rises back to above the preset reference voltage, the voltage at the error compensation terminal is stopped from being lowered to restore the duty cycle.

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