Data sampling point tuning and tracking

Abstract

Methods, apparatus, systems, and articles of manufacture corresponding to data sampling point tuning and tracking are described. An example device (100) includes a communication interface (110) configurable to receive a data signal, and a processor circuitry (102) coupled to the communication interface (110) and configurable to determine a first timing for sampling the data signal for a first value of a condition, determine a second timing for sampling the data signal for a second value of the condition using the first timing and a prediction compensation model, where the second timing is different than the first timing, measure the condition, select the first timing or the second timing using the measured condition, and program the communication interface (110) to sample using the selected timing.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 727,910, filed December 4, 2024, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This manual generally deals with circuits, and more specifically, with the tuning and tracking of data sampling points. Background Technology

[0004] Electrical devices (e.g., system-on-a-chip (SoC), integrated circuits, semiconductor devices, etc.) can contain components of electronic systems. These components can include microcontrollers, microprocessors, or one or more processor cores on a single substrate or microchip; static and dynamic memory; coprocessor circuitry, such as security circuitry and graphics processing units (GPUs); serial and parallel input / output ports; and networking connections, such as Ethernet, Wi-Fi, power line, and cellular communication interfaces. The device can be coupled to external devices using synchronous half-duplex data transmission protocols, such as the four-wire serial peripheral interface (QSPI) or eight-wire serial peripheral interface (OSPI) protocols. Summary of the Invention

[0005] For data sampling point tuning and tracking, one example apparatus includes: a processor circuitry coupled to a communication interface and configurable to: determine a first timing for sampling a data signal for a first value of a condition; determine a second timing for sampling the data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing is different from the first timing; measure the condition; select the first or second timing using the measured condition; and program the communication interface to sample using the selected timing. Other examples are described.

[0006] For data sampling point tuning and tracking, one example method includes determining a first timing for sampling a data signal for a first value of a condition. The method further includes using the first timing and a predictive compensation model to determine a second timing for sampling the data signal for a second value of the condition, wherein the second timing differs from the first timing. The method also includes measuring the condition. The method further includes using the measured condition to select either the first or second timing. The method also includes programming a communication interface to sample using the selected timing. Other examples are described.

[0007] For data sampling point tuning and tracking, one example system includes: a communication interface configurable to: transmit a clock signal and a first data signal based on tuning point parameters, and sample a second data signal based on the tuning point parameters. The system also includes peripheral devices coupled to the communication interface, configurable to: receive the clock signal and the first data signal; and transmit a second data signal corresponding to the first data signal. The system further includes a processor circuitry coupled to the communication interface, configurable to: determine a first timing for sampling the second data signal for a first value of a condition, the first timing corresponding to the tuning point parameters; determine a second timing for sampling the second data signal for a second value of a condition using the first timing and a predictive compensation model, wherein the second timing is different from the first timing; measure the condition; select either the first or second timing using the measured condition; and program the communication interface to use the selected timing. Other examples are described. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device for a flash memory coupled to an external device, based on various examples described herein.

[0009] Figure 2 yes Figure 1 A block diagram of an example implementation scheme for the communication interface.

[0010] Figure 3 An example sampling window for data signals is shown.

[0011] Figure 4 It is a sequence diagram of read transactions based on various instances;

[0012] Figure 5 It is a timing diagram of data sampling in read transactions based on various instances (e.g., where strobing marks sampling points as DQS and delayed DQS).

[0013] Figure 6 The following factors caused the delay were shown. Figure 1 The data path of the device.

[0014] Figure 7 The diagram shows the selection corresponding to Figure 6 The delay of the multiplexer.

[0015] Figure 8 yes Figure 1 A block diagram of an instance implementation of the core processor 102.

[0016] Figures 9 to 10 It indicates that it can be implemented through execution. Figure 5 The flowchart of the methods, instructions and / or operations of the core processor.

[0017] Figure 11A and 11B The example polygon calculation and representation of successfully sampled points are shown.

[0018] Figure 12 An example of shift sampling is shown.

[0019] Figure 13 Examples of shifted samples that produce different polygon representations are shown.

[0020] Figure 14 Different polygon representations based on shift sampling are shown.

[0021] Figure 15 The polygon representation and sampling point adjustment based on the prediction compensation model are shown.

[0022] Figure 16 An alternative polygon representation and sampling point adjustment based on a predictive compensation model are shown.

[0023] Figure 17 Stability indicators for different polygon representations are shown.

[0024] Figure 18 This is a block diagram of an instance processing platform, which includes structured instructions for running, instantiating, and / or executing instance machine-readable instructions and / or performing... Figures 9 to 10 Instance operations to implement Figure 8 A programmable circuit system for a controller.

[0025] The same reference numerals or other reference indicators are used in the drawings to indicate the same or similar (functional and / or structural) features. The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar parts. Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, mixed, and / or irregular. Detailed Implementation

[0026] Devices (e.g., SoCs, integrated circuits, semiconductor devices, etc.) may include a communication interface such as a Serial Peripheral Interface (SPI) that electrically couples the device to peripheral devices such as flash memory devices. The communication interface may be an eight-wire SPI (OSPI), a four-wire SPI (QSPI), an Interconnect Integrated Circuit (I2C), or other communication interfaces suitable for coupling the device to peripheral devices. The timing parameters of the SPI that control programming and reading transactions with peripheral devices are called tuning point parameters (also known as sampling point parameters, tuning point, or sampling point). Tuning point parameters include the transmit clock programmable delay line (PDL) delay (TX delay), the receive clock PDL delay (RX delay), and the RD loop. The RD loop is a series of loops (e.g., dummy loops) used to delay the SPI reference clock for reading data received by the SPI from the flash memory device.

[0027] Under different die conditions (e.g., different tuning parameters, operating temperature, usage time, etc.), some ranges of the tuning point result in successful transactions between the SPI and the flash memory device, while others do not. A successful tuning point allows the SPI to reliably program data to and read data from the flash memory device. An unsuccessful tuning point causes the SPI to fail completely or to unreliably program data to and read data from the flash memory device. The range of successful and unsuccessful tuning points also changes under different die conditions. Traditionally, the SPI tuning point is programmed after the device is first coupled to the flash memory device and is not reprogrammed during subsequent operation of the device. Therefore, when device die operating temperature, usage time, humidity, ambient impedance or conductance, clock jitter, crosstalk on input lines, grounding (e.g., board and device grounding), parallel activity, input voltage, corner position of chips on the die, etc., change during operation, the originally programmed successful tuning point of the SPI may become a suboptimal (e.g., unsuccessful) tuning point. Therefore, traditional technologies require long-term service interruptions for recalibration to determine a new tuning point, which results in downtime and the consumption of energy and resources.

[0028] The examples described herein select, during configuration, the communication interface tuning point parameters for transactions with peripheral devices (e.g., flash memory devices) that will successfully program and read from the peripheral devices over a wider range of die conditions than other successful tuning point parameters. Furthermore, the examples described herein can determine different tuning point parameters corresponding to different conditions, such as environmental conditions or die conditions. Environmental conditions may correspond to temperature, humidity, ambient impedance, or conductance, etc. Die conditions may correspond to the duration of die usage, the duration of usage of one or more components on the die, the number or duration of the die or components on a die in use, clock jitter, crosstalk on input lines, grounding, parallel activity, input voltage, die structure, die location on the wafer, and / or any other physical conditions or characteristics of the die and / or components on the die. In this way, the examples described herein can dynamically adjust the tuning point parameters based on monitored conditions (e.g., environmental conditions and / or die conditions) without requiring recalibration of the tuning point parameters. The examples described herein search for a subset of candidate tuning point parameters by adjusting tuning point parameters (e.g., RX delay, TX delay, reference clock, and / or protocol configuration) and / or by shift sampling delay (e.g., RD ​​cycle) and determining whether the adjusted tuning point parameters and / or shift sampling delay result in successful data reading from a peripheral device via a communication interface.

[0029] A successful set of tuning points (e.g., RX delay, TX delay, reference clock, protocol configuration for sampling) can be represented on a graph of RX and TX delays as one or more polygons (e.g., a polygon for each shifted delay) (see example). Figure 11A , 11B(and 14 to 17). Although all points in one or more polygons for each specific reference clock and protocol configuration correspond to the RX and TX delays that result in successful data reading from the peripheral device via the communication interface, tuning points closer to the edges of the polygon are less stable. For example, as described above, conditions such as environmental conditions and / or die conditions can adjust the location where the edges of the polygons appear. Therefore, the examples described herein select sampling / tuning points from the polygons of successfully tuned points based on the location of the sampling / tuning point within the polygon (e.g., the point where the weighting center and / or its distance to any edge of the polygon is highest). After determining the initial polygons and the corresponding sampling / tuning points, the examples described herein can use a predictive compensation model to generate additional sampling / tuning points corresponding to different conditions (e.g., environmental and / or die conditions). The examples described herein determine the sampling / tuning points for the additional polygons and the corresponding stability indication values, which can be used to determine the final sampling / tuning points and / or for specific conditions during device operation. The examples described in this paper select one of multiple generated sampling / tuning points based on a stability indicator value (e.g., the selected sampling / tuning point corresponds to the sampling / tuning point with the maximum stability indicator value). Because the final sampling / tuning point is generated based on multiple factors and / or conditions, it can be more robust and last longer than conventionally selected sampling / tuning points. The above is defined for a specific operating profile. If multiple operating profiles are supported (e.g., single data rate (SDR) vs. dual data rate (DDR), flash memory frequency, access to flash memory registers vs. access to memory, etc.), different optimal sampling points can be applied to different operating profiles.

[0030] The technology disclosed herein can provide rapid adjustment of sampling points in response to changing conditions. For example, the device can store one or more pre-generated sampling points for use when conditions have changed. The selected sampling points can be more accurate, thereby increasing the likelihood of sampling the correct bits on the receive line.

[0031] Figure 1 This is a block diagram of the instance device 100 coupled to the instance flash memory 112 according to various instances. Although Figure 1 Corresponding to the connection to instance flash memory 112, but in some embodiments, flash memory 112 may be replaced by a different type of peripheral device (e.g., a different type of memory, another microcontroller, or a display controller). Device 100 includes an instance core processor 102 coupled to instance memory 104. Memory 104 is configured to store instructions that, when executed by core processor 102, cause core processor 102 to perform the various functionalities described herein.

[0032] Figure 1 The core processor 102 is further coupled to the flash memory 112 via the instance communication interface 110. Additionally, the core processor 102 may be coupled to one or more communication links via a second communication interface to facilitate communication with other devices. The device 100 may also include... Figure 1 Other circuitry and processors not shown below. As further described below, core processor 102 performs a sampling / tuning point selection protocol by transmitting instructions to communication interface 110 to adjust the parameters of communication interface 110, sending known data to flash memory 112, sampling stored data from flash memory 112, and comparing the results with the known data to determine whether the sampling was successful. Core processor 102 generates one or more polygon representations of the parameters that cause successful sampling and selects a sampling / tuning point based on one or more polygon representations, as further described below. Additional instance details of the sampling point selection can be found in commonly assigned U.S. Patent No. 11,935,613, filed July 30, 2021, entitled “Method for Tuning an External Memory Interface,” which is incorporated herein by reference in its entirety.

[0033] Figure 2 This is a block diagram of communication interface 110 and flash memory 112. Communication interface 110 is coupled to flash memory 112 via instance data line 202, instance SPI clock line 204, and instance data strobe (DQS) line 208. Data line 202 is bidirectional, allowing each of communication interface 110 and flash memory 112 to send data to each other at different stages of a transaction. For example, core processor 102 controls communication interface 110 to provide an OSPI clock to flash memory 112. The OSPI clock is generated by delaying a reference clock via TXPDL 210. Flash memory 112 uses the clock to capture commands and addresses during the command and address phases. In some instances, communication interface 110 is a half-duplex system-based interface, such as SPI, OSPI, QSPI, or XSPI. Flash memory 112 uses SPI clock line 204 to capture command and address information from data line 202 during the command and address phases of a transaction. Flash memory 112 also uses SPI clock line 204 to capture data from data line 202 during the data phase of a program transaction. Communication interface 110 uses a delayed copy of DQS line 208 to capture data from data line 202 during the data phase of a read transaction.

[0034] Communication interface 110 includes an internal reference clock 206 (e.g., a clock signal) formed by a delay of TX PDL 210 to form the SPI clock line 204. The value of the TX PDL 210 delay is referred to as the "TX delay". The core processor 102 can adjust the TX delay as part of a sampling / tuning point selection protocol. During the data phase of a read transaction, the edges of the signal pulses on DQS line 208 are aligned with the data transitions on data line 202 from flash memory 112. DQS line 208 is delayed by RX PDL 212 so that the received first-in-first-out (FIFO) shift register samples the data on data line 202 after the value has stabilized. The value of the RX PDL 212 delay is referred to as the "RX delay". The core processor 102 can adjust the RX delay as part of a sampling / tuning point selection protocol.

[0035] The round-trip delay of data can be defined as the time from the edge of reference clock 206 to the sampling time of data from flash memory 112 in communication interface 110 triggered by said edge. The round-trip delay is caused by the delay of TX PDL 210, the travel time of the clock on SPI clock line 204, the output delay of flash memory 112, and the delay of RX PDL 212. As described above, communication interface 110 samples data line 202 into RXFIFO 214 using DQS line 208 delayed by RX PDL 212. Data is read from RX FIFO 214 by communication interface 110 using reference clock 206. The read data is passed to core processor 102 to determine whether the read (also referred to as sampling) was successful.

[0036] Communication interface 110 expects to capture the first byte of data within a specific cycle (target cycle or RD cycle) of reference clock 206, and capture all remaining data in subsequent cycles of reference clock 206. In some cases, the round-trip delay is longer than the period of reference clock 206, and the target cycle is moved to a subsequent cycle of reference clock 206 to successfully read data on data line 202.

[0037] As further described below, the core processor 102 selects a preferred tuning point (for TX delay, RX delay, and RD loop values) for use with the flash memory 112 based on the sampling / tuning point detection protocol described herein. The sampling / tuning point detection protocol includes generating one or more polygon representations of successfully sampled data based on different tuning point parameters and / or conditional parameters, and selecting a sampling / tuning point from one or more polygon representations based on the stability of points within those polygon representations.

[0038] Figure 3This is a timing diagram illustrating an example of a first data signal 300 corresponding to the minimum delay tolerance and a second data signal 302 corresponding to the maximum delay tolerance. The first data signal corresponds to a first sampling window 304, and the second data signal 302 corresponds to a second sampling window 306. Communication interface 110 will successfully sample the first data signal 300 as long as data is sampled within sampling window 304. Similarly, communication interface 110 will successfully sample the second data signal 302 as long as data is sampled within sampling window 306. However, data can be shifted anywhere between the first data signal 300 and the second data signal 302. Therefore, the effective sampling window 308 corresponds to the sampling window that will cause successful sampling of the data signal, regardless of whether it corresponds to the first data signal 300, the second data signal 302, or any other data signal shifted between them. Sampling / tuning point parameters can be selected such that sampling occurs within effective sampling window 308 or one or more estimates of effective sampling window 308. However, such techniques for generating sampling / tuning point parameters based on the effective sampling window 308 are not very robust to long-term effects, resulting in significant performance degradation due to sensitivity to clock-to-data skew, narrow sampling window, limited real-time compensation / complexity in calibration logic, calibration time overhead, interference with the signal, etc.

[0039] Figure 4 Demonstrating examples based on those described in this article Figure 1 and 2The timing diagram 400 illustrates an instance of a read transaction executed by the communication interface 110. The read transaction includes an instance command phase 402, an instance address phase 404, and an instance data phase 406. In the command phase 402, the communication interface 110 may transmit a command byte on data line 202 and a reference clock 206 delayed by TX PDL 210 on SPI clock line 204. The command byte may correspond to a command to read data from a specific address, where the data stored at that address is known. In the address phase 404, the communication interface 110 transmits an address byte on data line 202 and a reference clock 206 delayed by TX PDL 210 on SPI clock line 204. The address byte may reference the address of the data to be read. One or more dummy loops are inserted after the address phase 404 to provide the flash memory 112 with the time to access the addressed memory. In the command phase 402 and address phase 404, the flash memory 112 may sample (e.g., read) the command byte and address byte from data line 202, respectively. In data phase 406, flash memory 112 can transmit data bytes on data line 202 and a DQS signal on DQS line 208. As further described above, core processor 102 can compare the sampled data with known data to determine whether the sample is successful or failed. Core processor 102 can transmit the same command multiple times for different tuning parameters to generate a polygonal representation of the successful sample, as further described above.

[0040] Figure 5 Example timing diagram 500 shows data sampling in communication interface 110 during read transactions according to various instances. Read data bytes on data line 202 and DQS signal on DQS line 208 are shown below. Figure 4 As shown in the example. Example delayed DQS signal 502 is DQS line 208 delayed by the value of RX PDL 212, as shown in example RX delay 504.

[0041] Figure 6The RX reference clock sampling options are illustrated, demonstrating the core processor 102's ability to select from three options: A) RX-ref A: no loopback; B) RX-ref B: pad loopback; and C) RX-ref C: external loopback or DQS. For each of these options, a different RD cycle can be selected. Therefore, when implementing the sampling / tuning point selection protocol, each of the three options (multiplied by the amount of RD cycles for each option) will produce a different polygonal representation. To tune and track the data sampling / tuning point, ensuring that the clock sampling edges are correctly aligned with the data bits, the core processor 102 can also select a method for generating the reference RX ref clock for tuning and tracking the data sampling / tuning point based on either internal (relative to transmitted data) or external (relative to arriving samples). Figure 6 Include Figure 1 The communication interface 110 and the flash memory 112. Figure 6 It further includes example pads 600, 602 (e.g., terminals, interfaces, etc.) that allow wires, etching, etc. to connect the communication interface 110 to the flash memory 112.

[0042] Figure 6 The diagram illustrates the non-linear delay fluctuations of the TX and RX clocks. D1 and D5 represent the internal chip pad clock delays. The delay between the internal TX clock and the TX clock returning to the chip pads due to internal chip delays may vary from chip to chip.

[0043] D3 represents the output valid clock transient. The output valid clock transient is a characteristic of the peripheral device. It is the delay between the SPI clock transition on the external peripheral clock pin and the time it takes for the peripheral device to drive valid data. D3 can be a nondeterministic delay (tmin to tmax) that can include the peripheral device's internal registers and data sectors.

[0044] D2 and D4 represent board delays, for example, where two devices are coupled to a board. The impedance of the line should correspond to the input / output impedance of the external peripheral device. Board delays D2 and D4 are caused by the length of the wire / line. Board delays D2 and D4 may exist even if the line is perfectly impedance matched to the input / output of the external peripheral device.

[0045] Figure 7 This is example circuit 700, which can be based on the above combined with... Figure 6 The three options described select the RD loop used for sampling. Figure 7 The circuit 700 includes an example multiplexer (MUX) 702. The MUX 702 has three inputs and one output. The first input of the MUX 702 corresponds to RX-ref A: no loopback, which indicates... Figure 6The internal chip pad clock delay is D1+D5. The second input of the MUX 702 corresponds to B) RX-ref B: pad loopback, which indicates Figure 6 The internal chip pad clock delay and board delay D1+D2+D4+D5 are included. The third input of the MUX 702 corresponds to RX-ref C: External Loopback or DQS, which represents all delays, internal chip pad clock delay, board delay, and output-validated clock transient delay, i.e., D1+D2+D3+D4+D5. The output of the MUX 702 is coupled to a data point sampler, which forces the MUX 702 to sample data at a selected delay. The core processor 102 can apply control signals to the selection input of the MUX 702 to control which delay amount is executed during sampling. When the sampling / tuning point is determined, each delay amount (referred to as shift sampling) produces a different polygonal representation.

[0046] Figure 8 yes Figure 1 A block diagram of an instance implementation of the core processor 102. Figure 8 The core processor 102 includes an interface circuit system 800, an instance parameter selection circuit system 802, an instance polygon representation determination circuit system 804, an instance sampling / tuning point determination circuit system 806, an instance prediction compensation model (PCM) circuit system 808, an instance comparator 810, an instance sampling / tuning point application circuit system 812, and an instance storage device 814.

[0047] Figure 8 The interface circuitry 800 activates transactions via the interface lines themselves (e.g., clock, data). Additionally, as part of a sampling / tuning point selection protocol, the interface circuitry transmits instructions to TX PDL 210 and / or RX PDL 212 to adjust tuning point parameters (e.g., TX delay, RX delay, and / or RD delay). Furthermore, the interface circuitry 800 can send instructions (e.g., via the ENB terminal of communication interface 110) to read data at a specific address. The data at the address is known data and / or previously written known data. Additionally, the interface circuitry 800 can receive samples received from flash memory 112 from RXFIFO 214 after data sampling.

[0048] Figure 8 The parameter selection circuit system 802 selects the tuning parameters used in the sampling / tuning point selection protocol. For example, the parameter selection circuit system 802 can determine the sampling RX reference clock sampling option (e.g., RD ​​loop and combination thereof) for generating the polygon based on successful sampling / tuning points for different tuning point parameters. Figure 6(The options described). Additionally, the parameter selection circuitry 802 determines the amount of TX and RX delay applied to each sample in the sampling / tuning point selection protocol when generating a polygonal representation for the selected RD cycle value.

[0049] Figure 8 The polygon representation determination circuitry 804 generates a polygon representation of a successful sample / tuning point for each tunable degree of freedom (e.g., an RD loop that may be used for each selected RX reference clock sampling option). The polygon contains points represented by the TX and RX delays of the successfully sampled data. To generate the polygon representation, the polygon representation determination circuitry 804 selects a first TX delay and a first RX delay, and instructs the communication interface 110 to access known data from flash memory 112 based on the first TX delay, the first RX delay, and the RD delay. After the communication interface 110 sends instructions to flash memory 112 and samples the data returned by flash memory 112, the interface circuitry 800 accesses the sampled data. The polygon representation determination circuitry 804 determines whether the sampled data matches the expected known data. If the polygon representation determination circuitry 804 determines that the sampled data matches the expected known data, the polygon representation determination circuitry 804 marks the tuning parameters as successful. If the polygon representation determination circuitry 804 determines that the sampled data does not match the expected known data, then the polygon representation determination circuitry 804 marks the tuning parameters as failed. The polygon representation determination circuitry 804 repeats this process for various different TX and RX delays until a polygon representation is determined for the RD cycle value. After determining the polygon representation, the polygon representation determination circuitry 804 may repeat the process for one or more different RD delay values ​​and RX reference clocks to generate one or more additional polygon representations.

[0050] Figure 8The sampling / tuning point determination circuitry 806 selects a sampling / tuning point from one or more polygon representations generated by the polygon representation determination circuitry 804. As described above, although all sampling / tuning point identifiers are combinations of TX and RX delays that result in successful sampling for a specific RD delay and RX reference clock, the stability of the sampling / tuning points is different. Therefore, the sampling / tuning point determination circuitry 806 selects a sampling / tuning point representing the desired polygon (e.g., one of the tuning points constituting the polygon representation) based on selected optimization and stability criteria (e.g., the maximum distance from the polygon representation boundary) (e.g., the tuning point with the highest distance from the polygon (containing the polygon) to its nearest boundary). Points farther from the edge are more stable than points closer to the edge under different conditions (e.g., environment or die). In some instances, the sampling / tuning point determination circuitry 806 uses the following polygon centroid formula (also referred to as centroid or centrifugal center) in Equations 1 and 2 to determine the sampling / tuning point of a given polygon.

[0051] (Equation 1)

[0052] (Equation 2)

[0053] In Equations 1 and 2 above, Cx is the TX delay of the selected sampling / tuning point, Cy is the RX delay of the selected sampling / tuning point, x represents the x-coordinate of the polygon, y represents the y-coordinate of the polygon, and A is the area of ​​the polygon. The sampling / tuning point determination circuit system 806 uses the following Equation 3 to determine the area of ​​the polygon.

[0054] (Equation 3)

[0055] In some instances, the sampling / tuning point determination circuitry 806 calculates the selected sampling / tuning points (e.g., centroids) of the polygon as a weighted sum of the centroids of the polygon's partitions into triangles. After each selected sampling / tuning point in the polygon representation, the sampling / tuning point determination circuitry 806 determines a sampling / tuning point stability point based on the distance from the selected sampling / tuning point to the nearest edge of the polygon representation (e.g., using a distance formula).

[0056] Figure 8The predictive compensation model circuit system 808 generates additional sampling / tuning points corresponding to different conditions (e.g., temperature, humidity, usage time, structure, die position on the wafer, etc.) from selected sampling / tuning points by using a predictive compensation model (PCM) to adjust the selected sampling / tuning points and corresponding stability indicators. The PCM can be a mathematical function developed based on estimates of one or more valid conditions of a polygon representation. For example, the predictive compensation model circuit system 808 can generate a PCM that infers the polygon's dependence on input condition parameters (e.g., temperature, usage time, etc.). The predictive compensation model circuit system 808 can generate the PCM by collecting information about the polygon's geometry and material properties (e.g., shape, size, boundary conditions, etc.) and characterizing how the conditions change the polygon's structure. For example, one or more conditions can adjust the polygon's structure uniformly or disproportionately. After determining the effect of one or more conditions on the polygon, the predictive compensation model circuit system 808 can model the effect using various modeling methods (e.g., finite element method, computational fluid dynamics, etc.). The predictive compensation model circuit system 808 can apply modeling methods using simulation software or a programming environment. The predictive compensation model circuit system 808 defines a mathematical model (e.g., a function or formula) describing the relationship between one or more conditions and their effects on a stability point and / or the corresponding stability indicator at that stability point. The mathematical formula can be an empirical model or a mechanistic model. An empirical model is a mathematical representation derived directly from observation or experimentation without explicitly considering the underlying physical principles. In other words, empirical models are created by analyzing data and identifying relationships between variables using statistical methods, regression analysis, or machine learning techniques. A mechanistic model is a mathematical representation of the underlying physical principles and mechanisms that describe the behavior of a controlled system. These models aim to capture the intrinsic dynamics, processes, and relationships of the system under study. The predictive compensation model circuit system 808 applies PCM to generate different sampling / tuning points and corresponding sampling / tuning point stability indicators, which correspond to different conditions or trends in condition variation. PCM calculations can be performed locally or remotely via the core processor 102 (e.g., calculated by another computing element and sent to the core processor 102 via interface 110 or other interfaces). For example, the predictive compensation model circuit system 808 can generate a first sampling / tuning point and a corresponding stability indicator for a first temperature range and / or usage duration range, a second sampling / tuning point and a corresponding stability indicator for a second temperature range and / or usage duration range, etc.

[0057] Figure 8Comparator 810 compares the stability indicators of the generated sampling / tuning points to determine which stability indicator is the largest. A larger stability indicator indicates more stable sampling / tuning point parameters (tuning point parameters). Therefore, comparator 810 determines the most stable sampling / tuning point parameters based on the generated sampling / tuning point parameters, where the largest stability indicator takes into account changing environmental conditions. Comparator 810 outputs the finally selected sampling / tuning point based on the comparison.

[0058] Figure 8 The sampling / tuning point application circuit system 812 programs the communication interface 110 to operate based on the tuning parameters of the finally selected sampling / tuning point. For example, the sampling / tuning point application circuit system 812 can program the communication interface 110 to operate based on the RD cycle, the amount of TX delay, and / or the amount of RX delay corresponding to the finally selected sampling / tuning point under a certain RX reference clock. Additionally, the sampling / tuning point application circuit system 812 monitors conditions during operation using the selected sampling / tuning point. For example, the sampling / tuning point application circuit system 812 can monitor temperature, the usage time of device 100, etc. As described above, the PCM circuit system 808 can generate different sampling / tuning points for different conditions. In this way, if the sampling / tuning point application circuit system 812 determines that the measured conditions no longer correspond to the selected sampling / tuning point, the sampling / tuning point application circuit system 812 can select another sampling / tuning point corresponding to the measured conditions, generated by the predictive compensation model circuit system 808. Therefore, the sampling / tuning point application circuit system 812 provides in-operation tuning and tracking for different conditions without requiring recalibration of the sampling / tuning point.

[0059] Figure 8 The instance storage device 814 stores generated sample / tuning points produced by the sampling / tuning point determination circuitry 806 and / or the PCM circuitry 808, which correspond to stable sample / tuning point parameters for different conditions (e.g., temperature range, usage duration range, etc.). As described above, the sample / tuning points are initially generated and stored in the storage device 814 during calibration. In this way, during the application of the sample / tuning points, the sampling / tuning point application circuitry 812 can access the sample / tuning points for in-operation tuning based on changes in conditions.

[0060] Figure 9 It means that it can be generated by Figure 1 and 8 The flowchart shows the core processor 102 executing and / or instantiating methods and / or instance operations 900. Operation 900 can be performed by... Figures 1 to 5 To perform this, any one or a combination of the circuit systems shown herein. Although combined Figure 1 and8 The core processor 102 describes Figure 9 Instructions and / or operations can be described in conjunction with any type of circuitry that implements the processing circuitry system. Figure 9 Some processes shown in this specification may be executed in a different order than those described, and many processes may be executed in parallel. Furthermore, in some instances within this specification, certain procedures may be omitted or substituted. Figure 9 The process shown in the document.

[0061] Figure 9 The machine-readable instructions and / or operations 900 begin at block 902, where the parameter selection circuitry 802 selects a sampling RX reference clock sampling option (e.g., A) RX-ref A: no loopback; B) RX-ref B: pad loopback; or C) RX-ref C). After selection, the interface circuitry 800 can apply control signals to... Figure 7 The MUX 702's select terminal allows you to apply the selected sampling RX reference clock sampling option corresponding to the RD cycle.

[0062] At box 904, polygon representation determination circuitry 804 applies various tuning / sampling parameters to a selected sampling RX reference clock sampling option to produce a polygon representation of successful sampling / tuning point parameters (e.g., a two-dimensional (2D) successful sampling schedule polygon). For example, parameter selection circuitry 802 selects a first set of tuning parameters (e.g., RX delay and TX delay), samples data from a location in flash memory 112 based on this first set of tuning parameters, and determines whether the sampled data matches known data for that location. If the sampled data matches known data, polygon representation determination circuitry 804 marks the point corresponding to the first set of tuning parameters as successful to include it in the polygon representation. If the sampled data does not match known data, polygon representation determination circuitry 804 marks the point corresponding to the first set of tuning parameters as unsuccessful to exclude it from the polygon representation. This process is repeated for multiple sets of tuning parameters until a polygon representation of successful points is produced.

[0063] At box 906, the sampling / tuning point determination circuitry 806 determines the sampling / tuning point and the corresponding stability indicator for the polygon representation. For example, the sampling / tuning point determination circuitry 806 can use equations 1 to 3 above to determine the sampling / tuning point and determine the corresponding stability indicator based on the distance between the sampling / tuning point and the nearest point on the edge of the polygon representation. At box 908, the PCM circuitry 808 uses a predictive compensation model to generate different sampling / tuning points and corresponding stability indicators. (As described above...) Figure 8As described, PCM models the effect of one or more conditions on a stability point and its corresponding stability indicator. Therefore, the PCM circuit system 808 applies PCM to selected stability points and their corresponding stability indicators to generate different stability points and corresponding stability indicators for different conditions.

[0064] At block 910, parameter selection circuitry 802 determines whether another polygon can be generated based on whether all RD cycles and RX reference clock sampling options have already been used to generate a polygon. If there is another RD cycle / RX reference clock sampling option that has not yet been used to generate a polygon, the process is repeated for the remaining RD cycle / RX reference clock sampling options. Therefore, if parameter selection circuitry 802 determines that the generated polygon representation is not the last polygon representation to be generated (block 910: No), control returns to block 902 to repeat the process for subsequent RD cycle / RX reference clock sampling options.

[0065] If parameter selection circuitry 802 determines that the generated polygon representation is the last polygon representation to be generated (box 910: Yes), comparator 810 selects the final stability point parameters (e.g., TX delay, RX delay, and RD cycle) based on a stability indicator for the generated / selected sampling / tuning points of the generated polygon and / or based on different conditions (box 912). For example, the process in steps 902 to 912 may generate three polygon representations, each with a corresponding sampling / tuning point and multiple PCM-adjusted sampling / tuning points. Each sampling / tuning point corresponds to a stability indicator. Comparator 810 determines the maximum stability indicator and selects the final sampling / tuning point parameters corresponding to the maximum stability indicator (e.g., the RX delay, TX delay, and RD cycle that generate the maximum stability indicator). In some instances, the maximum stability indicator may be replaced by different stability optimization criteria.

[0066] At block 914, the sampling / tuning point application circuitry system 812 programs the communication interface 110 based on the final sampling / tuning point parameters. For example, the sampling / tuning point application circuitry system 812 (e.g., via interface circuitry system 800) outputs instructions to the communication interface 110 to operate based on the finally selected RX delay, TX delay, RD cycle, and RX reference clock. Interface circuitry system 800 can output a first control signal to TX PDL 210 to set the TX delay, a second control signal to RX PDL 212 to set the RX delay, a third control signal to the select terminal of MUX 702 to set the RX reference clock, and a fourth control signal to set the RD cycle. At block 916, normal operation is performed based on the selected sampling / tuning point parameters, as described below. Figure 10 Further description. If the core processor 102 (e.g., via interface circuitry 800) receives an instruction to recalibrate the sampling / tuning point parameters, control returns to block 902.

[0067] Figure 10 It means that it can be generated by Figure 1 and 8 The core processor 102 executes and / or instantiates methods and / or instance operations 916 to facilitate normal operation. Operation 916 can be... Figures 1 to 5 To perform this, any one or a combination of the circuit systems shown herein. Although combined Figure 1 and 8 The core processor 102 describes Figure 10 Instructions and / or operations can be described in conjunction with any type of circuitry that implements the processing circuitry system. Figure 10 Some processes shown in this specification may be executed in a different order than those described, and many processes may be executed in parallel. Furthermore, in some instances within this specification, certain procedures may be omitted or substituted. Figure 10 The process shown in the document.

[0068] Figure 10 Machine-readable instructions and / or operations 916 begin at block 1002, where the sampling / tuning point application circuitry system 812 monitors conditions. For example, the sampling / tuning point application circuitry system 812 may include or interface with one or more sensors, clocks, etc., to access information related to one or more conditions (e.g., temperature or humidity data from sensors, usage duration data from clocks, timers, or counters, accessible corner locations from the die, etc.). At block 1004, the sampling / tuning point application circuitry system 812 determines whether the monitored conditions correspond to or exceed a specific sampling / tuning point stored in storage device 814. As described above, the predictive compensation model circuitry system 808 may generate multiple different sampling / tuning points corresponding to different conditions (e.g., temperature ranges and / or operating time / usage duration ranges, etc.) for the generated polygonal representation. Such sampling / tuning points and their corresponding conditions are stored in storage device 814. Therefore, the sampling / tuning point application circuit system 812 can access the conditions used for the stored sampling / tuning point parameters and determine whether any sampling / tuning points match or exceed the current conditions.

[0069] If the sampling / tuning point application circuitry system 812 determines that the condition does not correspond to another sampling / tuning point stored in the storage device 814 (box 1004: No), control returns to box 1002. If the sampling / tuning point application circuitry system 812 determines that the condition corresponds to another sampling / tuning point stored in the storage device 814 (box 1004: Yes), then the sampling / tuning point application circuitry system 812 selects and applies (e.g., programs the communication interface 110) the sampling / tuning point parameters corresponding to the current condition (box 1006). If multiple sampling / tuning points exist corresponding to the current condition, the sampling / tuning point application circuitry system 812 can select the sampling / tuning point parameters corresponding to the desired (e.g., optimal) stability indicator. Therefore, Figure 10 The flowchart provides the in-run sampling / tuning point parameter tuning and tracking without requiring recalibration. After block 1006, control returns to block 1002 to continue monitoring / tracking conditions.

[0070] Figure 11A An example polygon representation 1100 is shown generated by the core processor 102 using a fast polygon generation technique for a specific protocol and reference clock configuration, based on polygon-based boundary detection, without needing to traverse all combinations of TX and RX delays. For example, the core processor 102 may first apply the minimum RX and TX delays to a specific RD cycle and sample known data based on the RX delay, TX delay, and RD cycle. If the sampled data matches the known data, the core processor 102 marks the sampling / tuning point (e.g., "A") as successful. If the sampled data does not match the known data, the core processor 102 may adjust one or more of the TX or RX delays and repeat until the first "corner" of the polygon representation is found as a successful sampling / tuning point.

[0071] After determining the first successful sampling / tuning point (“A”), the core processor 102 increases the RX delay and maintains the TX delay, and continues to compare the known data with the sampled data until the highest successful RX delay is determined (e.g., corresponding to sample “B”). Furthermore, after determining the first successful sampling / tuning point (“A”), the core processor 102 increases the TX delay and maintains the RX delay, and continues to compare the known data with the sampled data until the highest successful TX delay is determined (e.g., corresponding to sample “C”). After determining points A, B, and C, the core processor 102 may first apply the maximum RX and TX delays to a specific RD cycle and sample data known based on the RX delay, TX delay, RX reference clock, and RD cycle. If the sampled data matches the known data, the core processor 102 marks the sampling / tuning point (e.g., “D”) as successful. If the sampled data does not match the known data, the core processor 102 may adjust one or more of the TX or RX delays and repeat until the first “corner” of the polygon representation is found as a successful sampling / tuning point. After determining the largest successful sampling / tuning point (“C”), the core processor 102 reduces the RX latency while maintaining the TX latency, and continues to compare the known data with the sampled data until the highest successful RX latency is determined (e.g., corresponding to sample “F”). Furthermore, after determining the largest successful sampling / tuning point (“D”), the core processor 102 reduces the TX latency while maintaining the RX latency, and continues to compare the known data with the sampled data until the highest successful TX latency is determined (e.g., corresponding to sample “E”). The core processor 102 can then generate a polygon representation based on the determined points A, B, C, D, E, and F.

[0072] Figure 11B An example polygon representation 1102 generated by core processor 102 using a robust polygon generation technique (e.g., a strictly brute-force polygon generation technique) is illustrated. For example, core processor 102 may first apply minimum RX and TX delays to a specific RD cycle and sample data known based on the RX delay, TX delay, RX reference clock, and RD cycle. If the sampled data matches the known data, core processor 102 marks the sampling / tuning point (e.g., "A") as successful. If the sampled data does not match the known data, core processor 102 may adjust one or more of the TX or RX delays and repeat until a first "corner" of the polygon representation is found for successful sampling / tuning.

[0073] After determining the first successful sampling / tuning point (“A”), the core processor 102 increases the RX delay and maintains the TX delay, and continues to compare the known data with the sampled data until the highest successful RX delay is determined (e.g., corresponding to sample “B”). After determining the second successful corner sampling / tuning point (“B”), the core processor 102 increases the RX delay and / or increases the TX delay, and continues to compare the known data with the sampled data until the highest successful RX delay is generated along edge “1b”, until a successful corner (“C”) is identified, corresponding to the maximum RX delay. After determining the third successful corner sampling / tuning point (“C”), the core processor 102 increases the TX delay and continues to compare the known data with the sampled data until the maximum RX and TX delay sampling / tuning point (“D”) that generates a successful sample is determined. After determining the maximum successful sampling / tuning point (“C”), the core processor 102 decreases the RX delay and maintains the TX delay, and continues to compare the known data with the sampled data until the highest successful RX delay is determined (e.g., corresponding to sample “E”). After determining the fifth successful corner sampling / tuning point (“E”), the core processor 102 reduces the RX latency and / or reduces the TX latency, and continues to compare the known data with the sampled data until the highest successful RX latency is generated along edge “1e”, until the successful corner (“F”) is identified. After determining the sixth successful corner sampling / tuning point “F”, the core processor 102 continues testing while reducing the TX latency to verify edge 1f. The core processor 102 determines the polygon representation based on edges A, B, C, D, E, F and edges 1a, 1b, 1c, 1d, 1e, 1f. Although Figure 11A and 11B A polygon corresponds to a specific shape, but the size, shape, dimensions, etc., of the polygon can vary. Furthermore, although... Figure 11A and 11B Two techniques for testing sampling / tuning points to produce polygon representations are shown, but for a specific protocol and reference clock configuration, there are other ways to select sampling / tuning points to produce polygon representations with successful sampling / tuning point parameters. Figure 11A and 11B The polygons correspond to different delays (e.g., RX and TX delays) that produce successful sampling of data.

[0074] Figure 12 Example samples 1200 with different delay shifts (represented by 4-bit shifts in the QSPI protocol configuration) are shown. The first example sample 1202 corresponds to a sample with zero delay (e.g., sampled after a dummy signal). In some instances, the first sample 1202 corresponds to... Figure 3 and 4RX-ref B: The RD cycle associated with the pad loopback. The second instance sample 1204 corresponds to a sample with a positive shift delay of one (e.g., a sample spaced one sampling period before sample 1202). In some instances, the second sample 1204 corresponds to... Figure 3 and 4 RX-ref A: RD cycle without loopback correlation. The third instance sample 1206 corresponds to a sample with a negative shift delay of one (e.g., a sample spaced one cycle after the first sample 1202). In some instances, the third sample 1206 corresponds to... Figure 3 and 4 RX-ref C: External loop or DQS-related RD loop. See below for details. Figure 13 and Figure 14 Further description.

[0075] Figure 13 An example data signal 1302 is shown, which includes a dummy signal (corresponding to W7), first read data (corresponding to W8), and second read data (corresponding to W9). Figure 13 The data signal 1302 includes a first sample 1304, a second sample 1306, and a third sample 1309. The first sample 1304 (e.g., corresponding to the first RD cycle) corresponds to... Figure 12 The second sample 1204, the second sample 1306 (e.g., corresponding to the second RD cycle) corresponds to Figure 12 The first sample 1202, and the third sample 1308 (e.g., corresponding to the third RD cycle) correspond to Figure 12 The third sample is 1206. As described above, each sample corresponds to a different polygon representation, as detailed below. Figure 14 Further description. In some instances, additional shift delay can be used to determine additional or alternative polygon representations.

[0076] Figure 14 It shows the corresponding Figure 13 Different shift-delayed instance polygon representations 1404, 1402, and 1406 are associated with instance visual representation 1400. For example, polygon representation 1402 corresponds to the generation of... Figure 13 The third sample 1306 is a successful sample of the RX and TX delay combination (e.g., corresponding to a no-shift delay or RX-ref B: pad loopback RD loop). Polygon representation 1404 corresponds to generating... Figure 13 The first sample 1304 is a successful sample of the RX and TX delay combination (e.g., corresponding to a positive shift delay of one or RX-ref A: a loop-free RD cycle). Polygon representation 1406 corresponds to generating... Figure 13 The third sample 1308 is a successful sample of the RX delay and TX delay combination (e.g., corresponding to a negative shift delay of one or RX-ref C: outer loopback or RD loop of DQS).

[0077] Figure 15 Three example polygons, 1500, 1502, and 1504, for specific protocol and reference clock configurations are illustrated, along with the effects of applying PCM to the polygons. In the first polygon representation 1500, the core processor 102 determines the sampling / tuning point as “m”, which corresponds to the amount of TX and RX delays in the RD cycle corresponding to polygon representation 1500. Additionally, a PCM has been generated for the RD cycle, representing the effect of one or more conditions on the sampling / tuning point. The PCM may be taken into account and / or tuned to a specific protocol and reference clock configuration. For example, for one or more specific conditions, the PCM causes polygon representation 1500 to shrink towards the origin of the graph at a linear rate of 0.1 (e.g., reducing RX and TX delays). The shrinkage is due to a poor-case PCM implementation that produces a minimum polygon representation. However, other PCMs may produce different results, such as expansion, shifting, etc. In the second polygon representation 1502, the core processor 102 determines the sampling / tuning point as “n”, which corresponds to the amount of TX and RX delays in the RD cycle corresponding to polygon representation 1502. Additionally, a PCM has been generated for the RD cycle, representing the effect of one or more conditions on the sampling / tuning point. For example, for a specific one or more conditions, the PCM causes polygon representation 1500 to shrink upwards at a linear rate of 0.5 (e.g., increasing the RX delay). In the third polygon representation 1504, the core processor 102 determines the sampling / tuning point as "p," which corresponds to the amount of TX and RX delay in the RD cycle corresponding to polygon representation 1504. Additionally, a PCM has been generated for the RD cycle, representing the effect of one or more conditions on the sampling / tuning point. For example, for a specific one or more conditions, the PCM causes polygon representation 1500 to shrink upwards and to the right at a linear rate of 0.1 (e.g., increasing the RX and TX delay). Figure 15 Each polygon representation of the PCM 1500, 1502, 1504 corresponds to a quantity and direction (e.g., a representation based on linear vectors). However, the PCM can correspond to different (e.g., nonlinear models) that allow the polygon representation to be adjusted based on the effect of changing conditions on the sampling / tuning point and / or the polygon representation.

[0078] Figure 16 Alternative examples of polygon representation 1600 are shown, along with the effects of applying PCM to polygon representation 1600, demonstrating that PCM can generate a range of possible tuning points in a non-linear manner. Figure 16In one example, core processor 102 generates a first polygonal representation for the RD loop, where the selected sampling / tuning point is "0". The first polygonal representation corresponds to a first initial condition (e.g., a first temperature range below a second temperature range, a first usage duration range, etc.). When core processor 102 applies a PCM corresponding to a second environmental condition (e.g., a second temperature range, a second usage duration range longer than the first usage duration range, etc.), core processor 102 uses the PCM to adjust the selected sampling / tuning point from "0" to "1". When core processor 102 applies a PCM corresponding to a third condition (e.g., a third temperature range above the second temperature range, a third usage duration range longer than the second usage duration range, etc.), core processor 102 uses the PCM to adjust the selected sampling / tuning point from "1" to "2". For example... Figure 16 As shown, the polygon representation and sampling / tuning points change non-linearly from "0" to "1" to "2".

[0079] Figure 17 The generated instance polygon representations 1700, 1702, and 1704 for different RD cycles are shown, along with corresponding stability indicators for selected sampling / tuning points for each polygon representation. The first polygon representation 1700 corresponds to the first RD cycle and has a stability indicator X1, which is the nearest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1700. The second polygon representation 1702 corresponds to the second RD cycle and has a stability indicator X2, which is the nearest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1702. The third polygon representation 1704 corresponds to the third RD cycle and has a stability indicator X3, which is the nearest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1704. Figure 17 In this example, core processor 102 selects one of the sampling / tuning points of polygon representations 1700, 1702, and 1704 based on a stability indicator. For instance, core processor 102 determines that the stability indicator of the sampling / tuning point of the third polygon 1704 is greater than the stability indicators of the sampling / tuning points of the first polygon 1700 and the second polygon 1702 (assuming the optimization criteria are continuously increasing). Therefore, core processor 102 selects the sampling / tuning point of the third polygon representation 1704 because the corresponding stability indicator is the largest among the three polygon representations.

[0080] Figure 18 This is a block diagram of an instance programmable circuit system platform 1800, which is structured to execute and / or instantiate instance machine-readable instructions and / or... Figures 9 to 10 Instance operations to implement Figure 8The core processor 102. The programmable circuit system platform 1800 can be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., cellular phone, smartphone, such as iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, game consoles, head-mounted devices (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices or Internet of Things (IoT) devices, or any other type of computing and / or electronic device.

[0081] The programmable circuit system platform 1800 illustrated in this example includes a programmable circuit system 1812. The programmable circuit system 1812 illustrated in this example is hardware. For example, the programmable circuit system 1812 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, VPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 1812 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1812 implements parameter selection circuitry 802, polygon representation determination circuitry 804, sampling / tuning point determination circuitry 806, prediction compensation model 808, comparator 810, and sampling / tuning point application circuitry 812.

[0082] The programmable circuit system 1812 of the illustrated example includes local memory 1813 (e.g., cache memory, registers, etc.). The programmable circuit system 1812 of the illustrated example communicates with main memories 1814 and 1816 via bus 1818, the main memories including volatile memory 1814 and non-volatile memory 1816. Volatile memory 1814 may be implemented using synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. Non-volatile memory 1816 may be implemented using flash memory and / or any other desired type of memory device. Access to the main memories 1814 and 1816 of the illustrated example is controlled by memory controller 1817. In some instances, the memory controller 1817 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system to manage data flows to and from main memories 1814 and 1816. In some instances, one of local memory 1813, volatile memory 1814, or non-volatile memory 1816 may be implemented. Figure 8 Storage device 814.

[0083] The programmable circuit system platform 1800 shown in the example also includes an interface circuit system 1820. The interface circuit system 1820 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Serial Peripheral Interface (SPI) and / or a Peripheral Component Interconnect High Speed ​​(PCIe) interface. In some instances, the interface circuit system 1820 is implemented... Figure 8 The interface circuit 800.

[0084] In the illustrated example, one or more input devices 1822 are connected to the interface circuit system 1820. The input devices 1822 allow users (e.g., human users, machine users, etc.) to input data and / or commands into the programmable circuit system 1812. The input devices 1822 may be implemented using, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, and / or voice recognition systems.

[0085] One or more output devices 1824 are also connected to the interface circuitry system 1820 of the illustrated example. The output devices 1824 may be implemented, for example, by display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-situ switching (IPS) displays, touchscreens, etc.), haptic output devices, and / or speakers. Therefore, the interface circuitry system 1820 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry system such as a GPU.

[0086] The interface circuit system 1820 shown in the example also includes communication devices such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface to facilitate the exchange of data with external machines (e.g., any type of computing device) via network 1826. Communication can be carried out via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond-line-of-sight wireless systems, line-of-sight wireless systems, cellular telephone systems, optical connections, etc.

[0087] The programmable circuit system platform 1800 illustrated in the example also includes one or more mass storage disks or devices 1828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0088] It can be by Figures 9 to 10 The machine-readable instructions 1832 implemented by the machine-readable instructions may be stored in a mass storage device 1828, a volatile memory 1814, a non-volatile memory 1816 and / or on at least one non-transitory computer-readable storage medium, such as a removable CD or DVD.

[0089] Figures 2 to 5 The implementation is shown in the figure. Figure 1 The device 100, core processor 102, and / or communication interface 110 are examples of such devices. However, Figures 1 to 2 One or more of the elements, processes and / or devices shown may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other way.

[0090] also, Figure 8 The interface circuit system 800, parameter selection circuit system 802, polygon representation determination circuit system 804, sampling / tuning point determination circuit system 806, PCM circuit system 808, comparator 810, sampling / tuning point application circuit system 812, and / or storage device 814 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Therefore, for example, Figure 8 The interface circuit system 800, parameter selection circuit system 802, polygon representation determination circuit system 804, sampling / tuning point determination circuit system 806, PCM circuit system 808, comparator 810, sampling / tuning point application circuit system 812, and / or storage device 814 may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs).

[0091] When reading any of the device or system technical solutions in this patent to cover pure software and / or firmware implementations... Figure 8 At least one of the following—interface circuit system 800, parameter selection circuit system 802, polygon representation determination circuit system 804, sampling / tuning point determination circuit system 806, PCM circuit system 808, comparator 810, sampling / tuning point application circuit system 812, and / or storage device 814—is hereby explicitly defined as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, digital versatile optical disc (DVD), optical disc (CD), Blu-ray disc, etc., comprising software and / or firmware. Furthermore, Figure 8The interface circuit system 800, parameter selection circuit system 802, polygon representation determination circuit system 804, sampling / tuning point determination circuit system 806, PCM circuit system 808, comparator 810, sampling / tuning point application circuit system 812, and / or storage device 814, in addition to Figure 8 Other than or in place of the elements, processes and / or devices shown. Figure 8 The elements, processes, and / or devices shown may also comprise one or more elements, processes, and / or devices, and / or may comprise more than one of any or all of the elements, processes, and devices shown. As used herein, the phrase “communication” includes variations thereof covering direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-off events.

[0092] Figures 9 to 10 The text shows the representation used for implementation. Figure 1 and 8 The core processor 102 includes an instance of hardware logic, machine-readable instructions, a hardware-implemented state machine, and / or any combination thereof. Machine-readable instructions may be one or more executable programs or portions of executable programs for execution by a computer processor. The program may be implemented in software, stored on a non-transitory computer-readable storage medium such as a CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or processor-associated memory, but the entire program and / or portions thereof may alternatively be executed by a device outside the processor, and / or implemented in firmware or dedicated hardware.

[0093] Furthermore, despite reference Figures 9 to 10 The flowchart shown describes an example program, but many other methods of implementing the core processor 102 can be used alternatively. For example, the execution order of the blocks can be changed, and / or some of the described blocks can be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware.

[0094] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and packaged format. As described herein, machine-readable instructions can be stored as data (e.g., portions of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, depackaged, allocated, reallocated, compiled, etc., so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, wherein these portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0095] In another instance, machine-readable instructions may be stored in a state in which they are readable by a computer, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or other device. In another instance, machine-readable instructions (e.g., stored settings, data input, recorded network addresses, etc.) may be configured before they can be executed wholly or partially. Therefore, the described machine-readable instructions and / or corresponding programs encompass such machine-readable instructions and / or programs regardless of their specific format or state when stored or otherwise at rest or in transit.

[0096] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, any of the following languages ​​can be used to represent machine-readable instructions: assembly language, C, C++, Java, C-sharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0097] As mentioned above, Figure 6The instance process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on a non-transitory computer and / or machine-readable medium, such as a hard disk drive, flash memory, read-only memory, optical disk, digital universal optical disk, cache memory, random access memory, and / or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, short time period, temporary buffering of information, and / or cache). As used herein, the term non-transitory computer-readable medium is explicitly defined as including any type of computer-readable storage device and / or disk, excluding propagation signals and transmission media.

[0098] While certain example methods, apparatuses, and articles have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles that fall within the scope of the claims of this patent.

[0099] When identifying multiple elements or components that can be individually mentioned, descriptive terms such as "first," "second," "third," etc., are used herein. Unless otherwise specified or understood from the context of their use, such descriptive terms do not imply any priority, physical order, or arrangement or chronological order in a list, but are merely labels to refer to multiple elements or components separately to facilitate understanding of the described instance. In some instances, the descriptive term "first" may be used to refer to an element in a detailed description, while the same element may be referred to in the technical solution by different descriptive terms such as "second" or "third." In such cases, these descriptive terms are used solely for ease of reference to multiple elements or components.

[0100] In this specification and claims, unless otherwise stated, the terms "comprising" and "having," and their variations, are included in a manner similar to the term "including." Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. In another instance, "about," "approximately," or "substantially" preceding a value means + / - 5% of the stated value. In yet another instance, "about," "approximately," or "substantially" preceding a value means + / - 1% of the stated value.

[0101] As used herein, the terms “coupled,” “couples,” and variations thereof may cover connections, communication, or signaling paths that ensure functional relationships are consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: in a first instance, device A is coupled to device B; or in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C substantially does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A. Furthermore, the terms “coupled,” “couples,” and variations thereof include indirect or direct electrical or mechanical connections.

[0102] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device or a combination thereof.

[0103] Although not in Figures 1 to 4 All are individually labeled, but the components or elements of the systems and circuits shown herein have one or more conductors or ends that allow signals to enter or exit the component or element. Conductors or ends (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0104] As used herein, a “terminal” of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component is typically a conductor, such as a wire, trace, pin, pad, or other connector or interconnect that enables the component, device, system, etc., to be electrically and / or mechanically connected to another component, device, system, etc. Terminals can be used, for example, to receive or provide analog or digital electrical signals (or simply, signals) or to be electrically connected to a common or ground reference. Thus, an input terminal or input is used to receive signals from another component, device, system, etc. An output terminal or output is used to provide signals to another component, device, system, etc. Other terminals can be used to connect to a common, ground, or voltage reference, such as a reference terminal or ground terminal. Terminals on an IC or PCB may also be referred to as pins (vertical conductors) or pads (planar conductors). A node is a connection point or interconnect of two or more terminals. A number of terminals and nodes can be shown. However, depending on the specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, the terms “terminal,” “node,” “interconnect,” “pad,” and “pin” are used interchangeably.

[0105] The terms “or” and “and / or”, for example, when used in the form of, for example, A, B or C or A, B and / or C, refer to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C.

[0106] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An apparatus comprising: A communication interface that can be configured to receive data signals; as well as The processor circuitry, coupled to the communication interface, is configurable to: Determine a first timing for sampling the data signal in response to a first value of a condition; The first timing and the predictive compensation model are used to determine a second timing for sampling the data signal for a second value of the condition, wherein the second timing is different from the first timing; Measure the conditions; The first timing or the second timing is selected using measured conditions; as well as The communication interface is programmed to sample using a selected timing.

2. The apparatus according to claim 1, The condition mentioned above is temperature. The first value of the temperature is a temperature different from the second value of the temperature, and The first timing has a delay that is different from that of the second timing.

3. The apparatus of claim 1, wherein the prediction compensation model includes different delays for different temperatures.

4. The apparatus of claim 1, wherein the communication interface comprises a half-duplex serial peripheral interface.

5. The apparatus of claim 1, wherein the processing circuitry is configured to: A third timing is determined using either the first timing or the second timing for sampling the data signal against a third value of the condition, wherein the third timing is different from both the first timing and the second timing; and The first timing, the second timing, or the third timing is selected using measured conditions.

6. The apparatus of claim 1, wherein the predictive compensation model uses a mathematical function to adjust the first timing, the mathematical function being based on an estimate of the impact of the conditions on the success of the first timing.

7. The apparatus of claim 1, wherein the processor circuitry is configured to determine the first timing by generating a polygonal representation based on successful sampling of data for different tuning point parameters, the first timing corresponding to a point in the polygonal representation.

8. The apparatus of claim 7, wherein the processor circuitry is configured to generate the polygon representation by: Based on the different tuning point parameters, instructions for writing the first data to the peripheral device are transmitted. Second data is sampled from the peripheral device based on the different tuning point parameters; as well as Based on the first data, the second data is matched to determine that a portion of the sampling was successful; as well as The polygon representation is generated using portions of the different tuning point parameters corresponding to the portion of the sample.

9. The apparatus of claim 1, wherein the condition is at least one of environmental conditions or die conditions, the environmental conditions corresponding to one or more of temperature or humidity, and the die conditions corresponding to the usage duration of the communication interface, the structure of the communication interface, or the location of the communication interface when implemented in a wafer.

10. A method comprising: Determine the first timing for sampling the data signal in response to the first value of the condition; The first timing and the predictive compensation model are used to determine a second timing for sampling the data signal for a second value of the condition, wherein the second timing is different from the first timing; Measure the conditions; The first timing or the second timing is selected using measured conditions; as well as Program the communication interface to use a selected timing for sampling.

11. The method according to claim 10, The condition mentioned above is temperature. The first value of the temperature is a temperature different from the second value of the temperature, and The first timing has a delay that is different from that of the second timing.

12. The method of claim 10, wherein the prediction compensation model includes different delays for different temperatures.

13. The method of claim 10, wherein the communication interface comprises a serial peripheral interface.

14. The method of claim 10, further comprising: A third timing is determined using either the first timing or the second timing for sampling the data signal against a third value of the condition, wherein the third timing is different from both the first timing and the second timing; and The first timing, the second timing, or the third timing is selected using measured conditions.

15. The method of claim 10, wherein the predictive compensation model uses a mathematical function to adjust the first timing, the mathematical function being based on an estimate of the impact of the conditions on the success of the first timing.

16. The method of claim 10, further comprising determining the first timing by generating a polygonal representation based on successful sampling of data for different tuning point parameters, the first timing corresponding to a point in the polygonal representation.

17. The method of claim 16, wherein generating the polygon representation comprises: Based on the different tuning point parameters, instructions for writing the first data to the peripheral device are transmitted. Second data is sampled from the peripheral device based on the different tuning point parameters; as well as Based on the first data, the second data is matched to determine that a portion of the sampling was successful; as well as The polygon representation is generated using portions of the different tuning point parameters corresponding to the portion of the sample.

18. A system comprising: The communication interface can be configured as follows: The clock signal and the first data signal are transmitted based on the tuning point parameters; as well as The second data signal is sampled based on the tuning point parameters; as well as Peripheral devices coupled to the communication interface, the peripheral devices being configurable to: Receive the clock signal and the first data signal; as well as Transmit the second data signal, the second data signal corresponding to the first data signal; and A processor circuitry coupled to the communication interface, the processor circuitry being configurable to: A first timing is determined for sampling the second data signal for a first value of a condition, the first timing corresponding to the tuning point parameter; The first timing and the predictive compensation model are used to determine a second timing for sampling the second data signal for a second value of the condition, wherein the second timing is different from the first timing; Measure the conditions; The first timing or the second timing is selected using measured conditions; as well as Program the communication interface to use the selected timing.

19. The system according to claim 18, The condition mentioned above is temperature; The first value of the temperature is a temperature different from the second value of the temperature, and The first timing has a delay that is different from that of the second timing.

20. The system of claim 18, wherein the prediction compensation model includes different delays for different temperatures.

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