A semi-parallel 5G NR Polar coding method, apparatus and storage medium

Abstract

The application discloses a kind of semi-parallel 5G NR Polar encoding method, device and storage medium, mainly solve the problem of lower throughput of existing encoder.Its implementation scheme includes: the N long serial data of input encoder is converted into parallel, each serial data is converted into a sub-block;Each sub-block is encoded once based on the generator matrix using the pipelining processing mode, and 32 bits of the sub-code are stored in the memory BRAM;Sub-codes are read out from BRAM, and these sub-codes are encoded twice based on the generator matrix using the reverse order encoding mode, and 32 bits of the codeword are obtained.The application can improve the throughput of the encoder under the premise of consuming less resources, meet the requirements of high transmission rate in 5G communication, and can be used for error control of satellite communication.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication, and further relates to a semi-parallel 5G NR Polar coding method, device and storage medium, which can be used for error control in satellite communication. Background Technology

[0002] As people's demands for internet access continue to increase, 5G technology is also constantly innovating and developing. 5G represents another revolutionary breakthrough in the history of communication technology, achieving significant advancements over 4G. Its peak speed can reach up to 10Gbps, hundreds of times faster than 4G networks. The three main scenarios defined by 5G technology include: enhanced mobile broadband (eMBB), massive machine-type communications (mMTC), and ultra-reliable low-latency communications (URLLC). 5G aims to improve user experience, achieve zero-latency transmission, and enable the Internet of Things. Because 5G systems have higher requirements for transmission rates, throughput, and reliability, a series of key technologies within the system require in-depth research. Channel coding technology, as a guarantee of communication quality, is a crucial component of 5G systems. Channel coding is a technique that reduces the bit error rate and improves communication quality by detecting and correcting errors in the transmitted signals through the communication channel.

[0003] Polar codes are the first theoretically proven coding scheme to achieve the Shannon limit in binary input discrete memoryless channels and possesses excellent construction properties. They have become the control channel coding scheme for eMBB scenarios in the 5G standard. 5G Polar codes explicitly specify the use of polarization weighting to construct Polar sequences, a method beneficial for hardware implementation. However, due to the relatively recent development of Polar codes, while significant progress has been made in construction methods and coding architectures, less attention has been paid to the hardware implementation of Polar coding links in the 5G standard. Many problems remain to be solved in this area, such as the low overall system throughput. Therefore, studying the structural characteristics of Polar codes under the 5G standard and improving encoder throughput while maintaining low resource consumption in the 5G Polar encoder implementation is of great significance.

[0004] Polar codes, as a type of error-correcting code with a defined generator matrix structure, are implemented by multiplying the Polar sequence with the generator matrix. They are mainly categorized into four structures: fully parallel coding, semi-parallel coding, serial coding, and pipelined coding. The fully parallel coding structure is relatively simple in principle, requiring only one clock cycle to complete encoding, but it consumes excessive resources and its operating frequency is difficult to increase. The semi-parallel coding structure has resource consumption and encoding time between the fully parallel and pipelined structures, offering a balance between area utilization and throughput. The serial coding structure can operate at very high clock frequencies, but its latency is high, making it unsuitable for encoding longer codewords. The pipelined coding structure consumes the fewest resources, but its latency is relatively high, and the data needs to be input in two parallel streams, requiring additional buffering time.

[0005] In their paper "Research on 5G Polar Code Encoding and Decoding Technology and FPGA Implementation," Shen Zhenyu et al. disclosed a 5G Polar encoder and its implementation method. The encoder employs a nested encoding approach, dividing the encoding process into two steps: first, the N-length construction sequence is divided into 32-bit sub-blocks, and a generator matrix is ​​applied to each sub-block. Perform sub-block encoding; then, based on the generator matrix... and generating matrix The relationship is used for a second iteration of encoding to obtain the final N-length Polar codeword. This scheme, along with the generator matrix... While the fully parallel encoding method reduces resource consumption, it still has two shortcomings: first, the long critical path results in a low clock frequency; second, the serial output of the encoded results leads to excessive output data delay, resulting in low encoder throughput.

[0006] Patent document CN 2021220427823.2 discloses "a multi-core polar code encoder supporting multiple code lengths and multiple code rates in a common mode," which includes a multi-core pipelined processing structure and an encoding core. For the encoding process of N-length codewords, one or more input code lengths are first set to the minimum value. The butterfly encoding process is performed, and then subsequent butterfly operations are performed based on the code length N. This multi-core pipelined processing method will cause the encoder to consume a lot of resources. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, this invention proposes a semi-parallel 5G NR Polar coding method, apparatus, and storage medium to improve encoder throughput with less resource consumption.

[0008] The technical approach to achieve the objective of this invention is as follows: by analyzing the characteristics of the Polar encoding structure and combining it with the BRAM data reading rules, a reverse encoding method is adopted to obtain the final encoding result at the next moment after reading the stored data, thereby reducing the encoding waiting time; by pre-grouping the data input to the encoder to adapt to the parallel processing of the output encoding result by the group interleaver; and by inserting register pipelined processing to solve the problem of long critical paths, improve the operating clock frequency, and thus improve the encoder throughput.

[0009] Based on the above ideas, the technical solution of the present invention includes the following:

[0010] 1. A semi-parallel 5G NR Polar coding method, characterized in that it includes:

[0011] (1) Perform serial-to-parallel conversion on the N-length serial data input from the encoder, converting each... Each serial data item is converted into a sub-block, where 32 represents the length of the mother code, and 32 represents the number of conversion sub-blocks;

[0012] (2) For each sub-block based on The generator matrix is ​​encoded once using a pipelined processing method, resulting in 32 bits with a width of [missing information]. The subcode is stored in the BRAM memory;

[0013] (3) Read the subcode from the BRAM, based on The generator matrix uses reverse encoding to perform secondary encoding on the subcode, resulting in 32 bits with a width of [missing information]. The code words;

[0014] Furthermore, in (3) based on The generator matrix uses a reverse encoding method to perform secondary encoding on the subcodes, the implementation of which includes:

[0015] (3a) Set up 32 data registers with a width of N / 32 to store the data, and use a generator matrix with a row and column size of 32. Encode;

[0016] (3b) Read the stored sub-code from the block random access memory (BRAM) in reverse order according to the read address 31~0, and use the data register to store the read sub-code;

[0017] (3c) Encode the registered data, and combine the 32 registered data with... The column vectors are in a one-to-one correspondence, and different processing methods are applied based on the different values ​​of the column vectors:

[0018] If the column vector corresponding to this data register position is '1', then perform an XOR operation on the registered data;

[0019] If the column vector corresponding to this data register position is '0', then keep the original value of the registered data, update the registered data, and store the updated registered data in the corresponding data register to complete the second encoding;

[0020] (3d) Output the codewords after the second encoding in parallel.

[0021] 2. A semi-parallel 5G NR Polar coding device, characterized in that it comprises:

[0022] The serial-to-parallel conversion module is used to divide the serial data of the input encoder into a fixed 32 sub-blocks, that is, to convert single-bit data into N / 32-bit parallel data according to the value of the mother code length N.

[0023] The primary encoding module is used to calculate the sub-blocks and the generator matrix through a pipelined processing method. The encoding result, using Each pipeline register stores the updated sub-block bits, ultimately resulting in 32 sub-codes which are stored in the BRAM memory.

[0024] The secondary encoding module calculates 32 subcodes and the generator matrix using a reverse encoding method. The encoding result is used to store the subcodes read from the BRAM and the updated registered data using 32 data registers. After obtaining 32 codewords, the codewords are output in parallel.

[0025] 3. A non-transitory computer storage medium, characterized in that the non-transitory computer storage medium stores an encoding execution program, the encoding execution program being used to cause the encoding device to execute the satellite communication encoding method according to any one of claims 1 to 6.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Firstly, because the present invention uses a reverse encoding method, it can perform encoding processing while reading Block Random Access Memory (BRAM) data, overcoming the problem of long encoding time caused by the prior art requiring encoding after reading all BRAM data, reducing encoding time and thus improving encoding throughput.

[0028] Secondly, this invention divides the input encoder data into 32 groups, thereby adapting to the characteristics of the 5G NR Polar group interleaving structure, enabling the encoding results to be output in parallel. This overcomes the problem that existing technologies can only output the encoding results serially, reducing the time spent on output and further improving the encoder throughput.

[0029] Thirdly, this invention reduces the critical path length by inserting registers for pipelined processing during the first encoding, overcoming the problem of excessive critical path length caused by excessive calculations in a single clock cycle in the prior art. This can increase the encoder's operating clock frequency, thereby further improving the encoder's throughput. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating the implementation of the semi-parallel 5G NR Polar coding method of the present invention;

[0031] Figure 2 This is a schematic diagram illustrating the first encoding operation in the method of the present invention;

[0032] Figure 3 This is a schematic diagram illustrating the second encoding operation in the method of the present invention;

[0033] Figure 4 This is a structural block diagram of the semi-parallel 5G NR Polar coding device of the present invention;

[0034] Figure 5 This is a schematic diagram showing the result of encoding a Polar codeword with a mother code length of N=1024 using the present invention;

[0035] Figure 6 This is a schematic diagram showing the result of encoding a Polar codeword with a mother code length of N=64 using this invention;

[0036] Figure 7 This is a schematic diagram showing the result of encoding a Polar codeword with a mother code length of N=512 using the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part and not all of the embodiments of the present invention. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0038] It should be noted that the step numbers in the specification and claims of this invention are only for the purpose of clearly describing the embodiments of this invention and facilitating understanding, and their order is not limited.

[0039] Example 1: Semi-parallel 5G NR Polar coding method.

[0040] Reference Figure 1 The implementation steps for this example include the following:

[0041] Step 1: Perform serial-to-parallel conversion on the input data.

[0042] The input data includes: mother code length The serial data needs to be processed in order to output the encoded results in parallel. The implementation includes:

[0043] (1.1) Based on the current value of the mother code length N, the input serial data is divided into 32 groups, and the bit width of each group after grouping is determined to be... For example, serial data with a mother code length of N = 64 is divided into 32 groups, and the width of each group is determined to be 2; or serial data with a mother code length of N = 256 is divided into 32 groups, and the width of each group is determined to be 8.

[0044] (1.2) After completing the grouping, the serial data after grouping is concatenated sequentially to convert it into parallel data, resulting in 32 bits of width. For example, when the mother code length N is 256, 32 sub-blocks with a bit width of 8 can be obtained.

[0045] Step 2: Perform the first encoding on each sub-block.

[0046] (2.1) Determine the generator matrix to be used in this encoding. For serial data with a current mother code length of N, use a generator matrix with a row and column size of N. Generating matrix For example, when the mother code length N is 256, a generator matrix with a row and column size of 8 is used. ;

[0047] (2.2) Determine the number of pipeline register stages that need to be inserted for pipelined processing, for the currently used generator matrix. Then insert Pipeline processing is performed using a multi-stage pipeline register, for example, for the currently used generator matrix. It requires the insertion of a 3-stage pipeline register for pipelined processing;

[0048] (2.3) Update the bits of each sub-block, that is, first update the index to Bits and Generating Matrix The column vectors correspond one-to-one, and different processing is applied to the bits according to different values ​​of the column vectors: if the column vector corresponding to the index of a sub-block bit is '1', then an XOR operation is performed on that bit; if the column vector corresponding to the index of a sub-block bit is '0', then the original value of that bit is kept. The first encoding update structure diagram is as follows: Figure 2 As shown;

[0049] (2.4) Register each updated sub-block bit in the pipeline register to complete the first encoding;

[0050] (2.5) The 32 sub-blocks that have completed the first encoding are called 32 sub-codes. These sub-codes are stored in a block random access memory (BRAM) with a bit width and depth of 32. The first sub-code is stored at address 0, the second sub-code is stored at address 1, and so on, with the last sub-code stored at address 31.

[0051] Step 3: Encode the subcode a second time.

[0052] (3.1) Read the memory subcode from the block random access memory (BRAM) in reverse order. In the first clock cycle, read the memory subcode from BRAM memory address 31. In the second clock cycle, read the memory subcode from BRAM memory address 30. And so on. In the thirty-second clock cycle, read the memory subcode from BRAM memory address 0.

[0053] (3.2) Use data registers to store the subcodes read from BRAM. One subcode corresponds to one data register. The data register for the subcode read from BRAM address 0 is denoted as D0, the data register for the subcode read from BRAM address 1 is denoted as D1, and so on. The data register for the subcode read from BRAM address 31 is denoted as D31.

[0054] (3.3) Update the registered data in the data register, that is, first update the 32 registered data with the generator matrix. The column vectors correspond one-to-one, and different processing is performed on the registered data according to the different values ​​of the column vectors: if the column vector corresponding to the data register position is '1', then an XOR operation is performed on these registered data; if the column vector corresponding to the data register position is '0', then the original value of these registered data is kept. The first encoding update structure diagram is as follows. Figure 3 As shown;

[0055] (3.4) The updated registered data is stored in the pipeline register to complete the second encoding. The 32 subcodes that have completed the second encoding are called 32 codewords.

[0056] (3.5) Output the 32 codewords obtained after the second encoding in parallel according to the order of data registers D0 to D31.

[0057] Example 2: Semi-parallel 5G NR Polar coding device.

[0058] Reference Figure 4This example includes: a serial-to-parallel conversion module 1, a primary encoding module 2, and a secondary encoding module 3. The primary encoding module 2 includes: a first register submodule 21, a status counting submodule 22, a BRAM write address generation submodule 23, a BRAM storage submodule 24, and a signal control submodule 25. The secondary encoding module 3 includes: a BRAM read address generation submodule 31, a second register module 32, and an output codeword index generation submodule 33.

[0059] The working principle of the entire device is as follows:

[0060] The serial-to-parallel conversion module 1 is used to divide the serial data input to the encoder into a fixed 32 sub-blocks, that is, to convert single-bit data into N / 32-bit parallel data according to the value of the mother code length N, and to send the parallel data into the primary encoding module 2.

[0061] The primary encoding module 2 is used to calculate the relationship between each sub-block and the generator matrix through a pipelined processing method. The encoding result, using Each pipeline register stores the updated sub-block bits, where:

[0062] The first register submodule 21 includes A series of pipeline registers, which are used to store the updated sub-block bits during the first encoding process;

[0063] The state counting submodule 22 includes a state counter, which increments the counter value by 1 for each clock cycle during the current sub-block encoding process. The encoding state of the current sub-block is determined by the count value. When the count value is 1... When the count value is less than 1, it indicates that the current sub-block encoding is complete, i.e., a sub-code has been obtained; when the count value is less than 1, it indicates that the current sub-block encoding is complete. The time indicates that the current sub-block encoding is still in progress. After obtaining a sub-code, the counter is cleared to zero. When the next sub-block arrives, the counter starts counting again and sends the count value to the BRAM write address generation submodule 23 for use.

[0064] BRAM write address generation submodule 23 is used to generate the address for writing subcode to the Block Random Access Memory (BRAM). The BRAM write address starts from 0. When the status counter in the status counting submodule 22 counts to... The BRAM write address is incremented by 1 until the maximum write address of the BRAM is 31, and then the write address is sent to the storage BRAM submodule 24.

[0065] The storage BRAM submodule 24 contains a block random access memory (BRAM) with a bit width and depth of 32, which is used to store 32 subcodes after one encoding. The corresponding subcodes are written according to the address given by the BRAM write address generation submodule 23, and then the stored subcodes are sent to the second encoding module 3.

[0066] Signal control submodule 25 is used to indicate the end of the first encoding and interact with the second encoding module 3, determining the end time of the first encoding as N+ based on the N value. When the counter reaches the end time of the first encoding, the encoding end signal becomes valid and is transmitted to the second encoding module 3 to start the second encoding process.

[0067] The secondary encoding module 3 is used to calculate the 32 subcodes and the generator matrix using a reverse encoding method. The encoding result uses 32 data registers to store the subcodes read from the BRAM and the updated register data. After the update, 32 codewords are obtained, of which:

[0068] BRAM read address generation submodule 31 is used to generate BRAM read address. The BRAM read address starts from 31 and is decremented by 1 every clock cycle until the minimum BRAM read address is 0. Then the write address is sent to storage BRAM submodule 24 for use.

[0069] The second register submodule 32 includes 32 data registers, which are defined as D0~D31 respectively. They are used to register the subcodes read from the storage BRAM submodule 24 and the updated register data, and send the updated codewords to the output codeword index generation submodule 33.

[0070] The output codeword index generation submodule 33 is used to generate the output order of codewords. It generates the index according to the order of data registers D0~D31 and outputs codewords with indices 0~31.

[0071] It should be noted that the above functional modules can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, as program instruction products. A program instruction product includes one or a set of program instructions. When the program instructions are loaded and executed on a computer, the described process or function is generated, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The program instructions can be stored in a computer-readable and writable storage medium, or transferred from one computer's readable and writable storage medium to another.

[0072] The direct coupling or communication connection between the modules shown or discussed in this embodiment can be achieved through indirect coupling or communication connection through some interfaces, devices, or modules. The various functional modules and sub-modules in this embodiment can dynamically reside within a single processing unit, or each module can exist physically independently, or two or more modules can dynamically reside within a single processing unit. When the aforementioned dynamic components are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable and writable storage medium, such as a memory, optical disc, or hard disk.

[0073] This invention provides a non-transitory computer storage medium storing an coded executable program that can be loaded by a processor to execute steps in any of the satellite communication channel coding methods provided in this invention. The non-transitory computer storage medium includes both permanent and non-permanent, removable and non-removable media, and can be implemented using any method or technology to store the coded executable program. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, DVD or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0074] The effectiveness of this invention can be illustrated by the following simulation results.

[0075] 1. Simulation experimental conditions.

[0076] The software platform for the simulation experiment of this invention is Vivado 2018.3, using the VHDL hardware description language, and the selected FPGA model is xc7vx690tffg1761-2.

[0077] The application scenarios of the simulation experiments include: Cyclic Redundancy Check Auxiliary Polar Code (CA-Polar) scenario, Parity Check-Cyclic Redundancy Check Auxiliary Polar Code (PC-CA Polar) scenario, and Distributed Cyclic Redundancy Check Polar Code (DCRC-Polar) scenario.

[0078] 2. Simulation experiment content.

[0079] Simulation Experiment 1: In the CA-Polar scenario, the encoder of this invention is used to encode a Polar code with a mother code length of 1024. The results are as follows: Figure 5 As shown. From Figure 5It is evident that the encoding process requires 1094 clock cycles, and the Polar code encoding result with a mother code length of 1024 is correct.

[0080] Simulation Experiment 2: In the PC-CA Polar scenario, the encoder of this invention is used to encode a Polar code with a mother code length of 64. The results are as follows: Figure 6 As shown. From Figure 6 It is evident that the encoding process takes 99 clock cycles, and the Polar code with a mother code length of 64 is correctly encoded.

[0081] Simulation Experiment 3: In the DCRC-Polar scenario, the encoder of this invention is used to encode a Polar code with a master code length of 512. The results are as follows: Figure 7 As shown. From Figure 7 It is evident that the encoding process takes 548 clock cycles, and the Polar code with a mother code length of 512 is correctly encoded.

[0082] Simulation Experiment 4 statistically analyzed the operating clock frequencies of the traditional encoder and the encoder of the present invention in three application scenarios, and the results are shown in Table 1.

[0083] Table 1. Comparison of operating clock frequencies between conventional encoders and the encoder of this invention.

[0084]

[0085] As shown in Table 1, the encoder of this invention exhibits a significant improvement in operating clock frequency compared to traditional encoders in all three scenarios. Specifically, the operating clock frequency is increased by 34MHz in the CA-Polar scenario, by 100MHz in the PC-CA-Polar scenario, and by 70MHz in the DCRC-Polar scenario.

[0086] Simulation Experiment 5 statistically analyzed the throughput of the traditional encoder and the encoder of the present invention in three application scenarios, and the results are shown in Table 2.

[0087] Table 2. Comparison of throughput between conventional encoders and encoders of the present invention

[0088]

[0089] The statistical results in Table 2 show that, compared with traditional encoders, the encoder of the present invention has significantly improved throughput in all three scenarios. Specifically, the throughput can be improved by 109.6% in the CA-Polar scenario, 83% in the PC-CA-Polar scenario, and 130.1% in the DCRC-Polar scenario.

[0090] The simulation results above show that the encoder of the present invention can achieve correct encoding function in three application scenarios, and its working clock frequency and throughput are significantly improved compared with traditional encoders.

Claims

1. A semi-parallel 5G NR Polar coding method, characterized in that, include: (1) Perform serial-to-parallel conversion on the N-length serial data input from the encoder, converting each... Each serial data item is converted into a sub-block, where 32 represents the length of the mother code, and 32 represents the number of conversion sub-blocks. (2) For each sub-block based on The generator matrix is ​​encoded once using a pipelined processing method, resulting in 32 bits with a width of [missing information]. The subcode is stored in the BRAM memory; (3) Read the subcode from the BRAM, based on The generator matrix uses reverse encoding to perform secondary encoding on the subcode, resulting in 32 bits with a width of [missing information]. The code words.

2. The method according to claim 1, characterized in that, The implementation of the serial-to-parallel conversion of the N-length serial data of the input encoder in (1) includes: (1a) Suppose the length of the input encoder is N, the serial data is divided into 32 groups, the bit width of the converted parallel data is determined to be N / 32, the maximum count value of the first counter cnt1 is determined to be N / 32, and the maximum count value of the second counter cnt2 is determined to be 32; (1b) The received serial data is concatenated sequentially, and the first counter cnt1 is used to count the concatenated serial data until the maximum value is reached to complete the conversion of a sub-block. Then the second counter cnt2 is incremented by 1 to count the number of converted sub-blocks until the second counter cnt2 reaches the maximum value, resulting in 32 sub-blocks with a bit width of N / 32.

3. The method according to claim 1, characterized in that, The (2) is based on each sub-block The generator matrix is ​​encoded once using a pipelined processing method, the implementation of which includes: (2a) Based on the value of N, determine the generator matrix to be used for this encoding, which has a row and column size of N / 32. : , in The Arrican kernel is the fundamental constructing matrix for generating matrices. For Kronecker product operation; (2b) Determine the number of pipeline stages in the coding process as follows: Level, use A pipelined register is used to store intermediate encoded data; (2c) Encode each sub-block: index as bits and The column vectors correspond one-to-one, and different processing methods are applied based on the different values ​​of the column vectors: If the column vector corresponding to the index of a sub-block bit is '1', then perform an XOR operation on that bit; If the column vector corresponding to the index of a sub-block bit is '0', then keep the original value of that bit, update each bit and store it in the pipeline register to complete the first encoding; (2d) Store the subcodes after the first encoding into the BRAM memory. The write address of the first subcode is 0, and the write address of the last subcode is 31. The BRAM stores a total of 32 subcodes.

4. The method according to claim 3, characterized in that, The step (2c) updates each bit. A pipelined processing approach is adopted to update bits at different time intervals. The updated bit positions at each time interval are as follows: The first moment is to move the child block to its first position. The bit and the first XORing 1 bit with 1 bit, where This indicates the sub-block bit index, and the updated bit is stored in the first pipeline register. The second moment is to move the child block to its first position. The bit and the first XORing 2 bits together, where The updated bits are stored in the second pipeline register; No. The moment is when the child block is... The bit and the first XORing 1 bit with 1 bit, where , using the The pipeline register stores the updated bits.

5. The method according to claim 1, characterized in that, The (3) based on The generator matrix uses a reverse encoding method to perform secondary encoding on the subcodes, the implementation of which includes: (3a) Set up 32 data registers with a width of N / 32 to store the data, and use a generator matrix with a row and column size of 32. Encode; (3b) Read the stored sub-codes from the BRAM in reverse order according to the read addresses 31~0, and use the data register to store the read sub-codes; (3c) Encode the registered data, and combine the 32 registered data with... The column vectors are in a one-to-one correspondence, and different processing methods are applied based on the different values ​​of the column vectors: If the column vector corresponding to this data register position is '1', then perform an XOR operation on the registered data; If the column vector corresponding to this data register position is '0', then keep the original value of the registered data, update the registered data, and store the updated registered data in the corresponding data register to complete the second encoding; (3d) Output the codewords after the second encoding in parallel.

6. The method according to claim 5, characterized in that, The update of each registered data in step (3c) is performed in reverse order, and is divided into 32 time steps. The update position at each time step is as follows: The first step is to XOR the nth registered data with the (n-1)th registered data, where n=32, and then use the first data register to store the updated data. The second step involves XORing the nth and (n-2)th registered data and storing the updated data in the second data register. Similarly, at the thirty-first time step, the nth registered data and the (n-31)th registered data are XORed, and the updated data at that time step is stored in the thirty-first data register. The thirty-second moment is when the first The first registered data and the first XORing the stored data, where The updated data is stored in the thirty-second data register.

7. A semi-parallel 5G NR Polar coding device, characterized in that, include: The serial-to-parallel conversion module is used to divide the serial data of the input encoder into a fixed 32 sub-blocks, that is, to convert single-bit data into N / 32-bit parallel data according to the value of the mother code length N. The primary encoding module is used to calculate the sub-blocks and the generator matrix through a pipelined processing method. The encoding result, using Each pipeline register stores the updated sub-block bits, ultimately resulting in 32 sub-codes which are stored in the BRAM memory. The secondary encoding module calculates 32 subcodes and the generator matrix using a reverse encoding method. The encoding result is used to store the subcodes read from the BRAM and the updated registered data using 32 data registers. After obtaining 32 codewords, the codewords are output in parallel.

8. The apparatus according to claim 7, characterized in that, The primary encoding module includes: The first register submodule is used to register the updated sub-block bits during the encoding process, including... One pipeline register; The state counting submodule is used to determine the encoding state of the current subcode based on the count value. The state counter counts to... The time indicates that a sub-block encoding is complete. At the next moment, the counter is reset to zero, and the counting restarts after the next completed sub-block code arrives. The BRAM write address generation submodule is used to generate the Block Random Access Memory (BRAM) location for writing subcodes. The BRAM write address starts from 0, and the address is determined when the status counter counts to... The BRAM write address is incremented by 1, and the maximum write address of the BRAM is 31. The storage BRAM submodule is used to store the subcode that has been encoded once. The block random access memory (BRAM) has a bit width and depth of 32. The signal control submodule is used to indicate the end of the first encoding and interact with the second encoding module. The end time of the first encoding is determined as N+ based on the value of N. When the counter reaches the end time of the first encoding, the encoding end signal becomes valid and is transmitted to the second encoding module to start the second encoding process.

9. The apparatus according to claim 7, characterized in that, The secondary encoding module includes: The BRAM read address generation submodule is used to generate the BRAM position for subcode reading. The BRAM read address starts from 31 and is decremented by 1 every clock cycle until the minimum BRAM read address is 0. The second register submodule is used to register the subcode read from the block random access memory (BRAM) and the updated register data. This submodule includes 32 data registers, which are defined as D0~D31 respectively. The output codeword index generation submodule is used to generate the output order of codewords. It generates the index according to the order of BRAM addresses 0~31, and the output codeword index is 0~31.

10. A non-transitory computer storage medium, characterized in that, The non-transitory computer storage medium stores an encoding execution program, which is used to cause the encoding device to execute the satellite communication encoding method according to any one of claims 1 to 6.

Images