Automatic transceiver circuit and control device

Abstract

The application discloses an automatic transceiver circuit and a control device. The automatic transceiver circuit comprises a first Schmitt inverter module, a delay inversion module, a second Schmitt inverter module and a communication chip. The first Schmitt inverter module is used for generating a second signal according to a first signal of a first signal terminal. The delay inversion module outputs an enable delay signal according to the second signal and a power supply voltage of a power supply terminal. The second Schmitt inverter module is used for generating an enable control signal according to the first signal and the enable delay signal. An enable pin of the communication chip is connected to an output module of the second Schmitt inverter module, and is used for outputting a level signal according to the enable control signal. In the automatic transceiver circuit, the first Schmitt inverter module, the delay inversion module and the second Schmitt inverter module are arranged, so that the automatic transceiving of the communication chip can be realized. Moreover, the IO port of the controller is not separately occupied, the communication efficiency of the communication chip is improved, and the problem of uncertain IO output delay of the operating system is solved.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, and in particular to an automatic transceiver circuit and control device. Background Technology

[0002] RS485 (EIA-485) communication has been widely adopted due to its low cost and ease of use. With the rapid development of the Internet of Things (IoT), embedded systems using RS485 communication are also widely used in various fields. However, controllers with operating systems suffer from significant latency issues. Operating system delays are highly unpredictable; system lag can exceed 10 seconds. If I / O ports are used to control the RS485 chip's enable, the enable may fail to turn on or off in a timely manner, resulting in the inability to send or receive data correctly. Furthermore, some MCUs have limited I / O resources, leading to insufficient I / O ports. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems existing in the prior art. Therefore, this application provides an automatic transceiver circuit and control device.

[0004] The automatic transceiver circuit of this application includes:

[0005] A first Schmitt NAND module, wherein the first input terminal and the second input terminal of the first Schmitt NAND module are connected to a first signal terminal, and the second signal is generated according to the first signal terminal, wherein the potential of the second signal is opposite to that of the first signal;

[0006] The delay inversion module is connected to the output terminal and the power supply terminal of the first Schmitt NAND module, respectively, and is used to output an enable delay signal according to the first signal and the power supply voltage of the power supply terminal.

[0007] The second Schmitt NAND module has its first input connected to the first signal terminal and its second input connected to the delay inversion module, and is used to generate an enable control signal based on the first signal and the enable delay signal.

[0008] A communication chip, wherein the enable pin of the communication chip is connected to the output module of the second Schmitt NAND module, and is used to output a level signal according to the enable control signal.

[0009] In some implementations, the first Schmitt NAND module includes:

[0010] The first NAND gate logic chip has its first and second input terminals connected to a first signal terminal, and its output terminal connected to the second input terminal of the second Schmitt NAND module.

[0011] In some implementations, the second Schmitt NAND module includes:

[0012] The second NAND gate logic chip has its first input connected to the first signal terminal, its second input connected to the delay-inverting module, and its output connected to the enable pin of the communication chip.

[0013] In some implementations, the delay inversion module includes:

[0014] A first capacitor, one end of which is connected to the output terminal of the first Schmitt-N AND module, and the other end of which is connected to the second input terminal of the second Schmitt-N AND module;

[0015] A first resistor, one end of which is connected to the other end of the first capacitor, and the other end of which is connected to the power supply.

[0016] The second capacitor has one end connected to the power supply terminal and the other end connected to the ground terminal.

[0017] In some embodiments, the communication chip further includes an output pin connected to a second signal terminal, and the automatic transceiver circuit further includes:

[0018] The second pull-up resistor has one end connected to the power supply terminal and the other end connected to the output pin of the communication chip.

[0019] The second pull-down resistor has one end connected to the ground terminal and the other end connected to the enable pin of the communication chip.

[0020] In some embodiments, the communication chip includes a non-inverting pin and an inverting pin, and the automatic transceiver circuit further includes:

[0021] The first pull-up resistor has one end connected to the power supply terminal and the other end connected to the non-inverting pin.

[0022] The first pull-down resistor has one end connected to the ground terminal and the other end connected to the inverting pin.

[0023] In some embodiments, the automatic transceiver circuit further includes: a first filter resistor, one end of which is connected to the second signal terminal and the other end of which is connected to the communication chip;

[0024] The first filter capacitor has one end connected to the ground terminal and the other end connected to one end of the first filter resistor.

[0025] In some embodiments, the communication chip further includes a data input pin, and the automatic transceiver circuit further includes:

[0026] The second filter resistor has one end connected to the first signal terminal and the other end connected to the data input pin.

[0027] The second filter capacitor has one end connected to the data input pin and the other end of the second filter resistor, and the other end connected to the ground terminal.

[0028] In some embodiments, the automatic transceiver circuit further includes:

[0029] The third capacitor has one end connected to the ground terminal and the other end connected to the power supply terminal and the power input pin of the communication chip.

[0030] In the automatic transceiver circuit and control device of this application, by setting a first Schmitt NAND module, a delay inversion module and a second Schmitt NAND module, the automatic transmission and reception of the communication chip can be realized. Furthermore, it does not require separate occupation of the controller's I / O port, thus solving the problem of uncertain delay caused by the operating system's I / O output and improving the communication efficiency of the communication chip.

[0031] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0032] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0033] Figure 1 This is a circuit diagram of an automatic transceiver circuit according to an embodiment of this application.

[0034] Figure 2 This is another circuit diagram of the automatic transceiver circuit according to an embodiment of this application.

[0035] Explanation of key component symbols:

[0036] 10 - Automatic transceiver circuit; 11 - First Schmitt NAND module; IC1 - First NAND gate logic chip; 12 - Delay inversion module; C2 - First capacitor; R3 - First resistor; C3 - Second capacitor; 13 - Second Schmitt NAND module; IC2 - Second NAND gate logic chip; Communication chip 15; DE - Data receive enable pin; RE - Data transmit enable pin; A - Non-inverting pin; B - Inverting pin; RO - Output pin; VCC - Power input pin; DI - Data input pin; GND - Ground pin; R7 - First pull-up resistor; R6 - First pull-down resistor; R1 - Second pull-up resistor; R2 - Second pull-down resistor; R5 - First filter resistor; C4 - First filter capacitor; R4 - Second filter resistor; C5 - Second filter capacitor; C1 - Third capacitor; GND - Ground terminal; VCC - Power supply terminal; MCU_TX - First signal terminal; MCU_RX - Second signal terminal. Detailed Implementation

[0037] The embodiments of this application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0038] RS485 communication remains widely used in air conditioning, building automation, and industrial control due to its low cost and ease of application. With the rapid development of the Internet of Things (IoT), embedded operating systems using RS485 communication are also widely used in various fields. Currently, controllers with embedded operating systems primarily control RS485 communication enable via I / O ports. However, due to the highly unpredictable latency of embedded operating systems, if the system experiences a lag, the delay can exceed 10 seconds, resulting in the inability to promptly enable or disable RS485 communication, thus preventing normal data transmission and reception. Furthermore, some controllers have a limited number of I / O ports, leading to insufficient I / O capacity.

[0039] In related technologies, transistors can be used to enable automatic transmission and reception. However, due to their slow response speed, transistors result in a certain delay in transmission and reception, making them suitable only for low-speed communication, short communication distances with a small number of nodes, and applications where reliability requirements are not high. For high-speed, long-distance communication, and applications with a large number of communication nodes, reliability cannot be guaranteed.

[0040] In view of this, please refer to Figure 1 or Figure 2This application provides an automatic transceiver circuit 10, which includes a first Schmitt NAND module 11, an enable delay module 12, a second Schmitt NAND module 13, and a communication chip 14. The first and second input terminals of the first Schmitt NAND module 11 are connected to a first signal terminal MCU_TX, and are used to generate a second signal based on a first signal of the first signal terminal MCU_TX. The second signal has the opposite potential to the first signal. The enable delay module 12 is connected to the output terminal and the power supply terminal VCC of the first Schmitt NAND module 11, and is used to output an enable delay signal based on the second signal and the voltage of the power supply terminal VCC. The first input terminal of the second Schmitt NAND module 13 is connected to the first signal terminal MCU_TX, and the second input terminal of the second Schmitt NAND module 13 is connected to the enable delay module 12, and is used to generate an enable control signal based on the first signal and the enable delay signal. The enable pin of the communication chip 14 is connected to the output module of the second Schmitt NAND module 13, and is used to output a level signal based on the enable control signal.

[0041] In the automatic transceiver circuit 10 of this embodiment, by setting a first Schmitt NAND module 11, an enable delay module 12, and a second Schmitt NAND module 13, the automatic transmission and reception of the enable signal of the communication chip 14 is achieved. Furthermore, it eliminates the need to occupy a separate controller I / O port, ensures zero delay in enabling, eliminates limitations on the communication baud rate, and completely eliminates the impact of operating system latency on the communication chip 14's communication. This solves the problem of uncertain operating system I / O output latency due to the controller, thus improving the communication efficiency of the communication chip 14. Moreover, compared to the automatic transceiver circuit using transistors in related patents, the automatic transceiver circuit 10 of this embodiment can be applied to high-speed, long-distance, and multi-node communication scenarios, expanding its applicability.

[0042] Specifically, the first signal terminal MCU_TX is the Tx signal terminal of the controller, which can be a controller with an embedded operating system. The controller is used to send a first signal through the first signal terminal MCU_TX. The first signal can be a level signal, which can be high or low.

[0043] The first Schmitt NAND module 11 and the second Schmitt NAND module 13 both include a first input terminal, a second input terminal, and an output terminal. Both the first Schmitt NAND module 11 and the second Schmitt NAND module 13 are NAND gate modules with Schmitt trigger functionality. That is, when both input terminals of the first Schmitt NAND module 11 or the second Schmitt NAND module 13 are high (logic "1"), the output terminal is low (logic "0"); if at least one input terminal is low (logic "0"), the output terminal is high (logic "1").

[0044] As will be understood by those skilled in the art, a Schmitt trigger is a comparator circuit containing positive feedback, whose state is maintained by the input signal potential. It has two stable states, but unlike a general trigger, the Schmitt trigger has different threshold voltages for input signals with different directions of change: negative decreasing and positive increasing. These two threshold voltages are called the positive threshold voltage (VT+) and the negative threshold voltage (VT-), respectively.

[0045] The first and second input terminals of the first Schmitt NAND module 11 are both connected to the first signal terminal MCU_TX. The output terminal of the first Schmitt NAND module 11 is connected to the enable delay module 12. The first Schmitt NAND module 11 is used to generate a second signal with the opposite potential to the first signal terminal MCU_TX according to the first signal. That is, when the first signal is high, the second signal is low, or when the first signal is low, the second signal is high.

[0046] The enable delay module 12 is also connected to the power supply terminal VCC, which provides power voltage to the enable delay module 12. The enable delay module 12 is used to output an enable delay signal based on the second signal and the power supply voltage. The enable delay signal is a level signal. When the second signal is high, the enable delay module 12 outputs a high-level enable delay signal to the second input terminal of the second Schmitt NAND module 13 based on the second signal and the power supply voltage. During the transition from high to low level of the second signal, the enable delay signal generated by the enable delay module 12 based on the second signal and the power supply voltage first becomes low and then gradually rises to a high level.

[0047] The first input terminal of the second Schmitt NAND module 13 is connected to the first signal terminal MCU_TX, and the second input terminal of the second Schmitt NAND module 13 is connected to the enable delay module 12. The second Schmitt NAND module 13 generates an enable control signal based on the first signal and the enable delay signal. The enable control signal is a level signal; when both the first signal and the enable delay signal are high-level signals, the enable control signal is a low-level signal; when the first signal and / or the enable delay signal are low-level signals, the enable control signal is a high-level signal. This allows the enable control signal to delay the enabling action, preventing the communication chip 14 from receiving its own transmitted data.

[0048] Furthermore, the first Schmitt NAND module 11 includes a first NAND gate logic chip IC1. The first and second input terminals of the first NAND gate logic chip IC1 are connected to the first signal terminal MCU_TX, and the output terminal of the first NAND gate logic chip IC1 is connected to the enable delay module 12. Those skilled in the art will understand that a NAND gate logic chip is a very basic and commonly used logic gate chip in digital circuits. It has two input terminals and one output terminal. When both inputs are high (1), the output is low (0); if at least one input is low (0), the output is high (1). A NAND gate can be seen as a superposition of an AND gate and a NOT gate, performing an AND operation first, followed by a NOT operation.

[0049] The second Schmitt NAND module 13 includes a second NAND gate logic chip IC2. The first input terminal of the second NAND gate logic chip IC2 is connected to the first signal terminal MCU_TX, and the output terminal of the second NAND gate logic chip IC2 is connected to the communication chip 14.

[0050] The enable delay module 12 includes a first capacitor C2, a first resistor R3, and a second capacitor C3. One end of the first capacitor C2 is connected to the output terminal of the first Schmitt-NAND module 11, and the other end is connected to the second input terminal of the second NAND gate logic chip IC2. One end of the first resistor R3 is connected to the other end of the first capacitor C2, and the other end is connected to the power supply terminal VCC. One end of the second capacitor C3 is connected to the power supply terminal VCC, and the other end is connected to the ground terminal GND. The first resistor R3 is used to charge and discharge the first capacitor C2, and the second capacitor C3 is used to store energy. The first capacitor C2 has the function of delaying the enable switch to prevent the communication chip 14 from receiving data it sent.

[0051] Communication chip 14 can be an RS485 chip. RS-485 is a serial communication protocol based on differential signal transmission. It features long-distance transmission and is widely used in long-distance serial communication in fields such as air conditioning, building automation control, or industrial control. For example, in some examples, communication chip 14 can be illustrated using a chip of model MAX14783. Understandably, MAX14783 is an integrated circuit (IC) chip primarily used for half-duplex RS-485 / RS-422 communication.

[0052] Please refer to further information. Figure 1 or Figure 2The communication chip 14 may include an enable pin, an output pin RO, a non-inverting pin A, an inverting pin B, a power supply pin, and a ground pin GND. The enable pin includes a data receive enable pin DE and a data transmit enable pin RE. Both the data receive enable pin DE and the data transmit enable pin RE are connected to the output of the second Schmitt NAND module 13 to receive the enable control signal output by the second Schmitt NAND module 13. When the enable pin receives a high-level enable control signal, the communication chip 14 is in the transmit state, and the non-inverting pin A outputs a low level, while the inverting pin B outputs a high level. When the enable pin receives a low-level enable control signal, the non-inverting pin A outputs a high level, and the inverting pin B outputs a low level.

[0053] The output pin RO is connected to the controller's second signal terminal MCU_RX, used to convert the received level signal into a TTL level signal for the controller to process. The non-inverting pin A is the positive terminal of the differential signal, used to transmit the positive portion of the differential signal, and the inverting pin B is the negative terminal of the differential signal, used to transmit the negative portion of the differential signal. When the logic signal is 1, the voltage at the non-inverting pin A is lower than that at the inverting pin B (i.e., A-, B+); when the logic signal is 0, the voltage difference between the non-inverting pin A and the inverting pin B is negative. The power supply pin is connected to the power supply terminal VCC to power the communication chip 14, and the ground pin GND is connected to the ground terminal GND.

[0054] After the controller is powered on, the first signal of the controller's first signal terminal MCU_TX changes from low level to high level. After being inverted by the first NAND gate logic chip IC1, the output terminal of the first NAND gate logic chip IC1 outputs a low level. Since the first resistor R3 is connected to the power supply terminal VCC, the second input terminal of the second NAND gate logic chip IC2 is also at a high level after being charged by the power supply terminal VCC. Therefore, both inputs of the second NAND gate logic chip IC2 are at a high level, so the output terminal of the second NAND gate logic chip IC2 is at a low level.

[0055] The instant the first signal of the first signal terminal MCU_TX changes from high to low, the first and second input terminals of the first NAND gate logic chip IC1 are low, the output terminal of the first NAND gate logic chip IC1 is high, and the first input terminal of the second NAND gate logic chip IC2 is low. Since the potential of the first capacitor C2 cannot change abruptly, the second input terminal of the second NAND gate logic chip IC2 is high (2 times VCC), making the output terminal of the second NAND gate logic chip IC2 high. However, as the first resistor R3 discharges, the voltage of the second input terminal of the second NAND gate logic chip IC2 gradually decreases and approaches the VCC voltage.

[0056] Therefore, during the entire period when the first signal terminal MCU_TX is low, the output of the second NAND gate logic chip IC2 is high. That is, the enable pin of communication chip 14 is high, and the enable of communication chip 14 is in the transmit state. According to the output logic of communication chip 14: when the first signal terminal MCU_TX is low, the non-inverting pin A outputs a low level, and the inverting pin B outputs a high level.

[0057] The instant the first signal of the first signal terminal MCU_TX changes from low to high, the first and second input terminals of the first NAND gate logic chip IC1 are high, and the output terminal of the first NAND gate logic chip IC1 is low. Because the voltage across the first capacitor C2 cannot change abruptly, the potential between the second input terminal of the second NAND gate logic chip IC2 and the first capacitor C2 will also drop from high (VCC) to 0V. However, as R3 charges the first capacitor C2, since the second input terminal of the second NAND gate logic chip IC2 is low, the output terminal of the second NAND gate logic chip remains high. As the voltage at the second input terminal of the second NAND gate logic chip IC2 gradually increases, when this voltage exceeds the typical value of 1.8V, that is, when both the first and second input terminals of the second NAND gate logic chip IC2 become high, the output terminal of the second NAND gate logic chip IC2 will reverse to low.

[0058] After the first signal of MCU_TX at the first signal terminal goes high again, the enable pin of communication chip 14 remains high for tens of microseconds before going low. According to the output logic of communication chip 14: when the enable of communication chip 14 is in a high configuration, the non-inverting pin A outputs a low level, and the inverting pin B outputs a high level.

[0059] In some embodiments, the automatic transceiver circuit 10 further includes a first pull-up resistor R7 and a first pull-down resistor R6. One end of the first pull-up resistor R7 is connected to the power supply terminal VCC, and the other end of the first pull-up resistor R7 is connected to the non-inverting pin A. One end of the first pull-down resistor R6 is connected to the ground terminal GND, and the other end of the first pull-down resistor R6 is connected to the inverting pin B.

[0060] It should be noted that the first pull-up resistor R7 ensures that the non-inverting pin A is high in the idle or default state. This helps prevent uncertain states that may occur when the non-inverting pin A is floating, thereby improving the reliability of the circuit. The first pull-down resistor R6 ensures that the signal inverting pin B is low in the idle or default state. This helps prevent uncertain states that may occur when the inverting pin B is floating, thereby improving the reliability of the circuit.

[0061] The resistance values ​​of the first pull-up resistor R7 and the first pull-down resistor R6 can be determined based on the bus interference, number of nodes, and impedance of the non-inverting pin A and the inverting pin B. Generally, the greater the interference, the smaller the resistance value needs to be. Typically, the resistance of the first pull-up resistor R7 and the first pull-down resistor R6 is greater than or equal to 470 ohms.

[0062] Thus, by setting the first pull-up resistor R7 and the first pull-down resistor R6, data can be transmitted normally between the non-inverting pin A and the inverting pin B.

[0063] In some embodiments, the automatic transceiver circuit 10 further includes a second pull-up resistor R1 and a second pull-down resistor R2. One end of the second pull-up resistor R1 is connected to the power supply terminal VCC, and the other end of the second pull-up resistor R1 is connected to the output pin RO of the communication chip 14. One end of the second pull-down resistor R2 is connected to the ground terminal GND, and the other end of the second pull-down resistor R2 is connected to the enable pin of the communication chip 14.

[0064] The second pull-up resistor R1 ensures that the output pin RO is high in the idle or default state. This helps prevent uncertain states that may occur when the output pin RO is floating, thereby improving bus interference immunity. The second pull-down resistor R2 ensures that the enable pin is low in the idle or default state. This helps prevent uncertain states that may occur when the enable pin is floating, improving the reliability of the automatic transceiver circuit 10.

[0065] In some embodiments, the automatic transceiver circuit 10 further includes a first filter resistor R5 and a first filter capacitor C4, which can form an RC filter unit. One end of the first filter resistor R5 is connected to the second signal terminal MCU_RX, and the other end is connected to the output pin RO of the communication chip 14; one end of the first filter capacitor C4 is connected to the ground terminal GND, and the other end is connected to one end of the first filter resistor R5.

[0066] Thus, by setting the first filter resistor R5 and the first filter capacitor C4, interference from the output pin RO can be filtered out, improving the reliability of the output signal from the output pin RO.

[0067] Please refer to further information. Figure 2 In some embodiments, the communication chip 14 further includes a data input pin DI, which is connected to the ground terminal GND. In this embodiment, the communication chip 14 transmits data through the first signal terminal MCU_TX of the controller, and the grounding of the data input pin DI is only to provide a stable level reference. When the first signal terminal MCU_TX of the controller transmits data, it generates a high-low level change on the data input pin DI.

[0068] Please refer to further information. Figure 1 In some embodiments, the communication chip 14 further includes a data input pin DI, and the automatic transceiver circuit 10 further includes a second filter resistor R4 and a second filter capacitor C5. The second filter resistor R4 and the second filter capacitor C5 constitute an RC filter unit. One end of the second filter resistor R4 is connected to the first signal terminal MCU_TX, and the other end of the second filter resistor R4 is connected to the data input pin DI. One end of the second filter capacitor C5 is connected to the data input pin DI and the other end of the second filter resistor R4, and the other end of the second filter capacitor C5 is connected to the ground terminal GND.

[0069] In some embodiments, the automatic transceiver circuit 10 further includes a third capacitor C1, one end of which is connected to the ground terminal GND, and the other end of which is connected to the power supply terminal VCC and the power input pin VCC of the communication chip 14.

[0070] The third capacitor C1 is used for filtering or decoupling at the power supply VCC. The third capacitor C1 can effectively absorb noise and ripple in the power supply, providing a more stable power environment for the communication chip 14.

[0071] The control device provided in this application includes a controller and an automatic transceiver circuit 10 of any of the above embodiments.

[0072] The control device provided in this application, by setting a first Schmitt NAND module 11 and a second Schmitt NAND module 13, enables automatic transmission and reception of the enable signal of the communication chip 14. Furthermore, it eliminates the need to separately occupy the controller's I / O port, provides zero delay in enabling, has no limitation on the communication baud rate, and the operating system's latency does not affect the communication of the communication chip 14. This solves the problem of uncertain delays in the controller's operating system I / O output, improving the communication efficiency of the communication chip 14. In addition, compared to the automatic transmission and reception using transistors in related technologies, it can be applied to high-speed, long-distance, and multi-node communication scenarios, thus expanding its applicability.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0074] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. An automatic transceiver circuit, characterized in that, The automatic transceiver circuit includes: A first Schmitt NAND module, wherein the first input terminal and the second input terminal of the first Schmitt NAND module are connected to a first signal terminal, and the second signal is generated according to the first signal terminal, wherein the potential of the second signal is opposite to that of the first signal; The delay inversion module is connected to the output terminal and the power supply terminal of the first Schmitt-NAND module, respectively, and is used to output an enable delay signal according to the second signal and the power supply voltage of the power supply terminal. The second Schmitt NAND module has its first input connected to the first signal terminal and its second input connected to the delay inversion module, and is used to generate an enable control signal based on the first signal and the enable delay signal. A communication chip, wherein the enable pin of the communication chip is connected to the output module of the second Schmitt NAND module, and is used to output a level signal according to the enable control signal.

2. The automatic transceiver circuit according to claim 1, characterized in that, The first Schmitt NAND module includes: The first NAND gate logic chip has its first and second input terminals connected to a first signal terminal, and its output terminal connected to the second input terminal of the second Schmitt NAND module.

3. The automatic transceiver circuit according to claim 1, characterized in that, The second Schmitt NAND module includes: The second NAND gate logic chip has its first input connected to the first signal terminal, its second input connected to the delay-inverting module, and its output connected to the enable pin of the communication chip.

4. The automatic transceiver circuit according to claim 1, characterized in that, The delay inversion module includes: A first capacitor, one end of which is connected to the output terminal of the first Schmitt-N AND module, and the other end of which is connected to the second input terminal of the second Schmitt-N AND module; A first resistor, one end of which is connected to the other end of the first capacitor, and the other end of which is connected to the power supply. The second capacitor has one end connected to the power supply terminal and the other end connected to the ground terminal.

5. The automatic transceiver circuit according to claim 1, characterized in that, The communication chip includes a non-inverting pin and an inverting pin, and the automatic transceiver circuit further includes: The first pull-up resistor has one end connected to the power supply terminal and the other end connected to the non-inverting pin. The first pull-down resistor has one end connected to the ground terminal and the other end connected to the inverting pin.

6. The automatic transceiver circuit according to claim 1, characterized in that, The communication chip further includes an output pin, which is connected to a second signal terminal. The automatic transceiver circuit further includes: The second pull-up resistor has one end connected to the power supply terminal and the other end connected to the output pin of the communication chip. The second pull-down resistor has one end connected to the ground terminal and the other end connected to the enable pin of the communication chip.

7. The automatic transceiver circuit according to claim 1, characterized in that, The automatic transceiver circuit also includes: The first filter resistor has one end connected to the second signal terminal and the other end connected to the output pin of the communication chip. The first filter capacitor has one end connected to the ground terminal and the other end connected to one end of the first filter resistor.

8. The automatic transceiver circuit according to claim 1, characterized in that, The communication chip also includes a data input pin, and the automatic transceiver circuit further includes: The second filter resistor has one end connected to the first signal terminal and the other end connected to the data input pin. The second filter capacitor has one end connected to the data input pin and the other end of the second filter resistor, and the other end connected to the ground terminal.

9. The automatic transceiver circuit according to claim 1, characterized in that, The automatic transceiver circuit also includes: The third capacitor has one end connected to the ground terminal and the other end connected to the power supply terminal and the power input pin of the communication chip.

10. A control device, characterized in that, Includes the automatic transceiver circuit as described in any one of claims 1-9.

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