Image data processing method, apparatus, device and system

Abstract

The disclosure provides an image data processing method, device, equipment and system, and relates to the technical field of image data processing. The method comprises the following steps: receiving a storage address from a host; wherein the storage address is used to indicate the storage position of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; in response to receiving a trigger signal, the image processing parameters are batched from the host memory according to the storage address; wherein the trigger signal is used to indicate that image data processing is performed; and the image data processing is performed according to the image processing parameters. The method can improve the image processing efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of image data processing technology, and in particular to an image data processing method, apparatus, device and system. Background Technology

[0002] Image encoding and decoding technology is a multimedia processing technology that compresses and decompresses image data to achieve efficient storage and transmission. However, existing image encoding and decoding technologies suffer from cumbersome and time-consuming processes, resulting in low image processing efficiency. Summary of the Invention

[0003] This disclosure presents an image data processing method, apparatus, device, and system.

[0004] In a first aspect, embodiments of this disclosure propose an image data processing method, comprising: receiving a storage address from a host; wherein the storage address is used to indicate the storage location of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; in response to receiving a trigger signal, batch retrieving image processing parameters from the host memory according to the storage address; wherein the trigger signal is used to indicate image data processing; and performing image data processing according to the image processing parameters.

[0005] In one possible implementation, the above-mentioned batch acquisition of image processing parameters from host memory based on storage address includes: acquiring image processing parameters from host memory in batches based on storage address via a Direct Memory Access (DMA) controller.

[0006] In one possible implementation, the storage address is received via an address register; wherein, the above-mentioned acquisition of image processing parameters from host memory based on the storage address via the direct memory access (DMA) controller includes: reading the storage address from the address register; and acquiring image processing parameters in batches from host memory based on the storage address via the DMA controller.

[0007] In one possible implementation, the method provided by the first aspect further includes receiving a trigger signal via a start control register.

[0008] In one possible implementation, the image processing parameters include image processing parameters corresponding to multiple frames of images. The image processing parameters corresponding to each frame of images are independently encapsulated in a structured command block according to a structured format. The structured command blocks corresponding to each frame of images are stored in a contiguous address area of ​​the host memory according to the processing order of each frame of images.

[0009] In one possible implementation, the above-mentioned image data processing based on image processing parameters includes: processing image data for each frame of image according to the image processing parameters corresponding to each frame of image in a multi-stage pipeline manner; wherein, the image data processing for each frame of image includes: multiple ordered stages determined according to the image processing parameters of the corresponding frame; the multi-stage pipeline manner is to execute each stage of image data processing for the same frame of image in a stage-sequential manner, and to execute different stages of image data processing for different frames of image in parallel.

[0010] In one possible implementation, the method provided in the first aspect further includes: receiving a number of tasks from the host; wherein the number of tasks is the total number of frames of the images to be processed. The step of batch retrieving image processing parameters from host memory based on storage addresses includes: determining the address of the structured command block corresponding to the image based on the storage address, the number of tasks, and the length of a preset structured command block; and batch retrieving image processing parameters corresponding to each frame of the image from host memory based on the address of the structured command block corresponding to the image.

[0011] In one possible implementation, the number of received storage addresses is multiple, and each storage address corresponds to a structured command block corresponding to a frame of image.

[0012] In one possible implementation, the structured command block further includes a status area; wherein, after image data processing is performed according to image processing parameters, the method provided by the first aspect further includes: writing status information into the status area; wherein the status information is used to indicate whether the image data processing was successful or failed.

[0013] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0014] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0015] Secondly, embodiments of this disclosure propose an image data processing method, comprising: sending a storage address; wherein the storage address is used to indicate the storage location of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; sending a trigger signal; wherein the trigger signal is used to indicate image data processing, and the trigger signal is used to trigger the batch acquisition of the image processing parameters from the host memory according to the storage address.

[0016] In one possible implementation, sending the storage address includes: writing the storage address to the address register; Sending a trigger signal includes writing a trigger signal to the start control register.

[0017] In one possible implementation, the image processing parameters include image processing parameters corresponding to multiple frames of images. Before sending the storage address, the method provided by the second aspect further includes: independently encapsulating the image processing parameters corresponding to each frame of image in a structured command block according to a structured format; and storing the structured command blocks corresponding to each frame of image in a contiguous address area of ​​the host memory according to the processing order of each frame of image.

[0018] In one possible implementation, the method provided by the second aspect further includes: sending a number of tasks; wherein the number of tasks is the total number of frames of the image to be processed.

[0019] In one possible implementation, there are multiple storage addresses, each storage address corresponding to a structured command block for a frame of image.

[0020] In one possible implementation, the structured command block further includes a status area; after sending the trigger signal, the method provided by the second aspect further includes: in response to receiving a notification signal, reading status information from the structured command block corresponding to the notification signal; wherein the status information is used to indicate whether the image data processing is successful or failed; if the status information indicates that the image data processing is successful, acquiring the processed image data; if the status information indicates that the image data processing has failed, sending the trigger signal again.

[0021] In one possible implementation, after sending the trigger signal, the method provided by the second aspect further includes: in response to determining that the image processor has undergone a hardware function upgrade, determining the configuration parameters corresponding to the hardware function upgrade; and updating or expanding the fields in the structured command block corresponding to the configuration parameters corresponding to the hardware function upgrade based on the parameters corresponding to the image processor change and the structured format rules of the structured command block, to obtain a new structured command block.

[0022] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0023] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0024] Thirdly, embodiments of this disclosure provide an image data processing apparatus, including: an address receiving module, a parameter acquisition module, and an image processing module. The address receiving module is configured to receive a storage address from a host; wherein the storage address indicates the storage location of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format. The parameter acquisition module is configured to, in response to receiving a trigger signal, acquire image processing parameters in batches from the host memory according to the storage address; wherein the trigger signal indicates that image data processing should be performed. The image processing module is configured to perform image data processing based on the image processing parameters.

[0025] In one possible implementation, the parameter acquisition module is further configured to acquire image processing parameters in batches from the host memory based on the storage address via a direct memory access (DMA) controller.

[0026] In one possible implementation, the storage address is received via an address register; the parameter acquisition module is also configured to: read the storage address from the address register; and acquire image processing parameters in batches from the host memory based on the storage address via the DMA controller.

[0027] In one possible implementation, the image data processing apparatus proposed in the third aspect further includes a signal receiving module. The signal receiving module is configured to receive a trigger signal via a start control register.

[0028] In one possible implementation, the image processing parameters include image processing parameters corresponding to multiple frames of images. The image processing parameters corresponding to each frame of images are independently encapsulated in a structured command block according to a structured format. The structured command blocks corresponding to each frame of images are stored in a contiguous address area of ​​the host memory according to the processing order of each frame of images.

[0029] In one possible implementation, the image processing module is further configured to: perform image data processing on each frame of image according to the image processing parameters corresponding to each frame of image in a multi-stage pipeline manner; wherein, the image data processing of each frame of image includes: multiple ordered stages determined according to the image processing parameters of the corresponding frame; the multi-stage pipeline manner is to execute each stage of image data processing of the same frame of image in a stage-sequential manner, and to execute different stages of image data processing of different frames of image in parallel.

[0030] In one possible implementation, the image data processing apparatus proposed in the third aspect further includes a task receiving module. The task receiving module is configured to receive a number of tasks from the host; wherein the number of tasks is the total number of frames of the images to be processed. The parameter acquisition module is further configured to: determine the address of the structured command block corresponding to the image based on the storage address, the number of tasks, and the preset length of the structured command block; and acquire image processing parameters corresponding to each frame of the image in batches from the host memory based on the address of the structured command block corresponding to the image.

[0031] In one possible implementation, the number of received storage addresses is multiple, and each storage address corresponds to a structured command block corresponding to a frame of image.

[0032] In one possible implementation, the structured command block further includes a status area; wherein, the image data processing apparatus proposed in the third aspect further includes a status writing module. The status writing module is configured to write status information into the status area; wherein the status information is used to indicate whether the image data processing was successful or failed.

[0033] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0034] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0035] Fourthly, embodiments of this disclosure provide an image data processing apparatus, comprising: a first sending module and a second sending module. The first sending module is configured to send a storage address; wherein the storage address indicates the storage location of image processing parameters in host memory, and the image processing parameters are stored in host memory in a structured format. The second sending module is configured to send a trigger signal; wherein the trigger signal indicates image data processing, and the trigger signal triggers the batch retrieval of the image processing parameters from the host memory according to the storage address.

[0036] In one possible implementation, the first transmitting module is further configured to write a storage address to the address register; the second transmitting module is further configured to write a trigger signal to the start control register.

[0037] In one possible implementation, the image processing parameters include image processing parameters corresponding to multiple frames of images. The image data processing apparatus provided in the fourth aspect may further include an encapsulation module and a storage module. The encapsulation module is configured to independently encapsulate the image processing parameters corresponding to each frame of image in a structured command block according to a structured format. The storage module is configured to store the structured command blocks corresponding to each frame of image in a contiguous address region of the host memory according to the processing order of each frame of image.

[0038] In one possible implementation, the image data processing apparatus provided in the fourth aspect may further include: a third transmitting module. The first transmitting module is configured to transmit a number of tasks; wherein the number of tasks is the total number of frames of the images to be processed.

[0039] In one possible implementation, there are multiple storage addresses, each storage address corresponding to a structured command block for a frame of image.

[0040] In one possible implementation, the structured command block further includes a status area; the image data processing apparatus provided in the fourth aspect may further include: a reading module and an acquisition module. The reading module is configured to: in response to receiving a notification signal, read status information from the structured command block corresponding to the notification signal; wherein the status information is used to indicate whether the image data processing was successful or failed. The acquisition module is configured to: acquire the processed image data if the status information indicates that the image data processing was successful. The second sending module is further configured to: resend the trigger signal if the status information indicates that the image data processing failed.

[0041] In one possible implementation, after sending the trigger signal, the image data processing apparatus provided by the fourth aspect may further include: a determination module and a command block update module. The determination module is configured to: in response to determining a hardware function upgrade of the image processor, determine the configuration parameters corresponding to the hardware function upgrade. The command block update module is configured to: based on the parameters corresponding to the image processor change and the structured format rules of the structured command block, update or expand the fields in the structured command block corresponding to the configuration parameters corresponding to the hardware function upgrade, to obtain a new structured command block.

[0042] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0043] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0044] Fifthly, embodiments of this disclosure provide an image data processing system, including an image processor and a host. The image processor is configured to implement the methods described in the first aspect and any possible implementation thereof. The host is configured to implement the methods described in the second aspect and any possible implementation thereof.

[0045] In a sixth aspect, embodiments of this disclosure provide an electronic device, including: a processor, and a memory for storing processor-executable instructions. The processor is configured to, when executing instructions stored in the memory, implement any of the possible implementations of the first and second aspects, or the methods of the second aspect and any of its possible implementations.

[0046] In a seventh aspect, embodiments of this disclosure provide a chip including a processor for executing any of the possible implementations of the first and second aspects, or the methods in the second and any of the possible implementations of the second aspect.

[0047] Eighthly, embodiments of this disclosure provide a non-volatile computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement any of the possible implementations of the first and second aspects, or the methods in the second aspect and any of the possible implementations of the second aspect.

[0048] In a ninth aspect, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the steps of any possible implementation of the first and second aspects, or the method in the second aspect and any possible implementation of the second aspect.

[0049] The image data processing methods, apparatus, systems, chips, electronic devices, computer-readable storage media, and computer program products provided in this disclosure enable image processors to obtain image processing parameters sent by the host through storage addresses, eliminating the need to retrieve parameters from each register individually. This simplifies the parameter configuration process and improves image processing efficiency.

[0050] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description.

[0051] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0052] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is an exemplary system architecture to which this disclosure can be applied; Figure 2 A flowchart of an image data processing method provided in this disclosure embodiment; Figure 3 A flowchart of another image data processing method provided in this disclosure embodiment; Figure 4 A structural block diagram of an image data processing apparatus provided in an embodiment of this disclosure; Figure 5 A structural block diagram of another image data processing apparatus provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device suitable for performing an image data processing method, provided as an embodiment of the present disclosure. Detailed Implementation

[0053] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] It should be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0055] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0056] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0057] Figure 1 An exemplary system architecture 100 is shown, in which embodiments of the image data processing methods, apparatus, systems, chips, electronic devices, computer-readable storage media, and computer program products of the present disclosure can be applied.

[0058] like Figure 1 As shown, system architecture 100 may include a first device 101 and a second device 102, which can be connected via a network. The network serves as the medium for providing a communication link between the first device 101 and the second device 102. The network may include various connection types, such as wired or wireless communication links or fiber optic cables, etc.

[0059] The first device 101 and the second device 102 can be either hardware or software. When the first device 101 and the second device 102 are hardware, the first device 101 can be a JPEG Processing Unit (JPU), an image processor, a device including a JPU, a device including an image processor, etc., and the second device 102 can be a Central Processing Unit (CPU), a host, a device including a CPU, a device including a host, etc. When the first device 101 and the second device 102 are software, they can be installed in the electronic devices listed above. They can be implemented as multiple software programs or software modules, or as a single software program or software module; no specific limitations are made here.

[0060] It should be understood that Figure 1 The number of first and second devices shown is merely illustrative. Any number of first and second devices can be used depending on implementation requirements.

[0061] In some embodiments, the image encoding and decoding process may include steps 1 to 6 below.

[0062] Step 1: Initialize the hardware and configure the corresponding registers.

[0063] For example, before the image encoding / decoding task starts, the host performs hardware initialization operations on the JPEG Processing Unit (JPU). The host transmits initialization-related parameters to the JPU by writing configuration parameters to the JPU's registers, enabling the JPU to enter a normal working state.

[0064] Step 2: Load the quantization matrix item by item.

[0065] After hardware initialization is complete, the host computer loads the quantization matrix into the JPU to control the coefficient quantization during image compression or decompression. The host computer sequentially writes each parameter of the quantization matrix into the JPU's registers, and after writing each parameter, confirms that the parameter has been correctly received by the JPU.

[0066] The above parameter writing process is executed serially, which is time-consuming in high-resolution image or multi-frame image data processing scenarios, and places high demands on the software control logic on the host side.

[0067] Step 3: Load the Huffman tables item by item.

[0068] After the quantization matrix is ​​loaded, the host configures a Huffman table for the JPU.

[0069] For example, the host writes each Huffman code table into the JPU's register one by one, and performs the write operation according to the JPU's preset format and order to ensure that the written Huffman code table is legal and valid.

[0070] Step 4: Configure the input buffer and output buffer.

[0071] After the quantization matrix and Huffman table are loaded, the host configures the input data buffer and the output data buffer, including configuring the corresponding physical addresses for the luminance component Y, the blue color difference component Cb, and the red color difference component Cr, setting the start address and length of the bit stream buffer, and configuring access restrictions and other related parameters for each buffer.

[0072] The host writes the above buffer-related parameters into the JPU's registers one by one, ensuring that the configured address and length parameters are correct.

[0073] Step 5: Trigger the JPU to execute encoding / decoding tasks by writing control instructions to the startup register.

[0074] Before performing encoding or decoding tasks, the host first confirms that the JPU is in an idle state, which can be achieved by polling the status register or reading the idle flag.

[0075] After confirming that the JPU is idle and that all configuration parameters have been loaded, the host triggers the JPU startup task by writing control instructions to the START register or ENABLE register.

[0076] The JPU reads pre-configured parameters from registers, including initialization-related parameters, image parameters, quantization matrix, Huffman table, and buffer-related parameters, and performs corresponding encoding or decoding operations based on the read parameters.

[0077] Step 6: Wait for the hardware to complete and read the output result information.

[0078] During the JPU's encoding or decoding tasks, the host side confirms the task execution status by polling the busy (BUSY) flag or waiting for hardware notification signals.

[0079] After the JPU completes its task, the host computer reads the task execution result from the JPU. The execution result includes the output length, status flags, and error information. Subsequently, the host computer performs subsequent processing operations on the data in the output buffer.

[0080] In the aforementioned image encoding and decoding process, the host side loads various parameters by writing them to registers one by one, which is cumbersome and time-consuming, resulting in low image processing efficiency.

[0081] In addition, the host loads various parameters by writing them to registers one by one. The writing order is fixed, and a single task startup requires hundreds to thousands of register operations, which greatly increases the burden on the host and makes the driver logic complex and difficult to maintain.

[0082] The host writes the quantization matrix and Huffman table sequentially through registers. However, due to limitations in register bit width and interface mechanisms, data transmission bandwidth is low, writes are discontinuous, and data formats differ across hardware, requiring separate driver adaptation. These issues prolong initialization time, increase host load, and significantly reduce overall system throughput efficiency.

[0083] The host computer needs to synchronously drive the hardware according to a fixed process: configure registers, load the quantization matrix and Huffman table, write to the configuration registers again, start the JPU, poll the status or wait for an interrupt, and read the results. The host cannot submit the complete task at once; it needs to synchronously wait for each stage to complete, making it difficult to support multi-task, multi-threaded, and multi-stream parallel processing, reducing CPU utilization and increasing system latency.

[0084] It only supports register interface configuration, lacks the ability to read complex task descriptions from memory, cannot parse structured data formats, cannot automatically read configuration content from memory, does not support batch loading of configuration content using DMA or other methods, and cannot automatically distribute parameters such as quantization matrices and Huffman tables to the corresponding processing modules, making it difficult to achieve efficient and automated task configuration.

[0085] Register-based parameter transfer is inefficient. In scenarios requiring large amounts of configuration data, such as Joint Photographic Experts Group (JPEG) / Motion Joint Photographic Experts Group (MJPEG) image formats, frequent register writes prolong the configuration cycle, consume a large amount of CPU resources, and do not support efficient batch data transfer such as Direct Memory Access (DMA), thus limiting image processing throughput. In mobile system-on-chip (SoC) and embedded systems, this significantly reduces the system's energy efficiency ratio.

[0086] Please refer to Figure 2 , Figure 2 This is a flowchart of an image data processing method provided in an embodiment of the present disclosure. The executing entity is a first device 101, and the process 200 includes the following steps.

[0087] Step 201: Receive the storage address from the host.

[0088] For example, the storage address is used to indicate the storage location of image processing parameters in the host memory.

[0089] For example, image processing parameters are used for image data processing. These parameters include various configuration information required by the JPU to perform image data processing.

[0090] For example, the storage address can be the starting address of the image processing parameters in the host memory, or it can be any other address that can locate the image processing parameters.

[0091] For example, host can refer to CPU or a device that includes CPU, and host memory can refer to memory on the CPU side or host side.

[0092] For example, image processing parameters are stored in host memory in a structured format. This structured format can refer to a fixed format or a preset format. For instance, multiple parameters are stored according to a preset data structure, forming a parameter set with a fixed format and corresponding relationships. This can be achieved by encapsulating parameters according to a preset data structure, field order, and / or data type, ensuring that each parameter has a clearly defined storage location, length, and corresponding relationship in memory.

[0093] Step 202: In response to receiving the trigger signal, batch retrieve image processing parameters from the host memory according to the storage address.

[0094] For example, a trigger signal is used to indicate that image data processing should be performed.

[0095] In this embodiment of the disclosure, the first device 101 is described as a JPU or an image processor.

[0096] Optionally, after receiving the storage address from the host, the first device 101 retrieves the image processing parameters from the host memory based on the storage address.

[0097] The embodiments disclosed herein do not limit the specific timing of receiving the trigger signal and receiving the storage address; they can be received simultaneously or sequentially, as long as the storage address is received between the use of the storage address.

[0098] Step 203: Process image data according to image processing parameters.

[0099] Image data processing refers to encoding or decoding operations performed by the JPU. For example, the JPU processes the input image data according to the image processing parameters to obtain the processed image data.

[0100] The method provided in this disclosure receives the storage address of image processing parameters in the host memory. The image processing parameters are stored in the host memory in a structured format. In response to receiving a trigger signal, the image processing parameters are retrieved from the host memory according to the storage address. In this way, the image processor obtains the image processing parameters sent by the host through the storage address, without having to retrieve the parameters from each register one by one. The parameter configuration process is simple and can improve the image processing efficiency.

[0101] In some embodiments, step 202, which involves retrieving image processing parameters from host memory based on a storage address, may include step A1.

[0102] Step A1: Obtain image processing parameters from host memory according to the storage address using the DMA controller.

[0103] For example, image processing parameters are retrieved from host memory based on the storage address via the JPU's direct memory access controller.

[0104] In this way, the DMA controller can directly interact with the host memory to read image processing parameters in batches, which can reduce CPU resource consumption and improve the efficiency of parameter reading.

[0105] In some embodiments, the storage address is received via an address register.

[0106] For example, this disclosure does not limit the name of the address register; the address register may also be called the command address register.

[0107] For example, the host sends the storage address to the JPU's address register, such as JPU_CMD_ADDR = 0xA0000000.

[0108] Optionally, step A1, which involves using a DMA controller to retrieve image processing parameters in batches from the host memory based on the storage address, may include steps A11-A12.

[0109] Step A11: Read the storage address from the address register.

[0110] Step A12: Obtain image processing parameters in batches from the host memory according to the storage address using the DMA controller.

[0111] For example, after the JPU detects the trigger signal, it reads the storage address from the address register and retrieves the image processing parameters from the host memory based on the storage address via the DMA controller. In this way, by using the address register in conjunction with the DMA controller, image processing parameters can be efficiently retrieved directly from the host memory, improving parameter loading speed and reducing host CPU usage.

[0112] In some embodiments, image processing parameters may include, but are not limited to, one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0113] Optionally, after obtaining the image processing parameters, the JPU can use its internal command parser module to send the image processing parameters to the corresponding internal modules, thereby completing the initialization process. For example, initialization parameters can be sent to the corresponding functional modules, image parameters to the image preprocessing module, quantization matrices to the quantization module, Huffman tables to the Variable Length Coding (VLC) module, and compression quality to the encoding control module.

[0114] For example, initialization parameters include, but are not limited to, one or more of the following: image processor operating mode configuration, clock configuration, interrupt configuration, and hardware reset parameters.

[0115] For example, image parameters include resolution, sampling format, and row span.

[0116] For example, a quantization matrix is ​​used to control the quantization of coefficients during image compression or decompression. The quantization matrix includes luminance and chrominance components.

[0117] For example, a Huffman table includes separate Direct Current (DC) and Alternating Current (AC) tables for the luminance and chrominance components, such as a luminance DC table, a luminance AC table, a chrominance DC table, and a chrominance AC table. Each Huffman table includes code length information and / or symbol information. The code length information indicates the number of binary bits in the Huffman code, and the symbol information indicates the original data corresponding to the Huffman code.

[0118] For example, the input buffer address indicates the storage location of the image data to be processed. The input buffer address is the physical address of the corresponding storage area allocated by the host for the luminance component, blue chrominance component, and red chrominance component.

[0119] For example, the output buffer address indicates the storage location of the processed image data. The output buffer address might be the starting address of the storage area allocated by the host for the encoded bitstream.

[0120] For example, compression quality is used to control the degree of compression and the restoration effect of image encoding.

[0121] In some embodiments, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0122] The method provided in this disclosure can be used in both image encoding and image decoding scenarios, thus improving its versatility.

[0123] In some embodiments, the method provided in this disclosure may further include: receiving a trigger signal through a start control register.

[0124] For example, the JPU receives trigger signals through its startup control register. In this way, reliable startup and process control of the JPU can be achieved by receiving trigger signals through the startup control register.

[0125] For example, the startup control register may also be called the startup (START) register or the enable (ENABLE) register, etc., and this disclosure does not limit it.

[0126] In some embodiments, the image processing parameters may include image processing parameters corresponding to multiple frames of images. The image processing parameters corresponding to each frame of images are independently encapsulated in a structured command block according to a structured format. The structured command blocks corresponding to each frame of images are stored in a contiguous address area of ​​the host memory in the order of processing of each frame of images.

[0127] For example, the technical solutions provided in this disclosure are applicable to various image formats. Taking the Joint Photographic Experts Group (JPEG) image format as an example, when preparing the JPEG encoding task on the host side, the following information is stored in the system memory in a unified structured format: initialization parameters; input image buffer address: 0x80000000; output image buffer address: 0x90000000; resolution: 1920×1080; sampling format: YUV420; quantization matrix: JPEG quantization table; Huffman table: JPEG DC / AC encoding table; other encoding parameters: compression quality 90, etc.

[0128] For example, image processing parameters are encapsulated in a structured command block according to a structured format. The JPU reads the necessary parameters and table information from the structured command block in memory according to the structured format to initialize encoding or decoding operations, without requiring the host to configure each item individually. This mechanism enables asynchronous task startup, improving hardware utilization and reducing host waiting time and CPU usage. The elimination of register configuration at each task startup simplifies host control logic. Structured format management improves parameter management efficiency, reduces error probability, and facilitates system expansion and maintenance.

[0129] Optionally, the parameters in the image processing parameters are stored in a contiguous memory area and arranged in a structured format, making it easy for the image processor to read and parse them directly.

[0130] Optionally, the host can store image processing parameters for multiple frames in batches. Each structured command block corresponds to the image processing parameters for one frame, and multiple structured command blocks are stored in a contiguous address area of ​​the host memory in the order of processing each frame.

[0131] For example, the host can prepare structured command blocks for a single frame image, or for multiple frames images or multiple tasks in parallel, making full use of the JPU's processing power to achieve high-throughput encoding or decoding.

[0132] For example, the host generates an independent structured command block for each frame of image in memory. These structured command blocks are stored in memory sequentially, such as 0xA0000000: frame 1 command block; 0xA0000100: frame 2 command block; 0xA0000200: frame 3 command block, and so on. Optionally, each structured command block can have the same length, which the JPU can directly parse without requiring the host to configure registers individually. The host configures the multi-tasking parameters by configuring the storage address and the number of tasks, such as storage address JPU_CMD_ADDR=0xA0000000 and task number JPU_QUEUE_LEN=3.

[0133] In this way, multiple structured command blocks are cached simultaneously, and the JPU executes the data processing of each frame of the image in the order of the queue. This supports high-concurrency task processing and is suitable for batch image processing scenarios, which can improve system throughput and resource utilization efficiency.

[0134] In this way, there is no need to configure registers item by item each time a task starts, which simplifies the host control logic. Structured format management improves parameter management efficiency, reduces the probability of errors, and facilitates system expansion and maintenance.

[0135] Optionally, the structured format supports flexible expansion. Adding new parameters or tables simply involves adding fields to the structured format; there's no need to modify the core code controlling the JPU on the host side, especially the software logic for configuring registers item by item. This enables a highly compatible and scalable hardware control solution.

[0136] In some embodiments, the method provided in this disclosure may further include: receiving the number of tasks from the host.

[0137] Optionally, the number of tasks is the total number of frames of the images to be processed.

[0138] For example, the JPU receives the number of tasks from the host through the JPU's task register.

[0139] Optionally, retrieving image processing parameters from host memory based on the storage address may include steps B1-B2.

[0140] Step B1: Determine the address of the structured command block corresponding to the image based on the storage address, the number of tasks, and the preset length of the structured command block.

[0141] Step B2: Obtain the image processing parameters corresponding to each frame of the image from the host memory based on the address of the structured command block corresponding to the image.

[0142] For example, multiple pre-defined structured command blocks can have the same length, some of the same length, or completely different lengths.

[0143] For example, assuming that each structured command block has the same length, the address of the structured command block corresponding to each frame of the image is calculated based on the storage address, the number of tasks, and the preset length of the structured command block.

[0144] For example, in response to receiving a trigger signal, the address of the structured command block corresponding to the image is determined based on the storage address, the number of tasks, and the preset length of the structured command block. Then, based on the address of the structured command block corresponding to the image, the image processing parameters corresponding to each frame are retrieved from the host memory. In this way, the structured command blocks of each frame can be quickly located using fixed rules, improving the efficiency of image processing parameter reading.

[0145] In some embodiments, the number of received storage addresses is multiple, and each storage address corresponds to a structured command block corresponding to a frame of image.

[0146] For example, when there are multiple frames of images to be processed, multiple storage addresses can be sent, each corresponding to a structured command block for one frame of the image, or each storage address corresponding to image processing parameters for one frame of the image. In this way, by sending multiple storage addresses, structured command blocks can be prepared for multiple frames of images or multiple tasks in parallel, achieving high-throughput encoding or decoding.

[0147] Optionally, if the image processing parameters are the same for multiple image processing tasks, the host can reuse the image processing parameters or structured command blocks already stored in memory and send the corresponding parameter storage address to the JPU.

[0148] In some embodiments, image data processing based on image processing parameters may include: reading the original YUV image data to be encoded directly from the host memory via DMA according to the input image buffer address, where Y represents luminance, and U and V represent chrominance, with chrominance defining the hue and saturation of a color; dividing the image data into blocks, such as 8×8 blocks; performing a Discrete Cosine Transform (DCT) on the 8×8 blocks, and then quantizing the values ​​after the DCT transformation using a quantization matrix; encoding the quantized values ​​using a Huffman table to obtain compressed JPEG data; writing the compressed JPEG data into the output buffer and updating the state data of the structured command block, or only updating the state data of the structured command block in case of encoding anomalies.

[0149] In this way, after receiving a trigger command, the JPU can independently complete image encoding or decoding tasks, including reading input data from memory, applying quantization matrices and Huffman tables for compression or decompression, generating output data, and storing it in a specified buffer. Throughout the process, the host computer does not need to intervene in the specific operation steps. The CPU only needs to issue an instruction to start the encoding or decoding task. While the JPU is executing the encoding task, the CPU can handle other tasks, and the two are executed in parallel to achieve asynchronous processing.

[0150] In some embodiments, step 203, which processes image data according to image processing parameters, may include step C1.

[0151] Step C1: Based on the image processing parameters corresponding to each frame, perform image data processing on each frame in a multi-stage pipeline manner.

[0152] Optionally, the image data processing for each frame includes multiple ordered stages determined according to the image processing parameters of the corresponding frame.

[0153] For example, image data processing may include stages performed in the following order: reading image data, block partitioning, DCT and quantization processing, Huffman coding, and writing to the output buffer.

[0154] Optionally, the multi-stage pipeline approach involves executing each stage of image data processing for the same frame sequentially, and executing different stages of image data processing for different frames in parallel.

[0155] The JPU employs a multi-stage pipeline architecture, with each stage independently executing its corresponding task: reading image data, block partitioning, DCT and quantization processing, Huffman coding, and writing to the output buffer. When the first frame of an image enters the second stage (e.g., block partitioning), the second frame can simultaneously enter the first stage (e.g., reading image data), thus achieving frame-level pipelined processing. This approach offers significant advantages for real-time streaming media processing and high-resolution image processing scenarios.

[0156] This can improve hardware utilization, reduce hardware idle time, enable hardware modules to work in parallel, and thus improve the overall system throughput.

[0157] In some embodiments, a structured command block may also include a status area.

[0158] For example, a structured command block may include an image processing parameter area and a status area. The image processing parameter area is used to store image processing parameters, and the status area is used to store status information.

[0159] Optionally, after processing the image data according to the image processing parameters in step 203, the method provided in this embodiment of the disclosure further includes: writing state information into the state area.

[0160] Optionally, status information is used to indicate whether image data processing was successful or failed.

[0161] For example, status information may include the execution result of the image processing task, whether there were any errors, and / or the progress of completion.

[0162] Optionally, the method provided in this disclosure further includes sending a notification signal to the host. The notification signal can be used to indicate that image data processing is complete. The timing of sending the notification signal is not limited; for example, sending the notification signal to the host can be performed after the status information is written to the status area, ensuring that the host can obtain the status information after receiving the notification signal.

[0163] For example, after the JPU completes image data processing, it sends a notification signal to the host via an interrupt or other means. The notification signal can be an interrupt request semaphore. After receiving the notification signal, the host reads the status information in the structured command block.

[0164] This disclosure introduces a status feedback mechanism. Each command block includes a status identifier field. The JPU can record the error status when an exception occurs and choose to automatically retry or skip the abnormal task. By reading the status information, the host can flexibly adjust or reissue task commands. This mechanism not only reduces system stagnation caused by the failure of a single task but also enhances the reliability and stability of the entire codec system, making it particularly suitable for real-time processing and high-reliability scenarios.

[0165] Optionally, the JPU can support single-frame interrupt mode and batch completion mode. Single-frame interrupt mode refers to sending a notification signal after processing image data for one frame. Batch completion mode refers to sending a notification signal after processing image data for multiple frames.

[0166] In single-frame interrupt mode, the JPU sends a corresponding interrupt signal to notify the host when it completes processing one frame of image data; in batch completion mode, the JPU sends an interrupt signal all at once after processing multiple frames of image data, thereby reducing the overhead of interrupts.

[0167] Please refer to Figure 3 , Figure 3 This is a flowchart of an image data processing method provided in an embodiment of the present disclosure, wherein the executing entity is a second device 102, and process 300 includes the following steps.

[0168] Step 301: Send storage address.

[0169] For example, the storage address indicates the storage location of image processing parameters in the host memory. These parameters are stored in a structured format and are used for image data processing. Specific implementation details can be provided in the parameters. Figure 2 The corresponding explanations in the methods shown will not be repeated here.

[0170] Step 302: Send a trigger signal.

[0171] For example, a trigger signal is used to indicate image data processing, and the trigger signal is used to trigger the batch retrieval of image processing parameters from the host memory according to the storage address.

[0172] The method provided in this disclosure involves the host sending a storage address and a trigger signal to enable the image processor to process image data. The host sends the image processing parameters to the image processor as a whole through the storage address, without having to write the parameters to each register of the image processor one by one. The parameter sending process does not depend on register configuration, which simplifies the parameter configuration process between the host and the image processor, improves data transmission and system response efficiency, and thus improves image processing efficiency.

[0173] In some embodiments, step 301, sending the storage address, includes writing the storage address to the address register.

[0174] For example, the host writes a memory address to the JPU's address register. Correspondingly, the JPU receives the memory address through its address register.

[0175] Optionally, step 302 sending a trigger signal includes: writing a trigger signal to the startup control register.

[0176] For example, the host writes a trigger signal to the JPU's boot control register. Correspondingly, the JPU receives the trigger signal through the boot control register.

[0177] For example, the host can trigger the JPU to start and execute a preset image processing task by triggering signals, including but not limited to interrupt signals and writing preset values ​​to the startup control register.

[0178] In this way, the host can efficiently control and configure the JPU by writing the storage address and trigger signal to the corresponding register of the JPU. The solution is simple, which simplifies the host control logic, improves the efficiency of parameter management, reduces the probability of errors, and facilitates system expansion and maintenance.

[0179] Optionally, before sending the storage address in step 301, the method provided in this embodiment may further include: writing image processing parameters into host memory.

[0180] In some embodiments, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0181] In some embodiments, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0182] In some embodiments, the image processing parameters include image processing parameters corresponding to multiple frames of images. Before sending the storage address in step 301, the method provided in this disclosure embodiment may further include steps D1-D2.

[0183] Step D1: Encapsulate the image processing parameters corresponding to each frame of the image independently in a structured command block according to a structured format.

[0184] Step D2: Store the structured command blocks corresponding to each frame of the image in a contiguous address area of ​​the host memory in the order of processing each frame of the image.

[0185] Optionally, each structured command block corresponds to the image processing parameters of one frame of image.

[0186] For example, taking the JPEG image format as an example, the host stores the following information in the system memory in a unified structured format: initialization parameters; input image buffer address: 0x80000000; output image buffer address: 0x90000000; resolution: 1920×1080; sampling format: YUV420; quantization matrix: JPEG quantization table; Huffman table: JPEG DC / AC encoding table; other encoding parameters: compression quality 90, etc.

[0187] For example, if there are multiple images to be processed, the structured command blocks corresponding to each frame can be stored in a contiguous address region of the host memory according to the processing order of each frame. For example, 0xA0000000: frame 1 command block; 0xA0000100: frame 2 command block; 0xA0000200: frame 3 command block, and so on.

[0188] In this way, encapsulating image processing parameters into structured command blocks and storing them sequentially according to the processing order of each frame of the image can simplify the parameter configuration process, improve the efficiency of parameter reading and parsing, and facilitate batch processing of multiple frames of images by hardware.

[0189] By designing structured command blocks, the host can point all task-related parameters to the JPU hardware at once and notify the JPU to start executing the image data processing task via trigger signals (such as interrupts or register writes). The JPU reads the necessary parameters and table information from memory according to the structured command format and initializes the encoding / decoding operation. This eliminates the need for the host to configure each parameter individually, enabling asynchronous task startup, improving hardware utilization, and reducing host waiting time and CPU usage.

[0190] In some embodiments, the method provided in this disclosure may further include: sending a number of tasks.

[0191] Optionally, the number of tasks is the total number of frames of the images to be processed.

[0192] For example, this embodiment does not limit the timing of the execution of the number of sending tasks. For example, the number of sending tasks and step 301 of sending the storage address can be executed simultaneously or sequentially.

[0193] In this way, the host can prepare structured command blocks for a single frame image, or for multiple frames images or multiple tasks in parallel, making full use of the JPU's processing power to achieve high-throughput encoding or decoding.

[0194] In some embodiments, there are multiple storage addresses, and each storage address corresponds to a structured command block for a frame of image.

[0195] For example, when there are multiple frames of images to be processed, multiple storage addresses can be sent, each corresponding to a structured command block for one frame of the image, or each storage address corresponding to image processing parameters for one frame of the image. In this way, by sending multiple storage addresses, structured command blocks can be prepared for multiple frames of images or multiple tasks in parallel, achieving high-throughput encoding or decoding.

[0196] Optionally, if the image processing parameters are the same for multiple image processing tasks, the host can reuse the image processing parameters or structured command blocks already stored in memory and send the corresponding parameter storage address to the JPU.

[0197] In some embodiments, the structured command block further includes a state area. After sending the trigger signal in step 302, the method provided in this disclosure embodiment further includes steps E1-E3.

[0198] Step E1: In response to receiving a notification signal, read the status information from the structured command block corresponding to the notification signal.

[0199] Optionally, status information is used to indicate whether image data processing was successful or failed.

[0200] Step E2: If the status information indicates that the image data processing has failed, send the trigger signal again.

[0201] Step E3: If the status information indicates that the image data processing was successful, obtain the processed image data.

[0202] For example, the structured command block corresponding to the notification signal can refer to the structured command of the image processing task for a certain frame / batch of images corresponding to the notification signal.

[0203] For example, after the JPU completes image data processing, it sends a notification signal to the host. After receiving the notification signal, the host reads the status information in the structured command block.

[0204] If the status information indicates that image data processing has failed, the host can send a trigger signal again, prompting the JPU to re-execute the image processing task for that frame or batch of images based on the structured command blocks already stored in memory. This enables automatic retries of image processing tasks, improving system fault tolerance and processing success rate. Alternatively, if the status information indicates that image data processing has failed, the host can also skip the abnormal task.

[0205] Optionally, if the status information indicates that image processing has failed, and the status area of ​​the structured command block contains the corresponding error code, such as a data read error code or an encoding error code, the host can skip the operation of accessing the data storage address after processing and directly locate the problem based on the error code. For example, error code 01 corresponds to a DCT processing error, and error code 02 corresponds to a Huffman encoding failure. In this way, when image data processing fails, invalid address access is skipped and the problem is directly investigated based on the error code, which can reduce redundant operations and improve the efficiency of fault location and the convenience of system debugging.

[0206] When the status information indicates that the image data processing is successful, the host reads the processed image data from the corresponding memory area according to the preset storage rules, such as the output buffer address, and performs subsequent transmission, storage or display. In this way, the processed image data can be accurately obtained based on the success status information, which can ensure the accuracy of data acquisition.

[0207] After the JPU completes the image data processing task, it notifies the host of the task completion via interrupts or other means, and updates the status information in the structured command block for the host to use. Subsequently, the host can asynchronously read the output data or subsequent processing results. Upon receiving the notification signal from the JPU, the host can autonomously choose when to read the image data in the output buffer and / or the status information in the structured command block without blocking its own core business processing. There is no need to continuously poll the hardware status during task execution. For example, after the host sends a trigger signal, it does not need to wait for the task to complete by repeatedly reading the JPU status register; instead, the JPU actively triggers the notification signal, and the host only needs to respond to the notification signal. This reduces the host's occupancy rate, improves system resource utilization, simplifies the host's software logic, and enables efficient and stable task management.

[0208] In some embodiments, after sending the trigger signal in step 302, the method provided in this disclosure may further include steps F1-F2.

[0209] Step F1: In response to determining the hardware function upgrade of the image processor, determine the configuration parameters corresponding to the hardware function upgrade.

[0210] Step F2: Based on the parameters corresponding to the image processor change and the structured format rules of the structured command block, update or expand the fields in the structured command block that correspond to the configuration parameters corresponding to the hardware function upgrade, and obtain a new structured command block.

[0211] After the hardware functions of the image processor are upgraded or changed, such as adding support for new encoding formats or improving DCT processing accuracy, the new configuration parameters required for the upgraded function are first identified, such as new encoding mode parameters and precision control parameters. Based on preset structured format rules, only the fields related to the upgraded function in the structured command block are updated or expanded to obtain a new structured command block. This adapts to the new hardware functions while retaining the original fields and logic.

[0212] In this way, without modifying the core code of the host control JPU, parameter adaptation after hardware upgrades can be completed simply by updating or expanding command block fields. This ensures system compatibility during technology iterations and standard updates, reduces system upgrade and maintenance costs, and increases the product's lifecycle value.

[0213] This disclosure proposes an asynchronous operation mechanism that triggers hardware execution of command blocks via interrupts or status flags. For example, after the host sends out a structured command block and completes the configuration, it can start other work without waiting for the JPU to complete each step. After receiving the command block, the JPU independently executes the encoding or decoding task, and the host does not need to wait for each step to complete before proceeding to the next operation, thus achieving asynchronous processing.

[0214] This disclosure, through the adoption of structured command block configuration, multi-task processing, and pipelined execution mechanisms, enables efficient collaboration between the host and the image processor, improving the performance, efficiency, reliability, and scalability of the image codec. It reduces the host load, increases JPU hardware utilization, supports asynchronous multi-task execution, and can be used for large-scale image processing.

[0215] The technical solution provided in this disclosure can improve the efficiency of image encoding and decoding processing. The parameters, quantization matrix, and Huffman table required for encoding and decoding are uniformly encapsulated into a structured command block. Combined with an asynchronous triggering mechanism, this allows the JPU to continuously execute multi-frame image tasks without needing to configure registers frame by frame, reducing hardware idle time and improving pipeline processing efficiency.

[0216] The technical solutions provided in this disclosure can reduce the host's burden and improve system resource utilization. If the host frequently accesses hardware registers and polls for status, it consumes a large amount of CPU resources. This disclosure, by employing a one-time command block configuration and interrupt notification mechanism, allows the host to receive result notifications only when the task is completed, eliminating the need for continuous hardware status monitoring. This frees up CPU resources and improves the overall system resource utilization efficiency.

[0217] The technical solution provided in this disclosure supports asynchronous and high-concurrency processing. Through a structured command block and task queue management mechanism, the JPU can process multiple tasks simultaneously without requiring the host to wait synchronously, thus enabling asynchronous execution of image encoding and decoding tasks. For batch image processing, maintaining high-concurrency processing capabilities can improve system response speed and overall performance.

[0218] The technical solutions provided in this disclosure have good scalability and ease of maintenance. By adopting a unified structured command block design, the system can adapt to new hardware by simply updating the command block generation logic when hardware changes or upgrades are made, reducing system upgrade costs, facilitating software maintenance, and enabling the image codec to adapt to technological updates and diverse application needs.

[0219] Further reference Figure 4 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of an image data processing apparatus, which corresponds to the above method embodiments, and the apparatus can be specifically applied to various electronic devices.

[0220] like Figure 4 As shown, the image data processing apparatus 400 of this embodiment may include: an address receiving module 401, a parameter acquisition module 402, and an image processing module 403. The address receiving module 401 is configured to receive a storage address from a host; wherein the storage address indicates the storage location of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format. The parameter acquisition module 402 is configured to, in response to receiving a trigger signal, acquire image processing parameters from the host memory according to the storage address; wherein the trigger signal indicates that image data processing should be performed. The image processing module 403 is configured to perform image data processing according to the image processing parameters.

[0221] In this embodiment, the specific processing of the address receiving module 401, the parameter acquisition module 402, and the image processing module 403 in the image data processing device 400 and the resulting technical effects can be referred to the relevant descriptions of the above method embodiments, and will not be repeated here.

[0222] In one possible implementation, the parameter acquisition module 402 is further configured to acquire image processing parameters from host memory based on a storage address via a direct memory access (DMA) controller.

[0223] In one possible implementation, the storage address is received via an address register; the parameter acquisition module 402 is also configured to: read the storage address from the address register; and acquire image processing parameters from the host memory based on the storage address via the DMA controller.

[0224] In one possible implementation, the image data processing apparatus 400 further includes a signal receiving module. The signal receiving module is configured to receive a trigger signal via a start control register.

[0225] In one possible implementation, the image processing parameters may include image processing parameters corresponding to multiple frames of images. The image processing parameters corresponding to each frame of images are independently encapsulated in a structured command block according to a structured format. The structured command blocks corresponding to each frame of images are stored in a contiguous address area of ​​the host memory in the order of processing of each frame of images.

[0226] In one possible implementation, the image processing module 403 is further configured to: perform image data processing on each frame of image according to the image processing parameters corresponding to each frame of image in a multi-stage pipeline manner; wherein, the image data processing of each frame of image includes: multiple ordered stages determined according to the image processing parameters of the corresponding frame; the multi-stage pipeline manner is to execute each stage of image data processing of the same frame of image in a stage-sequential manner, and to execute different stages of image data processing of different frames of image in parallel.

[0227] In one possible implementation, the image data processing apparatus 400 further includes a task receiving module. The task receiving module is configured to receive a number of tasks from the host; wherein the number of tasks is the total number of frames of the image to be processed. The parameter acquisition module 402 is further configured to: determine the address of the structured command block corresponding to the image based on the storage address, the number of tasks, and the preset length of the structured command block; and acquire the image processing parameters corresponding to each frame of the image from the host memory based on the address of the structured command block corresponding to the image.

[0228] In one possible implementation, the number of received storage addresses is multiple, and each storage address corresponds to a structured command block corresponding to a frame of image.

[0229] In one possible implementation, the structured command block further includes a status area; wherein, the image data processing apparatus 400 further includes a status writing module. The status writing module is configured to write status information into the status area; wherein the status information is used to indicate whether the image data processing was successful or failed.

[0230] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0231] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0232] This embodiment exists as a device embodiment corresponding to the above method embodiment. The technical effects brought about by the image data processing device 400 provided in this embodiment can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0233] Further reference Figure 5 As an implementation of the methods shown in the above figures, this disclosure provides another embodiment of an image data processing apparatus, which corresponds to the above method embodiments, and the apparatus can be specifically applied to various electronic devices.

[0234] like Figure 5 As shown, the image data processing apparatus 500 of this embodiment may include: a first sending module 501 and a second sending module 502. The first sending module 501 is configured to send a storage address; wherein the storage address is used to indicate the storage location of image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format. The second sending module 502 is configured to send a trigger signal; wherein the trigger signal is used to indicate that image data processing is to be performed.

[0235] In this embodiment, the specific processing of the first sending module 501 and the second sending module 502 in the image data processing device 500 and the resulting technical effects can be referred to the relevant descriptions of the above method embodiments, and will not be repeated here.

[0236] In one possible implementation, the first sending module 501 is further configured to write a storage address to the address register; the second sending module 502 is further configured to write a trigger signal to the start control register.

[0237] In one possible implementation, the image processing parameters include image processing parameters corresponding to multiple frames of images. The image data processing apparatus 500 may further include an encapsulation module and a storage module. The encapsulation module is configured to independently encapsulate the image processing parameters corresponding to each frame of image in a structured command block according to a structured format. The storage module is configured to store the structured command blocks corresponding to each frame of image in a contiguous address region of the host memory according to the processing order of each frame of image.

[0238] In one possible implementation, the image data processing apparatus 500 may further include a third sending module. The first sending module 501 is configured to send a number of tasks; wherein the number of tasks is the total number of frames of the image to be processed.

[0239] In one possible implementation, there are multiple storage addresses, each storage address corresponding to a structured command block for a frame of image.

[0240] In one possible implementation, the structured command block further includes a status area; the image data processing apparatus 500 may also include a reading module and an acquisition module. The reading module is configured to: in response to receiving a notification signal, read status information from the structured command block corresponding to the notification signal; wherein the status information is used to indicate whether image data processing was successful or failed. The acquisition module is configured to: acquire the processed image data if the status information indicates that image data processing was successful. The second sending module 502 is further configured to: resend the trigger signal if the status information indicates that image data processing failed.

[0241] In one possible implementation, after sending the trigger signal, the image data processing apparatus 500 may further include a determination module and a command block update module. The determination module is configured to: in response to determining a hardware function upgrade of the image processor, determine the configuration parameters corresponding to the hardware function upgrade. The command block update module is configured to: based on the parameters corresponding to the image processor change and the structured format rules of the structured command block, update or expand the fields in the structured command block corresponding to the configuration parameters corresponding to the hardware function upgrade, to obtain a new structured command block.

[0242] In one possible implementation, the image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

[0243] In one possible implementation, the image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

[0244] This embodiment exists as a device embodiment corresponding to the above method embodiment. The technical effects brought about by the image data processing device 500 provided in this embodiment can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0245] This disclosure provides an image data processing system, including an image processor and a host. The image processor is configured to implement any of the methods described in the first device above. The host is configured to implement any of the methods described in the second device above.

[0246] This disclosure also provides a chip including a processor that can be used to implement any of the possible implementations of the methods provided in this disclosure. For example, the processor may be a CPU or a JPU.

[0247] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored in the memory. For example, the processor may be a CPU or a JPU.

[0248] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the described method. The computer-readable storage medium can be volatile or non-volatile.

[0249] This disclosure also provides a computer program product that, when executed by a processor, can implement the methods described in any of the above embodiments.

[0250] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device may be a first device, a second device, etc. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0251] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 6 As shown, the electronic device 600 of this embodiment includes a processor 601 and may further include a memory 602; wherein the memory 602 is used to store computer execution instructions; and the processor 601 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the first device or the second device in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.

[0252] Alternatively, the memory 602 can be either standalone or integrated with the processor 601.

[0253] When the memory 602 is set up independently, the electronic device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0254] It should be understood that the processor 601 described above can be a CPU or a JPU, etc. The steps of the method disclosed in the invention can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.

[0255] The memory 602 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0256] Bus 603 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0257] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0258] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0259] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0260] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include front-end components, or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0261] According to the technical solution of this disclosure embodiment, the storage address of image processing parameters in the host memory is received. The image processing parameters are stored in the host memory in a structured format. In response to receiving a trigger signal, the image processing parameters are obtained from the host memory according to the storage address. In this way, the image processor obtains the image processing parameters sent by the host through the storage address, without having to obtain the parameters from each register one by one. The parameter configuration process is simple and can improve the image processing efficiency.

[0262] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0263] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An image data processing method, comprising: Receive a storage address from the host; wherein the storage address is used to indicate the storage location of the image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; In response to receiving a trigger signal, the image processing parameters are retrieved in batches from the host memory according to the storage address; wherein the trigger signal is used to indicate image data processing. Image data processing is performed according to the image processing parameters.

2. The method according to claim 1, wherein, The image processing parameters are retrieved in batches from the host memory according to the storage address, including: The image processing parameters are retrieved in batches from the host memory according to the storage address via the Direct Memory Access (DMA) controller.

3. The method according to claim 2, wherein, The storage address is received through the address register; The step of obtaining the image processing parameters in batches from the host memory according to the storage address via the Direct Memory Access (DMA) controller includes: Read the storage address from the address register; The image processing parameters are retrieved in batches from the host memory using the DMA controller based on the storage address.

4. The method according to claim 3, wherein, The method further includes: The trigger signal is received by starting the control register.

5. The method according to any one of claims 1-4, wherein, The image processing parameters include image processing parameters corresponding to multiple frames of images. The image processing parameters corresponding to each frame of images are independently encapsulated in a structured command block according to a structured format. The structured command blocks corresponding to each frame of images are stored in a continuous address area of ​​the host memory according to the processing order of each frame of images.

6. The method according to claim 5, wherein, The image data processing according to the image processing parameters includes: Based on the image processing parameters corresponding to each frame, image data processing is performed on each frame in a multi-stage pipeline manner; wherein, the image data processing of each frame includes: multiple ordered stages determined according to the image processing parameters of the corresponding frame; the multi-stage pipeline manner is to execute each stage of image data processing of the same frame in a stage-sequential manner, and to execute different stages of image data processing of different frames in parallel.

7. The method according to claim 5, wherein, The method further includes: receiving a number of tasks from the host; wherein the number of tasks is the total number of frames of the image to be processed; The process of batch retrieving the image processing parameters from the host memory according to the storage address includes: The address of the structured command block corresponding to the image is determined based on the storage address, the number of tasks, and the preset length of the structured command block; Based on the address of the structured command block corresponding to the image, the image processing parameters corresponding to each frame of the image are retrieved in batches from the host memory.

8. The method according to claim 6, wherein, The number of received storage addresses is multiple, and each storage address corresponds to a structured command block corresponding to a frame of image.

9. The method according to claim 5, wherein, The structured command block also includes a status area; The method further includes, after processing the image data according to the image processing parameters: Status information is written into the status area; wherein, the status information is used to indicate whether the image data processing was successful or failed.

10. The method according to any one of claims 1-4, wherein, The image processing parameters include configuration parameters for image data encoding, or the image processing parameters include configuration parameters for image data decoding.

11. The method according to any one of claims 1-4, wherein, The image processing parameters include one or more of the following: initialization parameters, image parameters, quantization matrix, Huffman table, input buffer address, output buffer address, and compression quality.

12. An image data processing method, comprising: Send storage address; wherein, the storage address is used to indicate the storage location of image processing parameters in host memory, and the image processing parameters are stored in host memory in a structured format; Send a trigger signal; wherein the trigger signal is used to indicate image data processing, and the trigger signal is used to trigger the batch retrieval of the image processing parameters from the host memory according to the storage address.

13. The method according to claim 12, wherein, The image processing parameters include image processing parameters corresponding to multiple frames of images. Before sending the storage address, the method further includes: The image processing parameters corresponding to each frame are independently encapsulated in a structured command block in a structured format; The structured command blocks corresponding to each frame of the image are stored in a contiguous address region of the host memory in the order of processing each frame of the image.

14. The method according to claim 13, wherein, The structured command block further includes a status area; after sending the trigger signal, the method further includes: In response to receiving a notification signal, status information is read from the structured command block corresponding to the notification signal; wherein the status information is used to indicate whether the image data processing was successful or failed. If the status information indicates that the image data processing was successful, the processed image data is acquired; If the status information indicates that image data processing has failed, the trigger signal is sent again.

15. The method according to claim 13 or 14, wherein, After sending the trigger signal, the method further includes: In response to determining that the image processor has undergone a hardware function upgrade, the configuration parameters corresponding to the hardware function upgrade are determined; Based on the parameters corresponding to the image processor change and the structured format rules of the structured command block, the fields corresponding to the configuration parameters corresponding to the hardware function upgrade in the structured command block are updated or expanded to obtain a new structured command block.

16. An image data processing apparatus, comprising: The address receiving module is configured to receive a storage address from the host; wherein the storage address is used to indicate the storage location of the image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; The parameter acquisition module is configured to, in response to receiving a trigger signal, acquire the image processing parameters in batches from the host memory according to the storage address; wherein the trigger signal is used to indicate image data processing. The image processing module is configured to process image data according to the image processing parameters.

17. An image data processing apparatus, comprising: The first sending module is configured to send a storage address; wherein, the storage address is used to indicate the storage location of the image processing parameters in the host memory, and the image processing parameters are stored in the host memory in a structured format; The second sending module is configured to send a trigger signal; wherein the trigger signal is used to indicate image data processing, and the trigger signal is used to trigger the batch acquisition of the image processing parameters from the host memory according to the storage address.

18. An image data processing system, comprising: An image processor is configured to implement the method of any one of claims 1-11; The host is configured to implement the method of any one of claims 12-15.

19. An electronic device comprising: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 15 when executing instructions stored in the memory.

20. A chip comprising a processor for performing the method of any one of claims 1 to 15.

21. A non-volatile computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the method of any one of claims 1 to 15.

22. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 15.

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