Semiconductor memory device

Abstract

A semiconductor memory device includes a bit line extending in a horizontal direction, a contact plug, a contact isolation insulating layer surrounding the contact plug, the contact isolation insulating layer including a main isolation insulating layer and a sub isolation insulating layer disposed between a portion of the contact plug and the main isolation insulating layer, wherein a stepped shape is formed in the contact isolation insulating layer between an upper portion of the contact isolation insulating layer and a lower portion of the contact isolation insulating layer, a trench pattern disposed between the bit line and the contact plug and extending in a vertical direction, and a capacitor connected to the contact plug.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0177909, filed on December 3, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device including a vertical channel transistor. Background Technology

[0003] Because semiconductor memory devices are highly integrated, the semiconductor devices included in semiconductor memory devices are being highly integrated. Therefore, in order to achieve highly integrated semiconductor devices, vertical channel transistors formed vertically on semiconductor substrates have been introduced, instead of planar channel transistors formed one-dimensionally on semiconductor substrates. Summary of the Invention

[0004] Various aspects of the present invention provide a semiconductor memory device including a vertical channel transistor with enhanced operational reliability.

[0005] A semiconductor memory device according to an embodiment includes: a bit line extending in a horizontal direction; a contact plug; a contact isolation insulating layer surrounding the contact plug, the contact isolation insulating layer including a main isolation insulating layer and a sub-isolation insulating layer disposed between a portion of the contact plug and the main isolation insulating layer, wherein a stepped shape is formed in the contact isolation insulating layer between an upper portion and a lower portion of the contact isolation insulating layer; a channel pattern disposed between the bit line and the contact plug and extending in a vertical direction; and a capacitor connected to the contact plug.

[0006] A semiconductor memory device according to an embodiment includes: a bit line extending in a first horizontal direction; a word line extending on the bit line in a second horizontal direction different from the first horizontal direction; a back gate electrode extending on the bit line in the second horizontal direction and disposed separately from the word line in the first horizontal direction; a contact plug on the word line and the back gate electrode, wherein a first conductive pattern and a second conductive pattern comprising a semiconductor material and a third conductive pattern and a fourth conductive pattern comprising a metal base material are sequentially stacked in the contact plug; a contact isolation insulating layer surrounding the contact plug on the word line and the back gate electrode, and including a lower portion and an upper portion, the lower portion having a [missing information] in the first horizontal direction. A first minimum horizontal width, the upper portion having a second minimum horizontal width greater than the first minimum horizontal width in a first horizontal direction; a channel pattern including a first end connected to a bit line and a second end opposite to a first conductive pattern connected to a contact plug, and extending in a vertical direction, the channel pattern being disposed between the word line and the back gate electrode; and a capacitor including a lower electrode connected to a fourth conductive pattern of the contact plug, an upper electrode on the lower electrode, and a capacitor dielectric pattern disposed between the lower electrode and the upper electrode, wherein the boundary between the lower and upper portions of the contact isolation insulating layer is disposed vertically below the upper surface of the third conductive pattern and above the lower surface of the third conductive pattern.

[0007] A semiconductor memory device according to an embodiment includes: a bit line extending in a first horizontal direction; a plurality of contact plugs, each of which includes a first conductive pattern and a second conductive pattern of semiconductor material and a third conductive pattern and a fourth conductive pattern of metal base material, stacked sequentially; a plurality of channel patterns, each channel pattern disposed between a corresponding first conductive pattern of a corresponding bit line and a corresponding one of the plurality of contact plugs and extending in a vertical direction; a plurality of word lines and a plurality of back gate electrodes, the plurality of word lines and the plurality of back gate electrodes extending in a second horizontal direction perpendicular to the first horizontal direction between the bit lines and the plurality of contact plugs and disposed separately from each other, having a plurality of channel patterns between the plurality of word lines and the plurality of back gate electrodes; a contact isolation insulating layer surrounding the plurality of contact plugs on the plurality of channel patterns, the plurality of word lines and the plurality of back gate electrodes, the contact isolation insulating layer including a main isolation insulating layer and a plurality of sub-isolation insulating layers, wherein the main isolation insulating layer includes a main isolation insulating layer and a plurality of sub-isolation insulating layers. The insulating layer includes a plurality of first portions and a plurality of second portions, each first portion being at a first height above a bit line and having a first minimum horizontal width in a first horizontal direction between two adjacent channel patterns, each second portion being at a second height above a bit line and below the first height and having a second minimum horizontal width greater than the first minimum horizontal width between two adjacent channel patterns, each second portion being on a corresponding first portion, and a plurality of sub-insulating layers being disposed between an upper partial portion of each of the plurality of contact plugs and a second portion of the main insulating layer; and a plurality of capacitors including a plurality of lower electrodes respectively connected to a fourth conductive pattern of the plurality of contact plugs, upper electrodes on the plurality of lower electrodes, and a capacitor dielectric layer disposed between the plurality of lower electrodes and the upper electrodes, wherein the plurality of sub-insulating layers contact an upper partial portion of a third conductive pattern and a fourth conductive pattern of each of the plurality of contact plugs. Attached Figure Description

[0008] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of a semiconductor memory device according to an embodiment; Figure 2 This is a schematic perspective view of a semiconductor memory device according to an embodiment; Figure 3A and Figure 3B These are cross-sectional and plan views of a semiconductor memory device according to an embodiment; Figures 4A to 4H This is a cross-sectional view used to describe a method of manufacturing a semiconductor memory device according to an embodiment; Figures 5A to 5D This is a cross-sectional view of a semiconductor memory device according to an embodiment; Figure 6A and Figure 6BThese are cross-sectional and plan views of a semiconductor memory device according to an embodiment; Figure 7A and Figure 7B These are cross-sectional and plan views of a semiconductor memory device according to an embodiment; Figure 8 This is a schematic perspective view of a semiconductor memory device according to an embodiment; Figure 9 This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 10 This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 11 This is a schematic perspective view of a semiconductor memory device according to an embodiment; and Figure 12A and Figure 12B This is a cross-sectional view showing a semiconductor memory device according to an embodiment. Detailed Implementation

[0009] In the following description, embodiments of exemplary examples will be illustrated with reference to the accompanying drawings. As can be seen, for example, in the drawings, items described herein in a singular form may be provided in a plural form. Therefore, unless the context otherwise requires, a description of a single item provided in a plural form should be understood to apply to the remaining multiple items.

[0010] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it will be understood that, unless the context otherwise indicates, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component. On the other hand, the term “composed of” indicates that the component is formed solely by the listed element(s).

[0011] For ease of description, spatial relative terms such as “below,” “lower,” “lower part,” “above,” “top,” “bottom,” etc., are used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s) or feature(s). It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” other elements or features will be oriented “above” that other element or feature. Therefore, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0012] Ordinal numbers such as "first," "second," and "third" can be simply used as markers for certain elements, steps, etc., to distinguish them from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first") in a particular claim may be described elsewhere in the specification or another claim using a different ordinal number (e.g., "second").

[0013] As used herein, when referring to orientation, layout, location, shape, size, composition, quantity, or other measures, terms such as “identical,” “equal,” “planar,” or “coplanar” do not necessarily refer to identical orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures within typical variables that may occur due to conventional manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” may be identical, equal, or planar, or may be identical, equal, or planar within acceptable variables that may occur, for example, due to manufacturing processes.

[0014] It will be understood that when an element is referred to as “connected” or “coupled” to another element or “on another element,” it may be directly connected or coupled to that other element or directly on that other element, or there may be an intermediate element. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, or referred to as “in contact with another element” or “in contact with another element” (or any form of using the word “in contact”), there is no intermediate element at the point of contact.

[0015] The thickness of a layer can refer to its dimension in a direction perpendicular to the surface of the layer. The direction perpendicular to the surface can refer to its average orientation and does not include minute unintentional deviations (e.g., pits) that may form during the manufacturing process.

[0016] An item, layer, or part of an item or layer is described as extending "longitudinally" in a particular direction, having a length in that particular direction and a width in a direction perpendicular to that direction, wherein the length is greater than the width.

[0017] Figure 1 This is a block diagram of a semiconductor memory device 1000 according to an embodiment.

[0018] Reference Figure 1 The semiconductor memory device 1000 may include a memory cell array 1010, a row decoder 1020, a sense amplifier 1030, a column decoder 1040, and control logic 1050.

[0019] The memory cell array 1010 may include a plurality of memory cells MC arranged in two or three dimensions. Each of the memory cells MC may be connected between word lines WL and bit lines BL that intersect or cross each other.

[0020] Each memory cell MC may include a select element TR and a data storage element DS, and the select element TR and the data storage element DS may be electrically connected in series with each other. The select element TR may be connected between the data storage element DS and the word line WL, and the data storage element DS may be connected to the bit line BL via the select element TR. The select element TR may be a field-effect transistor (FET). In some embodiments, the select element TR may be... Figure 3A The vertical channel transistor (CTR) shown is illustrated, but not limited to this. In some embodiments, the data storage element (DS) may be... Figure 3A The capacitor 150 shown is not limited to this. In some other embodiments, the data storage element DS can be a variable resistor pattern that can be switched between two resistance states by an electrical pulse applied to the storage element. For example, the data storage element DS can include a phase change material whose crystallization state changes based on the amount of current, such as a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0021] The data storage element DS can be implemented as a magnetic tunnel junction pattern or a variable resistor. For example, the selection element TR may include a transistor, the gate electrode of which may be connected to the word line WL, and the source / drain terminals of which may be connected to the bit line BL and the data storage element DS, respectively.

[0022] The row decoder 1020 can decode an externally input address to select a word line WL from the word lines WL of the memory cell array 1010. The address decoded by the row decoder 1020 can be provided to a sub-word line driver, and the sub-word line driver can provide a specific voltage to each of the selected word line WL and the unselected word line WL in response to control by the control circuitry.

[0023] The sense amplifier 1030 can sense and amplify the voltage difference between the reference bit line and the bit line BL selected based on the address decoded by the column decoder 1040 to output the amplified voltage difference.

[0024] The column decoder 1040 provides a data transfer path between the sense amplifier 1030 and an external device (e.g., a memory controller). The column decoder 1040 can decode an address input from an external source to select a bit line BL from the bit lines BL.

[0025] Control logic 1050 can generate control signals that control the operation of writing data to or reading data from memory cell array 1010.

[0026] Figure 2 This is a schematic perspective view of a semiconductor memory device 1000 according to an embodiment.

[0027] Reference Figure 2 The semiconductor memory device 1000 may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS, wherein the peripheral circuit structure PS includes a peripheral circuit substrate PSUB. The cell array structure CS may be bonded to the peripheral circuit structure PS to be stacked on the peripheral circuit structure PS.

[0028] The peripheral circuit structure PS may include core and peripheral circuitry formed on the peripheral circuitry substrate PSUB. The core and peripheral circuitry may include their respective references. Figure 1 The row decoder 1020, the sense amplifier 1030, the column decoder 1040, and the control logic 1050 described above. Figure 2 The diagram shows the decoder and sense amplifier, respectively, included in the peripheral circuit structure PS within the core and peripheral circuitry. Figure 2 The diagram shows a peripheral circuit substrate PSUB positioned opposite the cell array structure CS in the vertical direction (Z direction) within the peripheral circuit structure PS; however, the inventive concept is not limited thereto. In some embodiments, the peripheral circuit substrate PSUB may be disposed on the side of the peripheral circuit structure PS facing the cell array structure CS in the vertical direction (Z direction).

[0029] A cell array structure CS may include bit lines BL, word lines WL, and memory cells MC between them. The memory cells MC may be arranged two-dimensionally or three-dimensionally on planes extending along a first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect each other to form a memory cell array. Figure 1 (1010). The bit line BL may extend in a first horizontal direction (X direction), and the word line WL may extend in a second horizontal direction (Y direction). Each of the memory cells MC may include a select element TR and a data storage element DS.

[0030] In some embodiments, the selection element TR for each memory cell MC may include a vertical channel transistor (VCT). Figure 3A CTR). Vertical channel transistor (CTR). Figure 3A The CTR (channel length) may have a structure in which the channel length extends in the vertical direction (Z direction). In some embodiments, the data storage element DS of each memory cell MC may be a capacitor.

[0031] Figure 3A and Figure 3B These are cross-sectional and plan views showing a semiconductor memory device 100 according to an embodiment. In detail, Figure 3A It is along Figure 3B The cross-sectional view taken from line IIIA-IIIA', and Figure 3B It shows that each of them is in Figure 3A The plan view of the fourth conductive pattern 138 and the contact insulating layer 140 is shown in the figure.

[0032] Reference Figure 3A and Figure 3B The semiconductor memory device 100 may include a memory cell array structure (MCA) in which a plurality of memory cells are disposed. For example, the plurality of memory cells may include a plurality of vertical channel transistors (CTRs). The memory cell structure MCA may be constructed by stacking bit line structures (BLSTs), channel structures (CHSTs), and capacitor structures (CTSTs). The peripheral circuit structure (PRST) may include a peripheral circuit transistor (PTR) constructed from a circuit gate structure (210). In some embodiments, the semiconductor memory device 100 may have a peripheral upper cell (CoP) structure in which the memory cell array structure (MCA) and the peripheral circuit structure (PRST) overlap each other in the vertical direction (Z direction). For example, the peripheral circuit transistor (PTR) constructed from the circuit gate structure (210) may be configured to transmit signals and / or power to the plurality of memory cells included in the memory cell array structure (MCA). For example, the peripheral circuit transistor (PTR) constructed from the circuit gate structure (210) may construct various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output (I / O) circuits. In some embodiments, the semiconductor memory device 100 may include a peripheral circuit region surrounding the memory cell array structure MCA at a one-dimensional angle, excluding the peripheral circuit structure PRST. The peripheral circuit region may be a region in which a peripheral circuit transistor PTR constructed of a circuit gate structure 210 is disposed.

[0033] In some embodiments, in a semiconductor memory device 100, a bit line structure BLST, a channel structure CHST, and a capacitor structure CTST may be sequentially stacked on a peripheral circuit structure PRST in the vertical direction (Z direction).

[0034] The bit line structure BLST may include multiple bit lines BL and an interlayer insulating layer OBL surrounding the multiple bit lines BL. According to an embodiment, the multiple bit lines BL may extend longitudinally in a first horizontal direction (X direction) and may be arranged repeatedly and separately from each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). In some embodiments, the multiple bit lines BL may be separated from each other in the second horizontal direction (Y direction) with the interlayer insulating layer OBL located therebetween. The interlayer insulating layer OBL may fill all the space between the multiple bit lines BL and may cover the lower portion (e.g., lower surface) of the multiple bit lines BL. In some embodiments, multiple insulating capping lines BLCP may cover the lower surface of the multiple bit lines BL, and the interlayer insulating layer OBL may fill all the space between the multiple bit lines BL and the multiple insulating capping lines BLCP and may cover the lower portion of the multiple insulating capping lines BLCP. In some embodiments, each of the multiple bit lines BL may have a stacked structure of a first line pattern, a second line pattern, and a third line pattern. For example, the first line pattern may include a semiconductor material, and each of the second and third line patterns may include a metal-based material. The second and third line patterns may include different types of metal-based materials. For example, the first line pattern may include doped polycrystalline silicon. For example, the second line pattern may include titanium nitride (TiN) or titanium silicon nitride (Ti-Si-N) (TSN), and the third line pattern may include tungsten (W) or tungsten silicide (WSi). x In some embodiments, the second line pattern may perform a diffusion barrier function. An insulating capping line (BLCP) may be disposed on a third line pattern. The first line pattern, second line pattern, third line pattern, and insulating capping line (BLCP) may be sequentially disposed on a channel pattern (CHL). Figure 3A The diagram shows a first line pattern, a second line pattern, a third line pattern, and an insulating capping line (BLCP) sequentially arranged below the channel pattern (CHL), but the inventive concept is not limited thereto. For example, in Figure 10 and Figure 12B In the bit line BL shown, the first line pattern, the second line pattern, the third line pattern, and the insulating capping line BLCP may be sequentially arranged above the channel pattern CHL. The interlayer insulating layer OBL may include silicon oxide, silicon nitride, or a combination thereof. Each of the multiple insulating capping lines BLCP may include silicon nitride.

[0035] The channel structure CHST may include multiple channel patterns CHL, multiple back gate electrodes BG, and multiple word lines WL. Each of the multiple channel patterns CHL may extend in a vertical direction (Z direction). Each of the multiple back gate electrodes BG and multiple word lines WL may extend longitudinally in a second horizontal direction (Y direction).

[0036] According to an embodiment, multiple channel patterns CHL can be arranged repeatedly and separately on multiple bit lines BL along a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the uppermost multiple channel patterns CHL may include a first end and a second end opposite to each other in the vertical direction (Z direction). Figure 3A In this embodiment, each of the plurality of channel patterns CHL is shown as including a vertically extending portion extending in a vertical direction (Z direction), but the embodiments are not limited thereto. In some embodiments, the plurality of channel patterns CHL may include a horizontally extending portion extending from one end of the vertically extending portion along a first horizontal direction (X direction). In some embodiments, the horizontally extending portion of the plurality of channel patterns CHL may be located at a first end. Alternatively, in some embodiments, the horizontally extending portion of the plurality of channel patterns CHL may be located at a second end. In each of the plurality of channel patterns CHL, the first end may be connected to one contact plug 130 selected from a plurality of contact plugs 130, and the second end may be connected to one bit line BL selected from a plurality of bit lines BL. In some embodiments, the channel pattern CHL may include conductive regions, such as doped wells or doped structures. Although not shown, impurity regions serving as source / drain regions may be formed in each of the first and second ends.

[0037] In some embodiments, each of the plurality of channel pattern CHLs may include or be a semiconductor material. For example, each of the plurality of channel pattern CHLs may include or be monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, each of the plurality of channel pattern CHLs may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some other embodiments, each of the plurality of channel pattern CHLs may include an oxide semiconductor material. Each of the plurality of channel pattern CHLs may include at least one of a binary or ternary oxide semiconductor material comprising a first metal element, a ternary oxide semiconductor material comprising different first and second metal elements, and a quaternary oxide semiconductor material comprising different first, second, and third metal elements.

[0038] Binary or ternary oxide semiconductor materials can be, for example, ZnO (zinc oxide, Zn). x O), GaO (gallium oxide, Ga x O), TiO (titanium oxide, Ti x O), ZnON (zinc oxide, Zn) x O y N), IZO (indium zinc oxide, In) x Zn yO), GZO (zinc gallium oxide, Ga) x Zn y O), TZO (zinc tin oxide, Sn) x Zn y O) and TGO (tin gallium oxide, Sn) x Ga y The quaternary oxide semiconductor material can be one of, but is not limited to, IGZO (indium gallium zinc oxide). x Ga Y Zn z O), IGSO (indium gallium silicon oxide, In) x Ga y Si z O), ITZO (indium tin zinc oxide, In) x Sn y Zn z O), IGTO (indium gallium tin oxide, In x Ga y Sn z O), ZZTO (zirconium zinc tin oxide, Zr x Zn y Sn z O), HIZO (hafnium indium zinc oxide, Hf) x In y Zn z O), GZTO (gallium zinc tin oxide, Ga x Zn y Sn z O), AZTO (aluminum zinc tin oxide, Al) x Zn y Sn z O), YGZO (ytterbium gallium zinc oxide, Yb x Ga y Zn z It is one of (O) and IAZO (indium aluminum zinc oxide), but not limited to this.

[0039] In some embodiments, each of the plurality of channel pattern CHLs may include a crystalline oxide semiconductor material or an amorphous oxide semiconductor material. When each of the plurality of channel pattern CHLs includes an oxide semiconductor material, each of the plurality of channel pattern CHLs may have at least one of single crystal, polycrystalline, spinel, and c-axis aligned crystal (CAAC). In some embodiments, each of the plurality of channel pattern CHLs may be constructed by stacking at least two layers, the at least two layers including a first layer comprising a crystalline oxide semiconductor material and a second layer comprising an amorphous oxide semiconductor material. For example, each of the plurality of channel pattern CHLs may be constructed by sequentially stacking a first layer comprising a crystalline oxide semiconductor material, a second layer comprising an amorphous oxide semiconductor material, and a third layer comprising a crystalline oxide semiconductor material.

[0040] Each of the plurality of back gate electrodes BG and the plurality of word lines WL may extend longitudinally in a second horizontal direction (Y direction) at a vertical height between the plurality of bit lines BL and the plurality of contact plugs 130. The plurality of back gate electrodes BG and the plurality of word lines WL may be separated from each other in a first horizontal direction (X direction). According to an embodiment, each of the plurality of channel patterns CHL may be disposed on a corresponding bit line BL of the plurality of bit lines between a back gate electrode BG and a word line WL adjacent to each other in the first horizontal direction (X direction). For example, each of the plurality of channel patterns CHL may face a gate electrode BG on one side in the first horizontal direction (X direction) and a word line WL on the other side. In some embodiments, a back gate electrode BG and a pair of word lines WL may be alternately arranged between consecutive pairs of channel patterns CHL adjacent to each other in the first horizontal direction (X direction). According to an embodiment, a pair of channel patterns CHL can be disposed on both sides (e.g., opposite sides) of each of a plurality of back gate electrodes BG in a first horizontal direction (X direction), and a pair of word lines WL can be disposed separated from a first adjacent corresponding back gate electrode BG among the plurality of back gate electrodes BG, with a first channel pattern CHL between the pair of word lines WL and the first adjacent corresponding back gate electrode BG, and the pair of word lines WL can be disposed separated from a second adjacent corresponding back gate electrode BG among the plurality of back gate electrodes BG, with a second channel pattern CHL between the pair of word lines WL and the second adjacent corresponding back gate electrode BG. For example, a channel pattern CHL, a pair of word lines WL, and another channel pattern CHL can be sequentially disposed in the back gate electrodes BG between a pair of back gate electrodes BG that are adjacent to each other in the first horizontal direction (X direction) along the first horizontal direction (X direction). A pair of word lines WL between two adjacent channel patterns CHL in the first horizontal direction (X direction) can be separated from each other in the first horizontal direction (X direction), and there is an insulating pattern 124 between the pair of word lines WL.

[0041] In some embodiments, each of the plurality of back gate electrodes BG may include a metal, a conductive metal nitride, doped polysilicon, or a combination thereof, or be formed of a metal, a conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of back gate electrodes BG may include or may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), doped polysilicon, or a combination thereof, but is not limited thereto. Each of the plurality of word lines WL may include a metal, a conductive metal nitride, doped polysilicon, or a combination thereof, or be formed of a metal, a conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of word lines WL may include or may be Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof, but is not limited thereto.

[0042] The channel structure CHST may include a plurality of back gate dielectric layers 112 that respectively cover two (e.g., opposite) sidewalls of each of a plurality of back gate electrodes BG in a first horizontal direction (X direction). Each of the plurality of back gate dielectric layers 112 may be disposed between a back gate electrode BG and an adjacent channel pattern CHL. For example, each of the plurality of back gate dielectric layers 112 may contact the corresponding back gate electrode BG and the corresponding channel pattern CHL. Figure 3A The diagram shows a back gate dielectric layer 112 disposed between the back gate electrode BG and the bit lines BL, but the inventive concept is not limited thereto. For example, an insulating pattern may also be disposed between the back gate electrode BG and the bit lines BL. The back gate electrode BG may be separated from multiple bit lines BL in the vertical direction (Z direction), with the back gate dielectric layer 112 and / or insulating pattern between the back gate electrode BG and the multiple bit lines BL. In some embodiments, a capping insulating pattern 116 may be disposed between the back gate electrode BG and multiple contact plugs 130. In some embodiments, the capping insulating pattern 116 and the back gate electrode BG may be configured to overlap each other in the vertical direction (Z direction), and each of the two sidewalls of each of the capping insulating pattern 116 and the back gate electrode BG in a first horizontal direction (X direction) may contact and be covered by the back gate dielectric layer 112. The back gate electrode BG may be separated from a plurality of contact plugs 130 in a vertical direction (Z direction), and a capping insulating pattern 116 is provided between the back gate electrode BG and the plurality of contact plugs 130. In some embodiments, the capping insulating pattern 116 may comprise silicon oxide, silicon nitride, or a combination thereof, or be formed of silicon oxide, silicon nitride, or a combination thereof.

[0043] The channel structure CHST may include a plurality of gate dielectric layers 122 disposed between a plurality of word lines WL and a plurality of adjacent channel patterns CHL. A pair of gate dielectric layers 122 may be disposed between a pair of channel patterns CHL, which are separated from each other by an insulating pattern 124 therebetween and are adjacent to each other in a first horizontal direction (X direction). A pair of word lines WL may be disposed between a pair of gate dielectric layers 122. Each of the pair of gate dielectric layers 122 may be disposed between a word line WL and an adjacent channel pattern CHL of the plurality of channel patterns CHL arranged in a second horizontal direction (Y direction), and may contact the word line WL and the channel pattern CHL.

[0044] According to an embodiment, each of the plurality of channel patterns CHL has one sidewall in a first horizontal direction (X direction) that can contact one of the plurality of back gate dielectric layers 112 selected from the plurality of back gate dielectric layers 112, and another sidewall that can contact one of the plurality of gate dielectric layers 122 selected from the plurality of gate dielectric layers 122. According to an embodiment, each of the plurality of channel patterns CHL has two sidewalls in a second horizontal direction (Y direction) that can contact a corresponding gate dielectric layer 122 among the plurality of gate dielectric layers 122, and can face a corresponding word line WL among the plurality of word lines WL when a gate dielectric layer 122 is present therebetween.

[0045] According to an embodiment, an insulating pattern 124 may be disposed between a pair of word lines WL, which are disposed between a pair of adjacent channel patterns CHL. A first embedded insulating pattern 126 may be disposed between the pair of word lines WL and the bit lines BL, and a second embedded insulating pattern 128 may be disposed between the word lines WL and a plurality of contact plugs 130. The pair of second embedded insulating patterns 128 may be separated from each other in a first horizontal direction (X direction) with the insulating pattern 124 between them. The first embedded insulating pattern 126, the pair of word lines WL, and the pair of second embedded insulating patterns 128 may be configured to overlap each other in a vertical direction (Z direction) between a pair of adjacent channel patterns CHL in the first horizontal direction (X direction). The pair of word lines WL and the insulating pattern 124 may be separated from the plurality of bit lines BL in the vertical direction (Z direction), with the first embedded insulating pattern 126 between the pair of word lines WL and the insulating pattern 124 and the plurality of bit lines BL. A pair of letter lines WL may be spaced apart from a plurality of contact plugs 130 in a vertical direction (Z direction), with a second embedded insulating pattern 128 between the pair of letter lines WL and the plurality of contact plugs 130. In some embodiments, each of the isolation insulating pattern 124, the first embedded insulating pattern 126, and the second embedded insulating pattern 128 may comprise silicon oxide, silicon nitride, or a combination thereof, or be formed of silicon oxide, silicon nitride, or a combination thereof.

[0046] According to an embodiment, each of the gate dielectric layer 122 and the back gate dielectric layer 112 may include or may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof. As used herein, the term "high-k dielectric layer" may refer to a dielectric layer having a dielectric constant higher than that of silicon oxide. In an embodiment, each of the gate dielectric layer 122 and the back gate dielectric layer 112 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO), or be formed from the above materials. Multiple back gate electrodes BG, multiple word lines WL, multiple channel patterns CHL, multiple back gate dielectric layers 112, and multiple gate dielectric layers 122 disposed between multiple bit lines BL and multiple contact plugs 130 can form multiple vertical channel transistors (CTRs). In this document, multiple vertical channel transistors (CTRs) may be referred to as a vertical channel transistor structure.

[0047] exist Figure 3A The diagram shows that the lower surfaces of multiple back gate electrodes BG are positioned closer to the multiple bit lines BL than the multiple word lines WL to the multiple bit lines BL, but the inventive concept is not limited thereto. For example, the lower surfaces of the multiple back gate electrodes BG may be positioned at the same vertical level as the lower surfaces of the multiple word lines WL, or they may be positioned further away from the multiple bit lines BL than the lower surfaces of the multiple word lines WL to the multiple bit lines BL.

[0048] The capacitor structure CTST may include a plurality of contact plugs 130 and a plurality of capacitors 150 disposed on a plurality of channel patterns CHL. Each of the plurality of contact plugs 130 may be disposed on a corresponding channel pattern CHL among the plurality of channel patterns CHL. Each of the plurality of channel patterns CHL may extend in a vertical direction (Z direction) between a bit line BL selected from a plurality of bit lines BL and a contact plug 130 selected from the plurality of contact plugs 130.

[0049] According to an embodiment, a plurality of contact plugs 130 may be separated from a plurality of bit lines BL in a vertical direction (Z direction), and a plurality of channel patterns CHL are provided between the plurality of contact plugs 130 and the plurality of bit lines BL. The plurality of contact plugs 130 may be arranged in a matrix array to be separated from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The plurality of contact plugs 130 may be respectively connected to the plurality of channel patterns CHL in a one-to-one correspondence.

[0050] In some embodiments, each of the plurality of contact plugs 130 may include a metal, a conductive metal nitride, doped polysilicon, or a combination thereof, or be formed of a metal, a conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of contact plugs 130 may include or be Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped polysilicon, or a combination thereof.

[0051] In some embodiments, each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 sequentially stacked on each of the plurality of channel patterns CHL. The first conductive pattern 132 and the second conductive pattern 134 may include or may be semiconductor materials, and the third conductive pattern 136 and the fourth conductive pattern 138 may include or may be metal-based materials. For example, the first conductive pattern 132 may be undoped polysilicon, the second conductive pattern 134 may be doped polysilicon, the third conductive pattern 136 may be a metal silicide, and the fourth conductive pattern 138 may be a metal, but the inventive concept is not limited thereto. For example, each of the plurality of contact plugs 130 may include a second conductive pattern 134 (which includes doped polysilicon), a third conductive pattern 136 (which includes a metal silicide), and a fourth conductive pattern 138 (which includes a metal) sequentially stacked on each of the plurality of channel patterns CHL and not including undoped polysilicon. The stacked structure of the first conductive pattern 132 and the second conductive pattern 134, or the second conductive pattern 134 excluding the first conductive pattern 132, can be a buried contact, the fourth conductive pattern 138 can be a landing pad, and the third conductive pattern 136 can be a metal silicide layer disposed between the buried contact and the landing pad. The stacked structure of the first conductive pattern 132 and the second conductive pattern 134, or the second conductive pattern 134 excluding the first conductive pattern 132, can be a semiconductor pattern, the third conductive pattern 136 can be a metal silicide pattern, and the fourth conductive pattern 138 can be a metal pattern.

[0052] The capacitor structure CTST may include a contact isolation insulating layer 140 surrounding each of a plurality of contact plugs 130. Each of the plurality of contact plugs 130 is permeable through the contact isolation insulating layer 140 and is contactable with a selected channel pattern CHL. The plurality of contact plugs 130 may be separated from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction), with the contact isolation insulating layer 140 between the plurality of contact plugs 130. In some embodiments, the contact isolation insulating layer 140 may include silicon nitride.

[0053] The contact insulating layer 140 may include a main insulating layer 142 and a plurality of sub-insulating layers 146. In some embodiments, the contact insulating layer 140 may further include a plurality of interface insulating layers 144 disposed between the main insulating layer 142 and the plurality of sub-insulating layers 146. For example, the plurality of interface insulating layers 144 may form an interface between the main insulating layer 142 and the plurality of sub-insulating layers 146. Each of the main insulating layer 142 and the plurality of sub-insulating layers 146 may include or may be a nitride, and each of the plurality of interface insulating layers 144 may include or may be an oxide. For example, each of the main insulating layer 142 and the plurality of sub-insulating layers 146 may include or may be silicon nitride, and each of the plurality of interface insulating layers 144 may include or may be silicon oxide. In some embodiments, each of the plurality of interface insulating layers 144 may include or may be a native oxide.

[0054] The contact insulating layer 140 may fill the space between a plurality of contact plugs 130. For example, the plurality of contact plugs 130 may fill a plurality of contact holes, the contact holes being spaces defined by the contact insulating layer 140. A plurality of sub-insulating layers 146 may cover upper portions of the surfaces of the plurality of contact plugs 130 exposed at the sidewalls of the plurality of spaces defined by the main insulating layer 142. For example, the plurality of sub-insulating layers 146 may surround and contact the upper portion of the plurality of contact plugs 130, and the main insulating layer 142 may surround the plurality of sub-insulating layers 146 covering the upper portion of the plurality of contact plugs 130, and may also surround the lower portion of the plurality of contact plugs 130. When each of the plurality of contact plugs 130 has a circular horizontal shape, each of the plurality of sub-insulating layers 146 may have an annular horizontal shape.

[0055] The main insulating layer 142 may fill a portion of the space between a plurality of contact plugs 130. For example, the main insulating layer 142 may fill a portion of the space between a plurality of first conductive patterns 132, a plurality of second conductive patterns 134, a plurality of third conductive patterns 136, and a portion of the space between a plurality of fourth conductive patterns 138, each of which is included in one of the plurality of contact plugs 130. A plurality of sub-insulating layers 146 may fill another portion of the space between the plurality of third conductive patterns 136 and another portion of the space between the plurality of fourth conductive patterns 138, which are included in the plurality of contact plugs 130. The upper surface (e.g., the uppermost surface or upper end surface) of the main insulating layer 142 and the upper ends (e.g., the uppermost surface or upper end surface) of each of the plurality of sub-insulating layers 146 may be positioned at the same vertical level. The lower end (e.g., the lowest surface or lower end surface) of each of the plurality of sub-insulating layers 146 may be disposed at a vertical level higher than the lower surface (e.g., the lowest surface or lower end surface) of the main insulating layer 142. The lowest end of each of the plurality of sub-insulating layers 146 may be disposed at a vertical level lower than or equal to the lower surface of each of the plurality of fourth conductive patterns 138 and lower than or equal to the upper surface of each of the plurality of third conductive patterns 136, and may be disposed at a vertical level higher than or equal to the lower surface of each of the plurality of third conductive patterns 136 and therefore higher than the upper surface of each of the plurality of second conductive patterns 134. The upper and lower surfaces of the main insulating layer 142 can be respectively disposed at one end and the other end of the main insulating layer 142 in the vertical direction (Z direction). The upper and lower ends of the sub insulating layer 146 can be respectively disposed at one end and the other end of the sub insulating layer 146 in the vertical direction (Z direction). The upper and lower surfaces of the fourth conductive pattern 138 can be respectively disposed at one end and the other end of the fourth conductive pattern 138 in the vertical direction (Z direction). The upper and lower surfaces of the third conductive pattern 136 can be respectively disposed at one end and the other end of the third conductive pattern 136 in the vertical direction (Z direction). The upper and lower surfaces of the second conductive pattern 134 can be respectively disposed at one end and the other end of the second conductive pattern 134 in the vertical direction (Z direction). The upper and lower surfaces of the first conductive pattern 132 can be respectively disposed at one end and the other end of the first conductive pattern 132 in the vertical direction (Z direction).

[0056] In some embodiments, the lowest point of each of the plurality of sub-insulating layers 146 may be disposed at a vertical horizontal position that is lower than the upper surface of each of the plurality of third conductive patterns 136 and higher than the lower surface of each of the plurality of third conductive patterns 136. For example, the plurality of sub-insulating layers 146 may extend from the region between the main insulating layer 142 and the plurality of fourth conductive patterns 138 to the region between the main insulating layer 142 and the plurality of third conductive patterns 136. In some embodiments, the plurality of sub-insulating layers 146 may extend from the region between the main insulating layer 142 and the plurality of fourth conductive patterns 138 to the region between the main insulating layer 142 and the plurality of third conductive patterns 136, and may not extend to the plurality of second conductive patterns 134.

[0057] A plurality of first conductive patterns 132 and a plurality of second conductive patterns 134 may contact the main insulating layer 142. A plurality of fourth conductive patterns 138 may contact a plurality of sub-insulating layers 146 and may be disposed between the plurality of sub-insulating layers 146 and may be separate from the main insulating layer 142. In some embodiments, a plurality of third conductive patterns 136 may contact the main insulating layer 142 and the plurality of sub-insulating layers 146. For example, the lower portion of the plurality of third conductive patterns 136 may contact the main insulating layer 142, and the upper portion of the plurality of third conductive patterns 136 may contact the plurality of sub-insulating layers 146, the upper portion of the plurality of third conductive patterns 136 may be disposed between the plurality of sub-insulating layers 146, and the upper portion of the plurality of third conductive patterns 136 may be separate from the main insulating layer 142.

[0058] In some embodiments, the lower portion of the main insulating layer 142 may have a first horizontal width W1, and the upper portion of the main insulating layer 142 may have a second horizontal width W2 smaller than the first horizontal width W1. The sub-insulating layer 146 may have a specific thickness THK and may cover the upper portion of the main insulating layer 142. The lower portion of the contact insulating layer 140 may have a first horizontal width W1, and the upper portion of the contact insulating layer 140 may have a third horizontal width W3 greater than the first horizontal width W1. (Referring below...) Figure 5A The contact isolation insulation layer 140 is described in more detail.

[0059] The plurality of capacitors 150 may include a plurality of lower electrodes 152 respectively connected to a plurality of contact plugs 130, a capacitor dielectric layer 154 conformally covering the surface of each of the plurality of lower electrodes 152, and an upper electrode 156 covering the plurality of lower electrodes 152, with the capacitor dielectric layer 154 between the plurality of lower electrodes 152 and the upper electrode 156. Each of the plurality of lower electrodes 152 may be connected to a channel pattern CHL via a contact plug 130 selected from the plurality of contact plugs 130. A fourth conductive pattern 138 included in each of the plurality of contact plugs 130 may be used as a landing pad for contacting a lower electrode 152 selected from the plurality of lower electrodes 152.

[0060] Each of the plurality of lower electrodes 152 may be cylindrical, wherein the interior is filled to include a horizontal cross-sectional surface having a circular shape, but is not limited thereto. In some embodiments, each of the plurality of lower electrodes 152 may have a cylindrical shape with a closed lower portion. In some embodiments, the plurality of lower electrodes 152 may be arranged in a matrix, wherein the plurality of lower electrodes 152 are arranged in a row in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction). In some other embodiments, the plurality of lower electrodes 152 may be arranged in a honeycomb shape, wherein the plurality of lower electrodes 152 are arranged in a zigzag pattern in the first horizontal direction (X direction) or the second horizontal direction (Y direction). The plurality of lower electrodes 152 may comprise, or be formed of, doped silicon, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride.

[0061] The capacitor dielectric layer 154 may conformally cover the surfaces of the plurality of lower electrodes 152. In some embodiments, the capacitor dielectric layer 154 may include or may be a high-k dielectric layer. In some embodiments, the capacitor dielectric layer 154 may include or may be a metal oxide, the metal oxide including at least one metal selected from hafnium (Hf), zirconium (Zr), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), and titanium (Ti). In some embodiments, each of the plurality of lower electrodes 152 and upper electrodes 156 may include or may be a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxide nitride, or a combination thereof. In some embodiments, each of the plurality of lower electrodes 152 and upper electrodes 156 may include Nb, Nb oxide, Nb nitride, Nb nitride, Ti, Ti oxide, Ti nitride, Ti nitride, Co, Co oxide, Co nitride, Co nitride, Sn, Sn oxide, Sn nitride, Sn nitride or combinations thereof, or may be formed of Nb, Nb oxide, Nb nitride, Nb nitride, Ti, Ti oxide, Ti nitride, Ti nitride, Co, Co oxide, Co nitride, Co nitride, Sn, Sn oxide, Sn nitride, Sn nitride or combinations thereof. In some embodiments, each of the plurality of lower electrodes 152 and upper electrodes 156 may comprise TaN, TiAlN, TaAlN, V, VN, Mo, MoN, W, WN, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3) or combinations thereof, or may be formed of TaN, TiAlN, TaAlN, V, VN, Mo, MoN, W, WN, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO ((La,Sr)CoO3) or combinations thereof. However, the material of each of the plurality of lower electrodes 152 and upper electrodes 156 is not limited to the above description. In some embodiments, in addition to a metallic material, the upper electrode 156 may further include at least one of a doped semiconductor material layer and an interface layer, and may have a stacked structure thereof. The doped semiconductor material layer may include, for example, at least one of doped polycrystalline silicon and doped polycrystalline silicon germanium (poly-SiGe). The main electrode layer may include a metallic material. The interface layer may include, or may be, at least one of, for example, a metal oxide, a metal nitride, a metal carbide, and a gold silicide.

[0062] A first bonding insulating layer 166 may be disposed on the interlayer insulating layer OBL. For example, the first bonding insulating layer 166 may cover and contact the lower surface of the interlayer insulating layer OBL. For example, the first bonding insulating layer 166 may comprise silicon oxide or silicon carbonitride (SiCN) or be formed therefrom.

[0063] The peripheral circuit structure PRST may include a peripheral circuit substrate 202, which includes a plurality of active regions AC defined by a circuit device isolation layer 204 on the peripheral circuit substrate 202, a plurality of circuit gate structures 210 disposed in the plurality of active regions AC of the peripheral circuit substrate 202, an inter-wire insulating layer 220 covering the plurality of circuit gate structures 210, and a wiring structure 230 surrounded by and / or electrically connected to the plurality of circuit gate structures 210 by the inter-wire insulating layer 220. The plurality of circuit gate structures 210 disposed in the plurality of active regions AC may form a plurality of peripheral circuit transistors (PTRs). A second bonding insulating layer 266 may be disposed on the peripheral circuit structure PRST. For example, the second bonding insulating layer 266 may cover the inter-wire insulating layer 220 and the wiring structure 230. The second bonding insulating layer 266 may include silicon oxide or SiCN. The second bonding insulating layer 266 and the first bonding insulating layer 166 may form covalent bonds and may be bonded to each other. The memory cell array structure MCA and the peripheral circuit structure PRST can be bonded to each other through the first bonding insulating layer 166 and the second bonding insulating layer 266, and the memory cell array structure MCA can be stacked on the peripheral circuit structure PRST.

[0064] The peripheral circuit substrate 202 may include, for example, semiconductor materials (such as group IV semiconductor materials, group III-V semiconductor materials, or group II-VI semiconductor materials) and group II-VI oxide semiconductor materials. Group IV semiconductor materials may include, for example, Si, Ge, or SiGe. Group III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). Group II-VI semiconductor materials may include, for example, zinc tellurium (ZnTe) or cadmium sulfide (CdS). The peripheral circuit substrate 202 may be a bulk wafer or an epitaxial layer. The peripheral circuit substrate 202 may also be a bulk wafer or an epitaxial layer. In other embodiments, the peripheral circuit substrate 202 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The active region AC may be defined by a circuit device isolation layer 204 in the peripheral circuit substrate 202, and the active region AC and the circuit gate structure 210 may form a peripheral circuit transistor (PTR).

[0065] The circuit gate structure 210 may include: a circuit gate electrode 214 on the active region AC, a circuit gate insulating layer 212 disposed between the active region AC and the circuit gate electrode 214, a circuit gate capping layer 216 covering the circuit gate electrode 214, and a circuit gate isolator 218 covering the side surface of each of the circuit gate insulating layer 212, the circuit gate electrode 214 and the circuit gate capping layer 216.

[0066] Wiring structure 230 may include circuit wiring lines and circuit wiring contacts. Wiring structure 230 may include conductive materials such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof. Inter-wiring insulation layer 220 may include an insulating material, which may include silicon oxide, silicon nitride, a low-k dielectric material, or combinations thereof. The low-k dielectric material may be a material having a dielectric constant smaller than that of silicon oxide, and may include, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicon glass (OSG), spin-coated glass (SOG), spin-coated polymer, or combinations thereof. In some embodiments, inter-wiring insulation layer 220 may include an ultra-low k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK layer may include SiOC or SiCOH.

[0067] The semiconductor memory device 100 according to an embodiment may include a contact isolation insulating layer 140 surrounding a plurality of contact plugs 130, and the contact isolation insulating layer 140 may include a main isolation insulating layer 142 and a plurality of sub-isolation insulating layers 146. Therefore, the semiconductor memory device 100 can prevent bridging between the plurality of contact plugs 130, thereby enhancing operational reliability.

[0068] Figures 4A to 4H This is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment. In detail, Figures 4A to 4H It shows the manufacturing process. Figure 3A and Figure 3B A cross-sectional view of the method of contacting the plug 130 and the contact insulating layer 140 is shown.

[0069] Reference Figure 4A A first conductive layer 132P, a second conductive layer 134P, and a molded insulating layer 135P are sequentially formed on the substrate layer BSL. The substrate layer BSL may include Figure 3A The channel structure CHST shown is illustrated. In some embodiments, the base layer BSL may include... Figure 3A The bit line structure BLST and the channel structure CHST on the bit line structure BLST are shown, but are not limited thereto. For example, the substrate layer BSL may include the channel structure CHST and may not include the bit line structure BLST. In some embodiments, in sequentially formed Figure 3A After the channel structure CHST and capacitor structure CTST shown, the stacked structure of the channel structure CHST and capacitor structure CTST can be vertically flipped, and then the bit line structure BLST can be formed.

[0070] For example, the first conductive layer 132P may comprise undoped polycrystalline silicon, the second conductive layer 134P may comprise doped polycrystalline silicon, and the molded insulating layer 135P may comprise an oxide. For example, the molded insulating layer 135P may comprise plasma-enhanced oxide (PEOX), tetraethyl orthosilicate (TEOS), tetraethyl borosilicate (BTEOS), tetraethyl phosphoosilicate (PTEOS), tetraethyl borosilicate phosphoosilicate (BPTEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). In some embodiments, the molded insulating layer 135P may comprise TEOS.

[0071] Reference Figure 4A and Figure 4B A first conductive pattern 132, a second conductive pattern 134, and a molded insulating pattern 135 are formed by patterning a first conductive layer 132P, a second conductive layer 134P, and a molded insulating layer 135P. Isolation trenches 140TR can be formed between multiple stacked structures in which the first conductive pattern 132, the second conductive pattern 134, and the molded insulating pattern 135 are sequentially stacked. The multiple stacked structures are separated from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction), with isolation trenches 140TR between the multiple stacked structures.

[0072] Reference Figure 4C A primary insulating layer 142 can be formed to fill the insulating trench 140TR. The primary insulating layer 142 can be formed with a first horizontal width W1 between two stacked structures of a first conductive pattern 132, a second conductive pattern 134, and a molded insulating pattern 135 that are closest to each other in the horizontal direction. For example, the primary insulating layer 142 can be formed with a first horizontal width W1 between two stacked structures of a first conductive pattern 132, a second conductive pattern 134, and a molded insulating pattern 135 that are closest to each other in the first horizontal direction (X direction). The upper surface of the primary insulating structure 142 and the upper surfaces of the plurality of molded insulating patterns 135 can be disposed at the same vertical level to form coplanar surfaces.

[0073] Reference Figure 4C and Figure 4DMultiple molded insulating patterns 135 can be removed. In the process of removing the multiple molded insulating patterns 135, a partial upper portion of the main insulating layer 142 can be removed, and therefore, the horizontal width can be reduced. For example, the main insulating layer 142 may include a first portion 142W and a second portion 142N on the first portion 142W. The horizontal width of the second portion 142N of the main insulating layer 142 may be smaller than the horizontal width of the first portion 142W of the main insulating layer 142. The first portion 142W of the main insulating layer 142 may be a portion of the main insulating layer 142 embedded in multiple first conductive patterns 132 and multiple second conductive patterns 134, and the second portion 142N of the main insulating layer 142 may be a portion of the main insulating layer 142 exposed as the multiple molded insulating patterns 135 are removed. For example, the first portion 142W of the main insulating layer 142 may have a first horizontal width W1 in the first horizontal direction (X direction), and the second portion 142N of the main insulating layer 142 may have a second horizontal width W2 that is smaller than the first horizontal width W1. For example, the first horizontal width W1 may be about 5 nm to about 15 nm, and the second horizontal width W2 may be about 1 nm to about 4 nm smaller than the first horizontal width W1. For example, the second horizontal width W1 may be between 70% and 80% of the first horizontal width W1.

[0074] Reference Figure 4E An initial insulating layer 146P can be formed conformally covering the upper surface of a plurality of second conductive patterns 134 and the side and upper surfaces of the second portion 142N of the main insulating layer 142. For example, the thickness THK of the initial insulating layer 146P (e.g., in a direction perpendicular to the surface on which it is formed) can be from about 0.5 nm to about 4 nm. The thickness THK of the initial insulating layer 146P can be greater than or equal to half the difference between the first horizontal width W1 and the second horizontal width W2. In some embodiments, an initial interface layer 144P can be formed between the main insulating layer 142 and the initial insulating layer 146P.

[0075] Reference Figure 4E and Figure 4FA plurality of sub-isolation insulating layers 146 can be formed by removing a portion of the initial insulating layer 146P. For example, the plurality of sub-isolation insulating layers 146 can be formed by removing a portion of the upper surface of the initial insulating layer 146P covering a plurality of second conductive patterns 134 and the upper surface of the second portion 142N of the main insulating layer 142 via anisotropic etching. The main insulating layer 142 and the plurality of sub-isolation insulating layers 146 can form a contact insulating layer 140. In some embodiments, in the process of removing a portion of the initial insulating layer 146P, a portion of the initial interface layer 144P can be removed together, and thus a plurality of interface insulating layers 144 can be formed. For example, the contact insulating layer 140 may include the main insulating layer 142, the plurality of sub-isolation insulating layers 146, and the plurality of interface insulating layers 144 disposed between the main insulating layer 142 and the plurality of sub-isolation insulating layers 146.

[0076] Multiple sub-insulating layers 146 may cover the side surface of the second portion 142N of the main insulating layer 142. For example, the first portion 142W of the main insulating layer 142 may have a first horizontal width W1 in a first horizontal direction (X direction), the second portion 142N of the main insulating layer 142 may have a second horizontal width W2 that is less than the first horizontal width W1, and the second portion 142N of the main insulating layer 142 and the sub-insulating layers 146 covering the side surface of the second portion 142N of the main insulating layer 142 may have a third horizontal width W3 that is greater than or equal to the first horizontal width W1. The third horizontal width W3 may be slightly greater than or equal to the sum of the second horizontal width W2 and twice the thickness THK of the sub-insulating layer 146.

[0077] Reference Figure 4F and Figure 4G A plurality of third conductive patterns 136 may be formed on a plurality of second conductive patterns 134. In some embodiments, a metal material layer may be formed on the plurality of second conductive patterns 134, and then the plurality of third conductive patterns 136 may be formed by performing a heat treatment. For example, each of the plurality of third conductive patterns 136 may include a metal silicide.

[0078] In some embodiments, the third conductive pattern 136 may be a composite of a metal material layer and an upper partial portion of the second conductive pattern 134. For example, after forming a plurality of third conductive patterns 136, the upper surfaces of a plurality of second conductive patterns 134 may be disposed in a manner that is more favorable than the surface of the second conductive pattern 134. Figure 4FThe upper surface of the plurality of second conductive patterns 134 shown is at a lower vertical level. The lowermost point of each of the plurality of third conductive patterns 136 may be located at a lower vertical level than the lowermost point of each of the plurality of sub-insulating layers 146, and the uppermost point of each of the plurality of third conductive patterns 136 may be located at a higher vertical level than the lowermost point of each of the plurality of sub-insulating layers 146. For example, a lower portion of each of the plurality of sub-insulating layers 146 may be embedded in the plurality of third conductive patterns 136.

[0079] Reference Figure 4H Multiple fourth conductive patterns 138 can be formed on multiple third conductive patterns 136. The multiple fourth conductive patterns 138 can be formed to fill all the space defined by the contact insulating layer 140. For example, the space defined by the contact insulating layer 140 (e.g., the space formed in and retained therein) can be completely filled by multiple contact plugs 130 formed by multiple first conductive patterns 132, multiple second conductive patterns 134, multiple third conductive patterns 136, and multiple fourth conductive patterns 138. The upper surface of the main insulating layer 142, the upper surfaces of the multiple sub-insulating layers 146, and the upper surfaces of the multiple fourth conductive patterns 138 can form coplanar surfaces.

[0080] Reference Figures 4A to 4H Since the upper portion of the main insulating layer 142 is removed during the process of removing multiple molded insulating patterns 135, multiple sub-insulating layers 146 can cover the side surface of the second portion 142N of the main insulating layer 142 even when the second portion 142N of the main insulating layer 142 has a thinner horizontal width than the first portion 142W. Therefore, bridging between multiple contact plugs 130 can be prevented, thereby improving operational reliability.

[0081] Figures 5A to 5D This is a cross-sectional view of a semiconductor memory device according to an embodiment. In detail, Figures 5A to 5D It corresponds to Figure 4H A magnified cross-sectional view of part V.

[0082] Reference Figure 5AA contact insulating layer 140 may surround a plurality of contact plugs 130. Each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 stacked sequentially. In some embodiments, the lower surface of the third conductive pattern 136 may have or include a flat surface. The contact insulating layer 140 may fill the space between the plurality of contact plugs 130. The contact insulating layer 140 may include a main insulating layer 142 and a plurality of sub-insulating layers 146. The contact insulating layer 140 may also include a plurality of interface insulating layers 144 disposed between the main insulating layer 142 and the plurality of sub-insulating layers 146. For example, the plurality of interface insulating layers 144 may be formed at the interface between the main insulating layer 142 and the plurality of sub-insulating layers 146.

[0083] The main insulating layer 142 may include a first portion 142W and a second portion 142N on the first portion 142W. The first portion 142W of the main insulating layer 142 may be a portion of the main insulating layer 142, such as a lower portion, and the second portion 142N may be a portion of the main insulating layer 142, such as an upper portion, wherein the lower portion faces the portion including the upper portion. Figure 3A The channel structure CHST of the multiple channel patterns CHL shown in the figure, the upper portion facing Figure 3AMultiple capacitors 150 are shown. Between contact plugs 130 adjacent to each other in a first horizontal direction (X direction), a first portion 142W of a main insulating layer 142 may have a first horizontal width W1 in the first horizontal direction (X direction), and a second portion 142N of the main insulating layer 142 may have a second horizontal width W2 smaller than the first horizontal width W1. Multiple sub-insulating layers 146 may cover the side surface of the second portion 142N of the main insulating layer 142. For example, the first portion 142W of the main insulating layer 142 may have a first horizontal width W1 in the first horizontal direction (X direction), and the second portion 142N of the main insulating layer 142 may have a second horizontal width W2 smaller than the first horizontal width W1. The main insulating layer 142 may have a stepped shape between the first portion 142W and the second portion 142N. For example, the portion of the upper end of the first portion 142W not covered by the second portion 142N may be a stepped tread included in the main insulating layer 142, and the side surface of the second portion 142N may be a stepped vertical plate included in the main insulating layer 142. The second portion 142N of the main insulating layer 142 and the sub-insulating layer 146 covering the side surface of the second portion 142N of the main insulating layer 142 may have a third width W3 greater than or equal to the first horizontal width W1. The thickness THK of the plurality of sub-insulating layers 146 may be greater than or equal to half the difference between the first horizontal width W1 and the second horizontal width W2. Furthermore, in various embodiments, the entire contact insulating layer 140 may have a stepped shape between the upper and lower portions of the contact insulating layer 140 at the interface or joint where the sub-insulating layers 146 terminate (e.g., at a vertical height between the upper and lower surfaces of the third conductive pattern 136). The stepped shape may have angled corners or rounded corners. Furthermore, in various embodiments, the horizontal width (e.g., maximum horizontal width) of each contact plug 130 at its first end is less than the horizontal width (e.g., maximum horizontal width) of each contact plug 130 at its second end, wherein the first end is connected to the capacitor 150 and is located at a first vertical level, and the second end is opposite the first end and is located at a second vertical level. Additionally, the minimum horizontal width of the main insulating layer 142 between two adjacent contact plugs 130 at the first vertical level (e.g., the horizontal width in the first horizontal direction where the two adjacent contact plugs 130 are closest to each other at the first vertical level) is less than the minimum horizontal width of the main insulating layer 142 between two adjacent contact plugs 130 at the second vertical level (e.g., the horizontal width in the first horizontal direction where the two adjacent contact plugs 130 are closest to each other at the second vertical level).

[0084] The lowest point of each of the plurality of third conductive patterns 136 may be located at a vertical level lower than the lowest point of each of the plurality of sub-insulating layers 146, and the highest point of each of the plurality of third conductive patterns 136 may be located at a vertical level higher than the lowest point of each of the plurality of sub-insulating layers 146. For example, a lower portion of each of the plurality of sub-insulating layers 146 may be embedded in the plurality of third conductive patterns 136.

[0085] Multiple interface insulating layers 144 may be disposed between the main insulating layer 142 and multiple sub-insulating layers 146. For example, the multiple interface insulating layers 144 may cover the stepped treads and uprights included in the main insulating layer 142, that is, the portion of the upper end of the first portion 142W not covered by the second portion 142N and the side surface of the second portion 142N.

[0086] When each of the plurality of contact plugs 130 has a circular horizontal shape (when viewed from a plan view), each of the sub-isolation insulating layers 146 may have an annular horizontal shape. A portion of the lower surface of each of the plurality of combined sub-isolation insulating layers 146 and interface insulating layers 144 (or, when interface insulating layer 144 is not used, a portion of the lower surface of sub-isolation insulating layer 146) may be adjacent to and in contact with a portion of the stepped tread included in the main isolation insulating layer 142 (i.e., the upper end of the first portion 142W of the main isolation insulating layer 142), and other portions of the lower surface of each of the plurality of combined sub-isolation insulating layers 146 and interface insulating layers 144 may be adjacent to and in contact with a plurality of third conductive patterns 136. The inner surface of each of the multiple combined sub-isolation insulating layers 146 and interface insulating layers 144 having annular horizontal shapes (or the inner surface of the sub-isolation insulating layer 146 when the interface insulating layer 144 is not used) may cover the stepped vertical plate included in the main isolation insulating layer 142 (i.e., the side surface of the second portion 142N of the main isolation insulating layer 142), and furthermore, the upper portion of the outer surface of each of the multiple sub-isolation insulating layers 146 may be adjacent to and in contact with the multiple fourth conductive patterns 138, and the lower portion of the outer surface of each of the multiple sub-isolation insulating layers 146 may be adjacent to and in contact with the multiple third conductive patterns 136.

[0087] Reference Figure 5BA contact insulating layer 140 may surround a plurality of contact plugs 130a. Each of the plurality of contact plugs 130a may include a first conductive pattern 132, a second conductive pattern 134a, a third conductive pattern 136a, and a fourth conductive pattern 138, which are stacked sequentially. In some embodiments, the lower surface of the third conductive pattern 136a may include a convex surface facing the second conductive pattern 134a, and the upper surface of the second conductive pattern 134a may include a concave surface facing the third conductive pattern 136a corresponding to the lower surface of the third conductive pattern 136a. The contact insulating layer 140 may fill the space between the plurality of contact plugs 130a. The contact insulating layer 140 may include a main insulating layer 142 and a plurality of sub-insulating layers 146. The contact insulating layer 140 may also include a plurality of interface insulating layers 144 disposed between the main insulating layer 142 and the plurality of sub-insulating layers 146.

[0088] Reference Figure 5C A contact insulating layer 140a may surround a plurality of contact plugs 130. Each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 stacked sequentially. The contact insulating layer 140a may fill the space between the plurality of contact plugs 130. The contact insulating layer 140a may include a main insulating layer 142a and a plurality of sub-insulating layers 146a. The plurality of sub-insulating layers 146a may contact the main insulating layer 142a. For example, an interface may be provided between the main insulating layer 142a and the plurality of sub-insulating layers 146a, but it may be impossible to detect physically observable differences in thickness or chemical composition (e.g., oxygen). In this embodiment, for example, Figure 5A and 5B The interface isolation insulation layer is depicted in the image.

[0089] Reference Figure 5D A contact insulating layer 140b may surround a plurality of contact plugs 130. Each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 stacked sequentially. The contact insulating layer 140b may fill the space between the plurality of contact plugs 130. The contact insulating layer 140b may include a main insulating layer 142b and a plurality of sub-insulating layers 146b. The contact insulating layer 140b may also include a plurality of interface insulating layers 144b disposed between the main insulating layer 142b and the plurality of sub-insulating layers 146b. For example, the plurality of interface insulating layers 144b may be formed at the interface between the main insulating layer 142b and the plurality of sub-insulating layers 146b. In some embodiments, the plurality of sub-insulating layers 146b do not overlap with the main insulating layer 142b in the vertical direction (Z direction).

[0090] The main insulating layer 142b may include a first portion 142L and a second portion 142U on the first portion 142L. The first portion 142L of the main insulating layer 142b may be a face of the main insulating layer 142b including Figure 3A The channel structure CHST portion of the multiple channel patterns CHL shown in the figure, the second portion 142U may be the face of the main insulating layer 142b. Figure 3A The diagram shows portions of multiple capacitors 150. Between contact plugs 130 adjacent to each other in a first horizontal direction (X direction), a first portion 142L of the main insulating layer 142b may have a first horizontal width W1a in the first horizontal direction (X direction), and a second portion 142U of the main insulating layer 142b may have a second horizontal width W2a. The first horizontal width W1a and the second horizontal width W2a may have the same value. Multiple sub-insulating layers 146b may cover the side surfaces of the second portion 142U of the main insulating layer 142b. The main insulating layer 142b may include side surfaces extending in a vertical direction (Z direction). For example, the side surfaces of the first portion 142L and the second portion 142U may be aligned in the vertical direction (Z direction). The contact insulating layer 140b may include a lower portion formed by a first portion 142L of a main insulating layer 142b, and an upper portion formed by a second portion 142U of the main insulating layer 142b, an interface insulating layer 144b, and a sub-insulating layer 146b. In some embodiments, the upper portion of the contact insulating layer 140b may be configured to include the second portion 142U of the main insulating layer 142b, the sub-insulating layer 146b, and the interface insulating layer 144b. The lower portion of the contact insulating layer 140b may have a first horizontal width W1a, and the upper portion of the contact insulating layer 140b may have a third horizontal width W3a greater than the first horizontal width W1a.

[0091] The lowest point of each of the plurality of third conductive patterns 136 may be located at a vertical level lower than the lowest point of each of the plurality of sub-insulating layers 146b, and the highest point of each of the plurality of third conductive patterns 136 may be located at a vertical level higher than the lowest point of each of the plurality of sub-insulating layers 146b. For example, a lower portion of each of the plurality of sub-insulating layers 146b may be embedded in the plurality of third conductive patterns 136. For example, the boundary between the upper portion of the contact insulating layer 140b having a third horizontal width W3a and the lower portion of the contact insulating layer 140b having a first horizontal width W1a may be located at a vertical level lower than the upper surface of the third conductive pattern 136 and higher than the lower surface of the third conductive pattern 136. Figure 5A The alternative features of the contact plug shown can be compared with Figures 5B to 5D Used together with any of the embodiments described above.

[0092] Figure 6A and Figure 6B These are cross-sectional and plan views of a semiconductor memory device according to an embodiment. In detail, Figure 6A Is with Figure 4H The enlarged cross-sectional view corresponding to part V. Figure 6A It is along Figure 6B A cross-sectional view taken from line VIA-VIA'. Figure 6B It is shown Figure 6A The plan view of the fourth conductive pattern 138 and the contact isolation insulating layer 140c shown in the figure.

[0093] Reference Figure 6A and Figure 6B A contact insulating layer 140c may surround a plurality of contact plugs 130. Each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 stacked sequentially. The contact insulating layer 140c may fill the space between the plurality of contact plugs 130. The contact insulating layer 140c may include a main insulating layer 142c, a plurality of sub-insulating layers 146c, and a plurality of interface insulating layers 144c disposed between the main insulating layer 142c and the plurality of sub-insulating layers 146c. In some embodiments, the contact insulating layer 140c may not include the plurality of interface insulating layers 144c.

[0094] In some embodiments, the lower portion 142Wc of the main insulating layer 142c may have a first horizontal width W1, and the upper portion 142Nc of the main insulating layer 142c may have a second horizontal width W2 smaller than the first horizontal width W1. The sub-insulating layer 146c may have a specific thickness THK and may cover the second portion 142Nc of the main insulating layer 142c. The lower portion of the contact insulating layer 140c may have a first horizontal width W1, and the upper portion of the contact insulating layer 140c may have a third horizontal width W3 greater than the first horizontal width W1.

[0095] The main insulating layer 142c may include a first portion 142Wc and a second portion 142Nc on the first portion 142Wc. In some embodiments, the main insulating layer 142c may include at least one void 142V in the second portion 142Nc. Figure 4C and Figure 4DIn the process of removing multiple molded insulating patterns 135 shown, when the upper portion of the main insulating layer 142 is removed together, at least one void 142V included in the second portion 142Nc of the main insulating layer 142c can be formed. Multiple sub-insulating layers 146c can cover the side surfaces of the second portion 142Nc of the main insulating layer 142c and can fill at least one void 142V included in the second portion 142Nc of the main insulating layer 142c.

[0096] Figure 7A and Figure 7B These are cross-sectional and plan views of a semiconductor memory device according to an embodiment. In detail, Figure 7A Is with Figure 4H The enlarged cross-sectional view corresponding to part V. Figure 7A It is along Figure 7B The cross-sectional view taken from line VIIA-VIIA', and Figure 7B It is shown Figure 7A The plan view of the fourth conductive pattern 138 and the contact isolation insulating layer 140d shown in the figure.

[0097] Reference Figure 7A and Figure 7B A contact insulating layer 140d may surround a plurality of contact plugs 130. Each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, a third conductive pattern 136, and a fourth conductive pattern 138 stacked sequentially. The contact insulating layer 140d may fill the space between the plurality of contact plugs 130. The contact insulating layer 140d may include a main insulating layer 142d, a plurality of sub-insulating layers 146d, and a plurality of interface insulating layers 144d disposed between the main insulating layer 142d and the plurality of sub-insulating layers 146d. In some embodiments, the contact insulating layer 140d may not include the plurality of interface insulating layers 144d.

[0098] In some embodiments, the lower portion 142Wd of the main insulating layer 142d may have a first horizontal width W1, and the upper portion 142Nd of the main insulating layer 142d may have a second horizontal width W2 smaller than the first horizontal width W1. The sub-insulating layer 146d may have a specific thickness THK and may cover the second portion 142Nd of the main insulating layer 142d. The lower portion of the contact insulating layer 140d may have a first horizontal width W1, and the upper portion of the contact insulating layer 140 may have a third horizontal width W3 greater than the first horizontal width W1.

[0099] The main insulating layer 142d may include a first portion 142Wd and a second portion 142Nd on the first portion 142Wd. In some embodiments, the main insulating layer 142d may include at least one slit 142S in the second portion 142Nd. Figure 4C and Figure 4D In the process of removing multiple molded insulating patterns 135 shown, when the upper portion of the main insulating layer 142 is removed together, at least one slit 142S may be formed in a second portion 142Nd of the main insulating layer 142d. The at least one slit 142S in the second portion 142Nd of the main insulating layer 142d may extend in a vertical direction (Z direction). In some embodiments, the at least one slit 142S in the second portion 142Nd of the main insulating layer 142d may extend from the uppermost end of the second portion 142Nd in a vertical direction (Z direction) to the lowermost end of the second portion 142Nd, but is not limited thereto. For example, the at least one slit 142S in the second portion 142Nd of the main insulating layer 142d may extend from the uppermost end of the second portion 142Nd in a vertical direction (Z direction) toward the lowermost end of the second portion 142Nd, and may not extend to the lowermost end of the second portion 142Nd. For example, at least one slit 142S included in the second portion 142Nd of the main insulating layer 142d may extend from the lowermost end of the second portion 142Nd in a vertical direction (Z direction) toward the uppermost end of the second portion 142Nd, and may not extend to the uppermost end of the second portion 142Nd. For example, at least one slit 142S included in the second portion 142Nd of the main insulating layer 142d may extend in a vertical direction (Z direction) from a vertical level below the uppermost end of the second portion 142Nd to a vertical level above the lowermost end of the second portion 142Nd. A plurality of sub-insulating layers 146d may cover the side surfaces of the second portion 142Nd of the main insulating layer 142d and may fill at least one slit 142S included in the second portion 142Nd of the main insulating layer 142d.

[0100] Figure 8 This is a schematic perspective view of a semiconductor memory device 1000a according to an embodiment.

[0101] Reference Figure 8 The semiconductor memory device 1000a may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS, wherein the peripheral circuit structure PS includes a peripheral circuit substrate PSUB. Figure 8 The peripheral circuit substrate PSUB, peripheral circuit structure PS, and unit array structure CS shown can be connected with... Figure 2The peripheral circuit substrate PSUB, peripheral circuit structure PS, and cell array structure CS shown are essentially the same, and therefore, repeated descriptions can be omitted.

[0102] The cell array structure CS can be bonded to the peripheral circuit structure PS. The lower metal pad LMP can be located in the uppermost layer of the peripheral circuit structure PS. The lower metal pad LMP can be electrically connected to the core and peripheral circuits included in the peripheral circuit structure PS. The upper metal pad UMP can be located in the lowermost layer of the cell array structure CS. The upper metal pad UMP can be electrically connected to the memory cell array included in the cell array structure CS. Figure 1 1010). The upper metal pad UMP can contact and bond to the lower metal pad LMP of the peripheral circuit structure PS. In some embodiments, the peripheral circuit structure PS and the cell array structure CS can be bonded to each other via a metal oxide hybrid bonding process, and therefore, the memory cell array included in the cell array structure CS ( Figure 1 (1010) can be electrically connected to the core and peripheral circuits respectively included in the peripheral circuit structure PS. For example, the corresponding lower metal pads LMP and upper metal pads UMP can expand based on heat and can be bonded to each other, and then a plurality of bonding pads MP can be formed to form a single unit by diffusion bonding of metal atoms, and the insulating layer surrounding the lower metal pads LMP included in the peripheral circuit structure PS and the insulating layer surrounding the upper metal pads UMP included in the cell array structure CS can form covalent bonds and can be bonded to each other.

[0103] Figure 9 This is a cross-sectional view showing a semiconductor memory device 100a according to an embodiment.

[0104] Reference Figure 9 The semiconductor memory device 100a may include a memory cell array structure MCA in which a plurality of memory cells are disposed. For example, the plurality of memory cells may include a plurality of vertical channel transistors (CTRs). The memory cell structure MCA may be constructed by stacking bit line structures (BLSTs), channel structures (CHSTs), and capacitor structures (CTSTs). The peripheral circuit structure PRST may include peripheral circuit transistors (PTRs) constructed by circuit gate structure 210. In some embodiments, the semiconductor memory device 100a may have a CoP structure in which the memory cell array structure MCA and the peripheral circuit structure PRST overlap each other in the vertical direction (Z direction). Figure 9 The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown can be used with... Figure 3A The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown are essentially the same, and therefore, repeated descriptions can be omitted.

[0105] The bitline structure BLST may further include a unit wiring structure 170 disposed beneath the interlayer insulation layer OBL and an inter-unit wiring insulation layer 180 surrounding the unit wiring structure 170. The unit wiring structure 170 may include a plurality of unit wiring lines and a plurality of unit wiring contacts. The unit wiring structure 170 may include a conductive material, such as Cu, Al, W, Ag, Au, or combinations thereof. The inter-unit wiring insulation layer 180 may include an insulating material, which may include silicon oxide, silicon nitride, a low-k dielectric material, or combinations thereof. Some of the plurality of unit wiring contacts of the unit wiring structure 170 may pass through the interlayer insulation layer OBL and at least some of the plurality of insulating capping lines BLCP, and may electrically connect at least some of the plurality of bit lines BL to at least some of the plurality of unit wiring lines.

[0106] A plurality of upper metal pads 195 electrically connected to the cell wiring structure 170 and a first bonding insulating layer 190 surrounding the plurality of upper metal pads 195 may be disposed below the cell wiring structure 170 and the cell wiring interlayer insulating layer 180. A plurality of lower metal pads 295 electrically connected to the wiring structure 230 and a second bonding insulating layer 290 surrounding the plurality of lower metal pads 295 may be disposed on the wiring interlayer insulating layer 220 and the wiring structure 230. Each of the first bonding insulating layer 190 and the second bonding insulating layer 290 may comprise silicon oxide or SiCN. In some embodiments, the peripheral circuit structure PRST and the memory cell array structure MCA may be bonded to each other via a metal oxide hybrid bonding process. The first bonding insulating layer 190 and the second bonding insulating layer 290 may contact each other to form covalent bonds and may be bonded to each other. The plurality of corresponding upper metal pads 195 and the plurality of lower metal pads 295 may expand based on heat and may be bonded to each other, and then a plurality of bonding pads MP may be formed by diffusion bonding of metal atoms to form an integral plurality of bonding pads. The upper metal pad 195 and the lower metal pad 295 can be Figure 8 The upper metal pad UMP and the lower metal pad LMP are shown in the diagram.

[0107] Figure 10 This is a cross-sectional view showing a semiconductor memory device 100b according to an embodiment.

[0108] Reference Figure 10The semiconductor memory device 100b may include a memory cell array structure (MCA) in which a plurality of memory cells are disposed. In some embodiments, the semiconductor memory device 100b may have a CoP structure in which the memory cell array structure (MCA) and the peripheral circuit structure (PRST) overlap each other in the vertical direction (Z direction). In the semiconductor memory device 100b, the memory cell array structure (MCA) may be stacked on the peripheral circuit structure (PRST), and the memory cell array structure (MCA) may include a capacitor structure (CTST), a channel structure (CHST), and a bit line structure (BLST) sequentially stacked on the peripheral circuit structure (PRST). Figure 10 The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown can be used with... Figure 3A The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown are basically the same, but may have a vertically flipped structure, and therefore, repeated descriptions can be omitted.

[0109] The capacitor structure CTST may include a plurality of contact plugs 130, a contact insulating layer 140 surrounding the plurality of contact plugs 130, and a plurality of capacitors 150. Each capacitor 150 includes a plurality of lower electrodes 152 respectively connected to the lower portions of the plurality of contact plugs 130, a capacitor dielectric layer 154 conformally covering the surface of each of the plurality of lower electrodes 152, and an upper electrode 156 covering the capacitor dielectric layer 154, wherein the capacitor dielectric layer 154 is located between the plurality of lower electrodes 152 and the upper electrode 156. In some embodiments, the capacitor structure CTST may further include a capacitor capping layer CTCP covering the lower surface of the upper electrode 156. The capacitor capping layer CTCP may include silicon oxide, silicon nitride, or a combination thereof.

[0110] The bit line structure BLST may include multiple bit lines BL, multiple insulating capping lines BLCP covering the upper surfaces of the multiple bit lines BL, and an interlayer insulating layer OBL surrounding the multiple bit lines BL and the multiple insulating capping lines BLCP. In some embodiments, the bit line structure BLST may further include a bit line capping layer CBL covering the upper surface of the interlayer insulating layer OBL. The bit line capping layer CBL may include silicon nitride. The bit lines BL and word lines WL may be connected, for example, via conductive vias to the wiring structure 230 of the peripheral circuit structure PRST in a region outside the memory cell array structure MCA.

[0111] In some embodiments, a first bonding insulating layer 166 may be disposed on a capacitor capping layer CTCP. For example, the first bonding insulating layer 166 may cover the lower surface of the capacitor capping layer CTCP. A second bonding insulating layer 266 may cover the inter-wiring insulating layer 220 and the wiring structure 230. The second bonding insulating layer 266 and the first bonding insulating layer 166 may form covalent bonds and may be bonded to each other. The memory cell array structure MCA and the peripheral circuit structure PRST may be bonded to each other through the first bonding insulating layer 166 and the second bonding insulating layer 266, and the memory cell array structure MCA may be stacked on the peripheral circuit structure PRST.

[0112] Figure 11 This is a schematic perspective view of a semiconductor memory device 1000b according to an embodiment.

[0113] Reference Figure 11 The semiconductor memory device 1000b may include a cell array structure CS and a peripheral circuit structure PS on the cell array structure CS. Figure 11 The peripheral circuit substrate PSUB, peripheral circuit structure PS, and cell array structure CS shown can be connected with... Figure 2 The peripheral circuit substrate PSUB, peripheral circuit structure PS, and cell array structure CS shown are essentially the same, and therefore, repeated descriptions can be omitted.

[0114] The peripheral circuit structure PS can be coupled to the cell array structure CS. Figure 11 The diagram shows a peripheral circuit substrate PSUB disposed on the side of the peripheral circuit structure PS facing the cell array structure CS in the vertical direction (Z direction), but the inventive concept is not limited thereto. In some embodiments, the peripheral circuit substrate PSUB may be disposed on the side of the peripheral circuit structure PS opposite to the cell array structure CS in the vertical direction (Z direction).

[0115] In some embodiments, in the semiconductor memory device 1000b, the peripheral circuit structure PS and the cell array structure CS can be bonded to each other via a metal-oxide hybrid bonding process, such as... Figure 8 The semiconductor memory device 1000a shown is illustrated.

[0116] Figure 12A and Figure 12B This is a cross-sectional view showing a semiconductor memory device according to an embodiment.

[0117] Reference Figure 12AThe semiconductor memory device 100c may include a memory cell array structure MCA in which a plurality of memory cells are disposed and a peripheral circuit structure PRST stacked on the memory cell array structure MCA. In some embodiments, the semiconductor memory device 100c may have a PoC structure in which the peripheral circuit structure PRST and the memory cell array structure MCA overlap each other in the vertical direction (Z direction). Figure 12A The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown can be used with... Figure 3A The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown are essentially the same, and therefore, repeated descriptions can be omitted.

[0118] The capacitor structure CTST may further include a capacitor capping layer CTCP covering the upper surface of the upper electrode 156. The peripheral circuit structure PRST may further include a peripheral circuit capping layer PRCP covering the wiring insulation layer 220 and the wiring structure 230. Each of the capacitor capping layer CTCP and the peripheral circuit capping layer PRCP may include silicon oxide, silicon nitride, or a combination thereof.

[0119] In some embodiments, a first bonding insulating layer 166 may be disposed on a capacitor capping layer (CTCP). For example, the first bonding insulating layer 166 may cover the upper surface of the capacitor capping layer (CTCP). A second bonding insulating layer 266 may cover the lower surface of a peripheral circuit structure (PRST). In some embodiments, the second bonding insulating layer 266 may cover the lower surface of a peripheral circuit substrate 202. The second bonding insulating layer 266 and the first bonding insulating layer 166 may form covalent bonds and may be bonded to each other. The memory cell array structure (MCA) and the peripheral circuit structure (PRST) may be bonded to each other through the first bonding insulating layer 166 and the second bonding insulating layer 266, and the peripheral circuit structure (PRST) may be stacked on the memory cell array structure (MCA).

[0120] Reference Figure 12B The semiconductor memory device 100d may include a memory cell array structure (MCA) in which a plurality of memory cells are disposed and a peripheral circuit structure (PRST) stacked on the memory cell array structure (MCA). In some embodiments, the semiconductor memory device 100d may have a PoC structure in which the peripheral circuit structure (PRST) and the memory cell array structure (MCA) overlap each other in the vertical direction (Z direction). Figure 12B The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown can be used with... Figure 10The peripheral circuit structure PRST, bit line structure BLST, channel structure CHST, and capacitor structure CTST shown are essentially the same, and therefore, repeated descriptions can be omitted.

[0121] A capacitor structure CTST may be attached to a support substrate 102. The support substrate 102 may include, for example, semiconductor materials, such as group IV, III-V, or II-VI semiconductor materials and group II-VI oxide semiconductor materials. The capacitor structure CTST may also include a capacitor capping layer CTCP covering the lower surface of the upper electrode 156. In some embodiments, the capacitor capping layer CTCP may function as a bonding insulating layer for bonding the support substrate 102 to the capacitor structure CTST. For example, after the capacitor structure CTST is formed, the capacitor structure CTST may be attached to the support substrate 102 such that the capacitor capping layer CTCP of the capacitor structure CTST faces the support substrate 102. For example, the capacitor capping layer CTCP may include silicon oxide, silicon nitride, or a combination thereof.

[0122] The peripheral circuit structure PRST may also include a peripheral circuit capping layer PRCP covering the wiring interlayer insulation layer 220 and the wiring structure 230. Each of the capacitor capping layer CTCP and the peripheral circuit capping layer PRCP may include silicon oxide, silicon nitride, or a combination thereof.

[0123] A first bonding insulating layer 166 may be disposed on the interlayer insulating layer OBL. For example, the first bonding insulating layer 166 may cover the upper surface of the interlayer insulating layer OBL. A second bonding insulating layer 266 may cover the lower surface of the peripheral circuit structure PRST. In some embodiments, the second bonding insulating layer 266 may cover the lower surface of the peripheral circuit substrate 202. The second bonding insulating layer 266 and the first bonding insulating layer 166 may form covalent bonds and may be bonded to each other. The memory cell array structure MCA and the peripheral circuit structure PRST may be bonded to each other through the first bonding insulating layer 166 and the second bonding insulating layer 266, and the peripheral circuit structure PRST may be stacked on the memory cell array structure MCA. Figure 12A and Figure 12B The bit line BL and word line WL in the memory cell array structure MCA can be connected to the wiring structure 230 of the peripheral circuit structure PRST in a region outside the memory cell array structure MCA, for example, through conductive vias.

[0124] Exemplary embodiments have been described above in the accompanying drawings and specification. Embodiments have been described using the terminology described herein, but this is merely for illustrating the inventive concept and not for limiting the meaning or scope of the inventive concept as defined in the appended claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible based on the inventive concept.

[0125] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: Bit lines, which extend in the horizontal direction; Contact plug; A contact isolation insulation layer surrounds the contact plug, the contact isolation insulation layer includes a main isolation insulation layer and a sub-isolation insulation layer, the sub-isolation insulation layer is disposed between a portion of the contact plug and the main isolation insulation layer, wherein a stepped shape is formed in the contact isolation insulation layer between the upper part and the lower part of the contact isolation insulation layer; A channel pattern, disposed between the bit line and the contact plug, and extending in the vertical direction; and A capacitor, which is connected to the contact plug.

2. The semiconductor memory device of claim 1, wherein: The main insulating layer includes a first portion adjacent to the channel pattern and having a first horizontal width, and a second portion on the first portion overlapping the first portion along the vertical direction and adjacent to the capacitor, the second portion having a second horizontal width smaller than the first horizontal width. The sub-insulating layer covers the side surface of the second portion of the main insulating layer.

3. The semiconductor memory device of claim 2, wherein, The thickness of the sub-isolation insulation layer is greater than or equal to 1 / 2 of the difference between the first horizontal width and the second horizontal width.

4. The semiconductor memory device of claim 2, wherein, The contact plug includes a semiconductor pattern connected to and adjacent to the bit line, a metal pattern connected to and adjacent to the capacitor, and a metal silicide pattern disposed between the semiconductor pattern and the metal pattern.

5. The semiconductor memory device of claim 4, wherein, Relative to the vertical direction, the first end surface of the sub-isolation insulating layer is disposed at the same vertical level as the first end surface of the main isolation insulating layer, and the opposite second end surface of the sub-isolation insulating layer is disposed at the vertical level between the opposite first and second ends of the metal silicide pattern.

6. The semiconductor memory device of claim 4, wherein, The main insulating layer has a stepped shape between the first portion and the second portion, and A portion of the lower surface of the sub-isolation insulation layer is adjacent to a portion of a stepped tread included in the main isolation insulation layer, and another portion of the sub-isolation insulation layer is adjacent to the metal silicide pattern.

7. The semiconductor memory device of claim 2, wherein, The second portion of the main insulating layer includes at least one void, and The sub-insulating layer fills the at least one void.

8. The semiconductor memory device of claim 1, wherein, The contact isolation insulation layer further includes an interface insulation layer disposed between the main isolation insulation layer and the sub-isolation insulation layer.

9. The semiconductor memory device of claim 1, wherein, The sub-isolation insulation layer has an annular shape when viewed from a plan view and surrounds a portion of the contact plug.

10. The semiconductor memory device of claim 1, wherein: The contact plug is one of a plurality of contact plugs, and the capacitor is one of a plurality of capacitors respectively connected to the plurality of contact plugs; The horizontal width of each contact plug at the first end where the contact plug is connected to the capacitor and at the first vertical level is smaller than the horizontal width of each contact plug at the second end opposite the first end and at the second vertical level. The minimum horizontal width of the main insulating layer between two adjacent contact plugs at the first vertical level is greater than the minimum horizontal width of the main insulating layer between the two adjacent contact plugs at the second vertical level.

11. A semiconductor memory device, comprising: Bit line, which extends in the first horizontal direction; The character line extends along the bit line in a second horizontal direction different from the first horizontal direction; A back gate electrode that extends along the second horizontal direction on the bit line and is configured to be separated from the word line along the first horizontal direction; A contact plug, on the bit line and the back gate electrode, has a first conductive pattern and a second conductive pattern, each comprising a semiconductor material, and a third conductive pattern and a fourth conductive pattern, each comprising a metal base material, sequentially stacked in the contact plug. A contact isolation insulating layer surrounds the contact plug on the word line and the back gate electrode, and includes a lower portion and an upper portion, the lower portion having a first minimum horizontal width in the first horizontal direction, and the upper portion having a second minimum horizontal width in the first horizontal direction that is greater than the first minimum horizontal width; A channel pattern comprising a first end connected to the bit line and a second end opposite to a first conductive pattern connected to the contact plug and extending in a vertical direction, the channel pattern being disposed between the word line and the back gate electrode; as well as A capacitor includes a lower electrode connected to a fourth conductive pattern of the contact plug, an upper electrode on the lower electrode, and a capacitor dielectric layer disposed between the lower electrode and the upper electrode. The boundary between the lower and upper parts of the contact isolation insulating layer is located at a vertical level that is below the upper surface of the third conductive pattern and above the lower surface of the third conductive pattern.

12. The semiconductor memory device of claim 11, wherein, The contact isolation insulation layer includes a main isolation insulation layer and a sub-isolation insulation layer. The main isolation insulation layer includes a first portion having a first minimum horizontal width in the first horizontal direction and a second portion on the first portion having a third minimum horizontal width in the first horizontal direction that is less than the first minimum horizontal width. The sub-isolation insulation layer is disposed between the upper partial portion of the contact plug and the second portion of the main isolation insulation layer. The upper surface of the main insulating layer, the upper surface of the sub-insulating layer, and the upper surface of the fourth conductive pattern form a coplanar surface.

13. The semiconductor memory device of claim 12, wherein, The sub-isolation insulation layer extends from the region between the fourth conductive pattern and the main isolation insulation layer to the region between the third conductive pattern and the main isolation insulation layer.

14. The semiconductor memory device of claim 13, wherein, The lower surface of the sub-isolation insulating layer is disposed at a vertical level below the upper surface of the third conductive pattern and above the lower surface of the third conductive pattern.

15. The semiconductor memory device of claim 13, wherein, A portion of the lower surface of the sub-isolation insulating layer is adjacent to a first portion of the main isolation insulating layer, and a portion of the lower surface of the sub-isolation insulating layer contacts the third conductive pattern.

16. The semiconductor memory device of claim 13, wherein: The sub-insulating layer has a ring shape in the plan view. The inner surface of the sub-insulating layer covers the side surface of the second portion of the main insulating layer, and The upper part of the outer surface of the sub-isolation insulating layer contacts the fourth conductive pattern, and the lower part of the outer surface of the sub-isolation insulating layer contacts the third conductive pattern.

17. The semiconductor memory device of claim 12, wherein: The contact isolation insulation layer further includes an interface insulation layer disposed between the main isolation insulation layer and the sub-isolation insulation layer. Each of the main insulating layer and the sub-insulating layer comprises a nitride, and The interface insulating layer comprises oxides.

18. A semiconductor memory device, comprising: Bit line, which extends in the first horizontal direction; Multiple contact plugs, each comprising a first conductive pattern and a second conductive pattern of semiconductor material, and each comprising a third conductive pattern and a fourth conductive pattern of metal base material, are stacked sequentially. Multiple channel patterns, each channel pattern being disposed between the bit line and a corresponding first conductive pattern of one of the multiple contact plugs, and extending in the vertical direction; Multiple word lines and multiple back gate electrodes, each of the multiple word lines and multiple back gate electrodes extending in a second horizontal direction perpendicular to the first horizontal direction between the bit lines and the multiple contact plugs, and arranged to be separated from each other, having multiple channel patterns between the multiple word lines and the multiple back gate electrodes; A contact isolation insulating layer surrounds the plurality of contact plugs on the plurality of channel patterns, the plurality of word lines, and the plurality of back gate electrodes. The contact isolation insulating layer includes a main isolation insulating layer and a plurality of sub-isolation insulating layers. The main isolation insulating layer includes a plurality of first portions and a plurality of second portions. Each first portion is located at a first height above the bit lines and has a first minimum horizontal width in the first horizontal direction between two adjacent channel patterns. Each second portion is located at a second height above the bit lines and below the first height and has a second minimum horizontal width greater than the first minimum horizontal width between two adjacent channel patterns. Each second portion is located on a corresponding first portion. The plurality of sub-isolation insulating layers are disposed between an upper partial portion of each of the plurality of contact plugs and a second portion of the main isolation insulating layer. The plurality of capacitors include a plurality of lower electrodes respectively connected to a fourth conductive pattern of the plurality of contact plugs, an upper electrode on the plurality of lower electrodes, and a capacitor dielectric layer disposed between the plurality of lower electrodes and the upper electrode. The plurality of sub-isolation insulating layers contact the upper portion of the third conductive pattern of each of the plurality of contact plugs, and also contact the fourth conductive pattern.

19. The semiconductor memory device of claim 18, wherein: The upper surface of the main insulating layer, the upper surface of each of the plurality of sub-insulating layers, and the upper surface of the fourth conductive pattern form a coplanar surface. The plurality of sub-isolation insulating layers extend from the region between the fourth conductive pattern and the main isolation insulating layer to the region between the third conductive pattern and the main isolation insulating layer, and The lower surface of each of the plurality of sub-isolation insulating layers is disposed at a vertical horizontal position below the upper surface of the third conductive pattern and above the lower surface of the third conductive pattern.

20. The semiconductor memory device of claim 18, wherein: The second portion of the main insulating layer includes at least one gap or slit, and The plurality of sub-insulating layers fill the at least one gap or slit.

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