An otp memory and a method of manufacturing the same

Abstract

The application relates to the field of semiconductor technology and discloses an OTP memory and a preparation method thereof, which comprises a first metal layer, a core structure layer and a second metal layer which are sequentially stacked from bottom to top, the core structure layer comprises alternately stacked insulating dielectric film layers and metal film layers, the number of the insulating dielectric film layers is at least two, and the number of the metal film layers is at least one; and the edge of the core structure layer is in a non-linear shape in the vertical direction. The number of the insulating dielectric film layers in the core structure layer is at least two, the insulating dielectric film layers can disperse the voltage applied on the OTP memory, can significantly increase and accurately control the breakdown voltage, and can reduce the distribution of the breakdown voltage. The edge of the core structure layer is in a non-linear shape, the metal film layers can play a role in protecting the insulating dielectric located above the metal film layers, can reduce the metal back-sputtering deposition and etching damage at the edge of the insulating dielectric layer in the etching process, and can improve the breakdown voltage and yield of the OTP memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an OTP memory and a method for its fabrication. Background Technology

[0002] OTP (One-Time Programmable) memory is a special type of non-volatile memory that can only be programmed once; once programmed, the data is permanently valid. Anti-fuse OTP devices are based on the breakdown of an insulating dielectric (oxide). Before programming, they are in a high-resistance state, and after programming, they are in a low-resistance state, characterized by high security and low power consumption.

[0003] Currently, the structure of antifuse type OTP memory is metal electrode 1 / insulating medium / metal electrode 2, and the target breakdown voltage is achieved by adjusting the thickness of the insulating medium. However, the following problems exist: as the thickness of the insulating medium increases, the exposed area at the edge of the insulating medium also increases, thereby increasing the risk of edge etching damage and metal backsplash deposition. This results in larger fluctuations in the non-breakdown resistance, and breakdown channels are more likely to form at the edges, leading to a lower and more volatile breakdown voltage. Ultimately, it is difficult to obtain OTP memory with a high breakdown voltage.

[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide an OTP memory and a method for fabricating the same, so as to improve the breakdown voltage and yield of the OTP memory.

[0006] To address the aforementioned technical problems, this application provides an OTP memory, comprising:

[0007] The first metal layer, the core structure layer, and the second metal layer are stacked sequentially from bottom to top. The core structure layer includes alternating layers of insulating dielectric film and metal film. The number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one.

[0008] The edges of the core structural layer are non-linear in the vertical direction.

[0009] Optionally, it also includes:

[0010] The bottom metal electrode is located on the lower surface of the first metal layer;

[0011] The top metal electrode is located on the upper surface of the second metal layer.

[0012] Optionally, it also includes:

[0013] A hard mask layer located on the upper surface of the second metal layer.

[0014] Optionally, the thickness of the insulating dielectric film layer ranges from 0.5 nm to 3 nm; and / or, the thickness of the metal film layer ranges from not less than 1 nm.

[0015] Optionally, the edges of the core structural layer are serrated or stepped upwards in the vertical direction.

[0016] Optionally, the insulating dielectric film layer comprises any one or any combination of the following:

[0017] MgO layer, Al2O3 layer, HfO2 layer, MgAlO layer, CuO layer, TiO2 layer, Ta2O5 layer, ZnO layer;

[0018] And / or, the metal film layer comprises any one or any combination of the following:

[0019] Fe layer, Co layer, Ni layer and alloy layer formed by any combination of Fe, Co and Ni, as well as Ta layer, W layer, Mg layer and Al layer.

[0020] Optionally, the thickness of each insulating dielectric film layer is equal.

[0021] This application also provides a method for fabricating an OTP memory, comprising:

[0022] Prepare the first metal layer;

[0023] A core structure layer is prepared on the upper surface of the first metal layer; the core structure layer includes alternating layers of insulating dielectric film and metal film, wherein the number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one.

[0024] A second metal layer is prepared on the upper surface of the core structural layer;

[0025] The second metal layer, the core structure layer, and the first metal layer are etched, and the edge of the core structure layer is non-linear in the vertical direction.

[0026] Optionally, fabricating a core structure layer on the upper surface of the first metal layer includes:

[0027] Step S11: Using the first metal layer as the target metal layer, deposit an insulating dielectric film layer on the upper surface of the target metal layer;

[0028] Step S12: Deposit a metal film layer on the upper surface of the insulating dielectric film layer, use the metal film layer as the new target metal layer, and proceed to step S11 until the number of metal film layers reaches the first preset number of layers.

[0029] Step S13: Deposit an insulating dielectric film on the upper surface of the metal film layer.

[0030] Optionally, fabricating a core structure layer on the upper surface of the first metal layer includes:

[0031] Step S21: Using the first metal layer as the target metal layer, oxidize the target metal layer to form an insulating dielectric film layer; the oxidation thickness of the target metal layer is less than the thickness of the target metal layer.

[0032] Step S22: Deposit a metal film layer on the insulating dielectric film layer, and use the metal film layer as a new target metal layer, and proceed to step S21 until the number of layers of the insulating dielectric film layer reaches the second preset number of layers.

[0033] The OTP memory provided in this application includes: a first metal layer, a core structure layer, and a second metal layer stacked sequentially from bottom to top, wherein the core structure layer includes alternating layers of insulating dielectric film and metal film, the number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one; the edge of the core structure layer is non-linear in the vertical direction.

[0034] As can be seen, the OTP memory of this application includes a first metal layer, a core structure layer, and a second metal layer. The core structure layer includes alternating layers of insulating dielectric film and metal film. The number of insulating dielectric film layers is at least two. The insulating dielectric film layers can disperse the voltage applied to the OTP memory, which can not only significantly increase and precisely control the breakdown voltage, but also reduce the breakdown voltage distribution. In addition, the edge of the core structure layer in the OTP memory of this application is non-linear. The metal film layer can protect the insulating dielectric layer above the metal film layer, which can reduce metal backsplashing and etching damage at the edge of the insulating dielectric layer during etching, thereby improving the breakdown voltage and yield of the OTP memory.

[0035] In addition, this application also provides a preparation method with the above advantages. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of the structure of an OTP memory provided in this application embodiment. Figure 1 ;

[0038] Figure 2 for Figure 1 Schematic diagram of the equivalent resistance of the OTP memory;

[0039] Figure 3 A schematic diagram of the structure of an OTP memory provided in this application embodiment. Figure 2 ;

[0040] Figure 4 for Figure 3 A magnified view of a portion of region A at the edge of the central core structural layer;

[0041] Figure 5 This is a comparison diagram of the breakdown voltage of the OTP memory in this application and that of the OTP memory in the prior art;

[0042] Figure 6 This is a comparison chart of the coefficient of variation of the OTP memory in this application and the OTP memory in the prior art;

[0043] Figure 7 A flowchart illustrating a method for fabricating an OTP memory provided in an embodiment of this application;

[0044] Figures 8 to 11 A fabrication process flow for an OTP memory provided in this application embodiment Figure 1 ;

[0045] Figures 12 to 15 A fabrication process flow for an OTP memory provided in this application embodiment Figure 2 ;

[0046] In the figure, 1 is the first metal layer, 2 is the core structure layer, 3 is the second metal layer, 4 is the bottom metal electrode, 5 is the top metal electrode, 6 is the hard mask layer, 7 is the protective layer, 8 is the dielectric layer, 21 is the insulating dielectric film layer, and 22 is the metal film layer. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0049] As described in the background section, the current structure of antifuse type OTP memory is metal electrode 1 / insulating medium / metal electrode 2, and the breakdown voltage of OTP memory is relatively small.

[0050] In view of this, this application provides an OTP memory, please refer to... Figures 1 to 2 It can include:

[0051] The first metal layer 1, the core structure layer 2, and the second metal layer 3 are stacked sequentially from bottom to top. The core structure layer 2 includes alternating layers of insulating dielectric film layer 21 and metal film layer 22. The number of insulating dielectric film layer 21 layers is at least two, and the number of metal film layer 22 layers is at least one.

[0052] The edges of the core structural layer 2 are non-linear in the vertical direction.

[0053] It should be noted that in the core structure layer 2, the first and last layers are both insulating dielectric film layers 21 in the direction from bottom to top.

[0054] The number of insulating dielectric film layers 21 can be two, three, four, etc., and no specific limitation is made in this embodiment.

[0055] In this embodiment, the material of the insulating dielectric film layer 21 is not specifically limited and can be selected at will. As one possible implementation, the insulating dielectric film layer 21 includes, but is not limited to, any one or any combination of the following:

[0056] Films formed from MgO layers, Al2O3 layers, HfO2 layers, MgAlO layers, CuO layers, TiO2 layers, Ta2O5 layers, ZnO layers, and other resistive switching materials.

[0057] It should be noted that the thickness of the insulating dielectric film layer 21 is not limited in this embodiment and depends on the circumstances. As one possible implementation, the thickness of the insulating dielectric film layer 21 ranges from 0.5nm to 3nm. For example, the thickness of the insulating dielectric film layer 21 can be 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, etc.

[0058] If the thickness of the insulating dielectric film 21 is too small, the insulating dielectric film 21 is easily broken down; if the thickness of the insulating dielectric film 21 is too large, the breakdown voltage is too high, which will cause the breakdown voltage of the batch of OTP memory to be discrete and have poor uniformity.

[0059] The function of the metal film layer 22 is to separate two adjacent insulating dielectric film layers 21. The function of the insulating dielectric film layer 21 is to distribute the voltage applied to the OTP memory. Since the number of insulating dielectric film layers 21 increases to more than two layers, the breakdown voltage can be increased.

[0060] In this embodiment, the insulating dielectric film layer 21 of the OTP memory has a high resistance, for Figure 1 The OTP memory shown here, assuming the resistances of the insulating dielectric film layer 21 are R1, R2, and R3, then the equivalent resistance is as follows: Figure 2 As shown, this serves to disperse the voltage.

[0061] When a certain insulating dielectric film layer 21 is broken down, the remaining insulating dielectric film layers 21 will also be broken down due to the increased voltage drop they experience. Therefore, the OTP memory in this application will not have an intermediate state in the resistive state and can be used as an OTP device.

[0062] It should be noted that the material of the metal film layer 22 is not limited in this embodiment and can be selected at will. As one possible implementation, the metal film layer 22 includes, but is not limited to, any one or any combination of the following:

[0063] Magnetic metal material films such as Fe layer, Co layer, Ni layer and alloy layer formed by any combination of Fe, Co and Ni, as well as non-magnetic metal material films such as Ta layer, W layer, Mg layer and Al layer.

[0064] It should be noted that the thickness of the metal film layer 22 is not limited in this embodiment and depends on the circumstances. As one possible implementation, the thickness of the metal film layer 22 is not less than 1 nm. For example, the thickness of the metal film layer 22 can be 1 nm, 1.2 nm, 1.5 nm, 2 nm, etc.

[0065] The thickness of the metal film layer 22 is not less than 1 nm. On the one hand, this ensures the uniformity of the metal film layer 22, and on the other hand, it allows the core structure layer to form a sufficiently high step height, which provides better protection for the upper insulating dielectric film layer 21.

[0066] It should be noted that the material of the first metal layer 1 is not limited in this embodiment and can be selected by the user. For example, the first metal layer 1 can be a Mg layer or an Al layer, or it can be any one or any combination of the following: an Fe layer, a Co layer, a Ni layer, and an alloy layer formed by any combination of Fe, Co, and Ni.

[0067] It should also be noted that the material of the second metal layer 3 is not limited in this embodiment and can be selected by the user.

[0068] As one possible implementation, the second metal layer 3 includes, but is not limited to, any one or any combination of the following:

[0069] Magnetic metal material films such as Fe layer, Co layer, Ni layer and alloy layer formed by any combination of Fe, Co and Ni, as well as non-magnetic metal material films such as Ta layer, W layer, Mg layer and Al layer.

[0070] The magnetic layers composed of magnetic metallic materials such as the Fe layer, Co layer, Ni layer, and alloy layers formed by any combination of Fe, Co, and Ni can have their easy magnetization axis pointing in-plane, out-of-plane, or in any direction.

[0071] In this embodiment, the edge of the core structure layer 2 is non-linear in the vertical direction because the lateral etching rates of the metal film layer 22 and the insulating dielectric film layer 21 are different, i.e., the etching selection is different. The dielectric film layer has a fast etching rate, while the metal film layer 22 has a slow etching rate. The relative etching rate can be adjusted by the etching angle, resulting in the non-linear shape of the edge of the core structure layer 2 in the vertical direction. The slower etching of the metal film layer 22 can reduce etching damage and metal backsplash deposition on the insulating dielectric film layer 21, thereby improving the breakdown voltage and device yield.

[0072] It should be noted that the edge shape of the core structure layer 2 is not limited in this embodiment and can be determined as appropriate. As one possible implementation, the edge of the core structure layer 2 is serrated or stepped upwards in the vertical direction.

[0073] As one possible implementation, the OTP memory may further include a protective layer 7 located on the sides of the first metal layer 1, the core structure layer 2, and the second metal layer 3. On the one hand, the protective layer 7 can protect the sidewalls of the first metal layer 1, the core structure layer 2, and the second metal layer 3. On the other hand, when the dielectric layer 8 is SiO2, it can prevent the sidewalls of the first metal layer 1, the core structure layer 2, and the second metal layer 3 from oxidation.

[0074] The first metal layer 1, the core structure layer 2, and the second metal layer 3 may deform, generating internal stress. The protective layer 7 can act as a buffer.

[0075] The materials of the protective layer 7 include, but are not limited to, SiN, SiC, SiO2, Al2O3, MgO, etc.

[0076] As one possible implementation, the OTP memory may also include a dielectric layer 8 located on the surface of the protective layer 7. The material of the dielectric layer 8 includes, but is not limited to, SiN, SiC, SiO2, Al2O3, MgO, etc.

[0077] In this embodiment of the OTP memory, the first metal layer 1 can also serve as the bottom metal electrode 4, the second metal layer 3 can also serve as the top metal electrode 5, and the second metal layer 3 can also serve as a hard mask during the etching process.

[0078] This embodiment of the OTP memory includes a first metal layer 1, a core structure layer 2, and a second metal layer 3. The core structure layer 2 includes alternating layers of insulating dielectric film 21 and metal film 22. The insulating dielectric film 21 has at least two layers. The insulating dielectric film 21 can disperse the voltage applied to the OTP memory, which can not only significantly increase and precisely control the breakdown voltage, but also reduce the breakdown voltage distribution. In addition, the edge of the core structure layer 2 in this embodiment of the OTP memory is non-linear. The metal film 22 can protect the insulating dielectric above the metal film 22, which can reduce metal backsplashing and etching damage at the edge of the insulating dielectric film 21 during etching, thereby improving the breakdown voltage and yield of the OTP memory.

[0079] Furthermore, under the same breakdown voltage, the linear increase in initial resistance of the series structure in this embodiment is easier to control artificially than the exponential increase in initial resistance by increasing the thickness of the insulating medium in the prior art. In addition, the OTP memory in this embodiment can also reduce process requirements, can be compatible with existing processes to achieve high breakdown voltage, and reduce costs.

[0080] Based on any of the above embodiments, in one embodiment of this application, such as Figure 3 As shown, the OTP memory may also include:

[0081] Bottom metal electrode 4 located on the lower surface of the first metal layer 1;

[0082] The top metal electrode 5 is located on the upper surface of the second metal layer 3.

[0083] In this embodiment, the materials of the bottom metal electrode 4 and the top metal electrode 5 are not limited and can be set by the user.

[0084] Based on any of the above embodiments, in one embodiment of this application, such as Figure 3 As shown, the OTP memory may also include:

[0085] The hard mask layer 6 is located on the upper surface of the second metal layer 3.

[0086] The hard mask layer 6 can be used as a mask for etching the first metal layer 1, the core structure layer 2, and the second metal layer 3.

[0087] like Figure 1 and Figure 3 As shown, when the edge of the core structure layer 2 has an upward step shape in the vertical direction, the width W of the step can range from 1nm to 5nm, such as... Figure 4As shown. In the direction from bottom to top, the first insulating dielectric film layer 21 and the first metal film layer 22 can be regarded as the first stacking cycle, the second insulating dielectric film layer 21 and the second metal film layer 22 can be regarded as the second stacking cycle, and so on. In each stacking cycle, the edges of the insulating dielectric film layer 21 and the metal film layer 22 are flush or almost flush.

[0088] Based on any of the above embodiments, in one embodiment of this application, the thickness of each insulating dielectric film layer 21 may be equal.

[0089] When the thickness of each insulating dielectric film layer 21 is equal, the voltage division on each insulating dielectric film layer 21 can be equal, making it easy to estimate the overall breakdown voltage of the OTP device. Furthermore, it can simplify the fabrication method of the OTP memory, allowing the use of a cycle process.

[0090] In other embodiments of this application, the thickness of each insulating dielectric film layer 21 may be similar.

[0091] In other embodiments of this application, the thickness of each insulating dielectric film layer 21 may be unequal, or the thickness may gradually increase or decrease from bottom to top, etc., which is not limited in this application.

[0092] The breakdown voltage and coefficient of variation of the OTP memory in this application and the OTP memory in the prior art are compared below. The breakdown voltages of different samples are as follows: Figure 5 As shown, the horizontal axis represents the sample number, and the vertical axis represents the breakdown voltage. The coefficient of variation for different samples is as follows: Figure 6 As shown, the horizontal axis represents the sample number, and the vertical axis represents the coefficient of variation.

[0093] Depend on Figure 5 and Figure 6 It is known that the breakdown voltage of the OTP memory (Sample 5) of the present invention is 5.4 times that of the OTP memory 1 (Sample 1) in the prior art and 3.2 times that of the OTP memory 4 (Sample 4) in the prior art, while maintaining a low coefficient of variation (CV).

[0094] In the prior art, the OTP memory 1 consists of: metal electrode 1 / insulating medium (10A) / metal electrode 2; breakdown voltage V1, coefficient of variation CV1;

[0095] In the prior art, the OTP memory 2 consists of: metal electrode 1 / insulating medium (25A) / metal electrode 2; breakdown voltage V2, coefficient of variation CV2;

[0096] In the prior art, the OTP memory 3 consists of: metal electrode 1 / insulating medium (50A) / metal electrode 2; breakdown voltage V3, coefficient of variation CV3;

[0097] In the prior art, the OTP memory 4 consists of: metal electrode 1 / insulating medium (60A) / metal electrode 2; breakdown voltage V4, coefficient of variation CV4;

[0098] In this application, the OTP memory 5 consists of: a first metal layer / an insulating dielectric film layer 1 (20A) / a metal film layer 1 / an insulating dielectric film layer 2 (20A) / a metal film layer 2 / an insulating dielectric film layer 3 (20A) / a second metal layer; a breakdown voltage V5 and a coefficient of variation CV5.

[0099] This application also provides a method for fabricating an OTP memory; please refer to [reference needed]. Figure 7 ,include:

[0100] Step S101: Prepare the first metal layer.

[0101] Step S102: Prepare a core structure layer on the upper surface of the first metal layer; the core structure layer includes alternating layers of insulating dielectric film and metal film, wherein the number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one.

[0102] This embodiment does not limit the manufacturing process of the core structure layer. The following embodiments will describe two cases separately.

[0103] Step S103: Prepare a second metal layer on the upper surface of the core structure layer.

[0104] Step S104: Etch the second metal layer, the core structure layer and the first metal layer, wherein the edge of the core structure layer is non-linear in the vertical direction.

[0105] In one embodiment of this application, the second metal layer can be used as a hard mask layer for etching.

[0106] In other embodiments of this application, a hard mask layer may be deposited on the second metal layer, then patterned, the hard mask layer etched, and then the second metal layer, the core structure layer and the first metal layer etched.

[0107] It should be noted that after etching the second metal layer, the core structure layer and the first metal layer, the process may further include: fabricating a protective layer on the sides of the second metal layer, the core structure layer and the first metal layer, then filling the sides of the protective layer with a dielectric layer, and then using CMP (Chemical Mechanical Polishing) to grind down to the upper surface of the hard mask layer.

[0108] The OTP memory fabricated in this embodiment includes a first metal layer, a core structure layer, and a second metal layer. The core structure layer includes alternating layers of insulating dielectric film and metal film. The number of insulating dielectric film layers is at least two. The insulating dielectric film layers can disperse the voltage applied to the OTP memory, which can not only significantly increase and precisely control the breakdown voltage, but also reduce the breakdown voltage distribution. In addition, the edge of the core structure layer in this embodiment of the OTP memory is non-linear. The metal film layer can protect the insulating dielectric layer above the metal film layer, which can reduce etching damage and metal backsplash deposition of the insulating dielectric layer, thereby improving the breakdown voltage and yield of the OTP memory.

[0109] Furthermore, under the same breakdown voltage, the linear increase in initial resistance of the series structure in this embodiment is easier to control artificially than the exponential increase in initial resistance by increasing the thickness of the insulating medium in the prior art. In addition, the OTP memory in this embodiment can also reduce process requirements, can be compatible with existing processes to achieve high breakdown voltage, and reduce costs.

[0110] Based on the above embodiments, in one embodiment of this application, the preparation of the first metal layer may include fabricating the first metal layer on the bottom metal layer; after polishing the dielectric layer, it may further include depositing a top metal layer on the surface of the hard mask layer, the protective layer and the dielectric layer.

[0111] Based on any of the above embodiments, in one embodiment of this application, the method for preparing an OTP memory includes:

[0112] Step S201: Create a first metal layer on the bottom metal layer.

[0113] Step S202: Using the first metal layer as the target metal layer, deposit an insulating dielectric film layer on the upper surface of the target metal layer.

[0114] Step S203: Deposit a metal film layer on the upper surface of the insulating dielectric film layer, use the metal film layer as the new target metal layer, and proceed to step S202 until the number of metal film layers reaches the first preset number of layers.

[0115] It should be noted that the first preset number of layers is an integer greater than or equal to 1. In this embodiment, the specific first preset number of layers is not limited and can be set by the user.

[0116] Step S204: Deposit an insulating dielectric film layer on the upper surface of the metal film layer to obtain the core structure layer.

[0117] Step S205: Fabricate a second metal layer and a hard mask layer on the upper surface of the core structure layer.

[0118] like Figure 8As shown, the bottom metal electrode 4 is sequentially stacked with a first metal layer 1, a core structure layer 2, a second metal layer 3, and a hard mask layer 6.

[0119] Step S206: After patterning, the hard mask layer 6 and the core structure layer 2 are etched. During the etching process, the relative etching rate is adjusted by the etching angle, forming a non-linear boundary at the edge of the core structure layer 2. The etching terminates at the bottom metal electrode 4. Figure 9 As shown.

[0120] Step S207, as follows Figure 10 As shown, a protective layer 7 is covered and filled with a dielectric material to form a dielectric layer 8;

[0121] Step S208, as follows Figure 11 As shown, CMP grinding is performed to smooth down to the hard mask layer 6, and then the top metal electrode 5 is fabricated.

[0122] Based on any of the above embodiments, in one embodiment of this application, the method for preparing an OTP memory includes:

[0123] Step S301, as follows Figure 12 As shown, a first metal layer 1 is fabricated on the bottom metal electrode 4, wherein the material of the first metal layer 1 can be Al, Mg, etc.

[0124] Step S302: Using the first metal layer 1 as the target metal layer, oxidize the target metal layer to form an insulating dielectric film layer; the oxidation thickness of the target metal layer is less than the thickness of the target metal layer.

[0125] Step S303: Deposit a metal film layer on the insulating dielectric film layer, and use the metal film layer as a new target metal layer, and proceed to step S302 until the number of layers of the insulating dielectric film layer reaches the second preset number of layers, forming the core structure layer 2.

[0126] It should be noted that the second preset number of layers is an integer greater than or equal to 2. In this embodiment, the specific number of the second preset layers is not limited and can be set by the user.

[0127] Taking the second preset layer number as an example, such as Figures 13 to 15 As shown, the first metal layer 1 is first partially oxidized to form the first insulating dielectric film layer 21. Then, a metal film layer 22 is deposited and partially oxidized to form the second insulating dielectric film layer 21. Then, a metal film layer 22 is deposited and partially oxidized to form the third insulating dielectric film layer 21.

[0128] Step S304: Fabricate a second metal layer and a hard mask layer on the upper surface of the core structure layer.

[0129] Step S305: After patterning, the hard mask layer and the core structure layer are etched. During the etching process, the relative etching rate is adjusted by the etching angle to form a non-linear boundary at the edge of the core structure layer. The etching ends at the bottom metal electrode.

[0130] Step S306: Cover with a protective layer and fill with dielectric material to form a dielectric layer;

[0131] Step S307: Perform CMP grinding to smooth down to the hard mask layer, and then fabricate the top metal electrode.

[0132] Steps S304 to S307 can be referred to the above embodiments, and will not be described in detail here.

[0133] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0134] The OTP memory and its fabrication method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the solution and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. An OTP memory, characterized in that, include: The first metal layer, the core structure layer, and the second metal layer are stacked sequentially from bottom to top. The core structure layer includes alternating layers of insulating dielectric film and metal film. The number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one. The edges of the core structural layer are non-linear in the vertical direction.

2. The OTP memory as described in claim 1, characterized in that, Also includes: The bottom metal electrode is located on the lower surface of the first metal layer; The top metal electrode is located on the upper surface of the second metal layer.

3. The OTP memory as described in claim 1, characterized in that, Also includes: A hard mask layer located on the upper surface of the second metal layer.

4. The OTP memory as described in claim 1, characterized in that, The thickness of the insulating dielectric film is in the range of 0.5 nm to 3 nm; and / or the thickness of the metal film is not less than 1 nm.

5. The OTP memory as described in claim 1, characterized in that, The edges of the core structural layer are serrated or stepped upwards in the vertical direction.

6. The OTP memory as described in claim 1, characterized in that, The insulating dielectric film layer includes any one or any combination of the following: MgO layer, Al2O3 layer, HfO2 layer, MgAlO layer, CuO layer, TiO2 layer, Ta2O5 layer, ZnO layer; And / or, the metal film layer comprises any one or any combination of the following: Fe layer, Co layer, Ni layer and alloy layer formed by any combination of Fe, Co and Ni, as well as Ta layer, W layer, Mg layer and Al layer.

7. The OTP memory according to any one of claims 1 to 6, characterized in that, The thickness of each insulating dielectric film layer is equal.

8. A method for fabricating an OTP memory, characterized in that, include: Prepare the first metal layer; A core structure layer is prepared on the upper surface of the first metal layer; The core structure layer includes alternating layers of insulating dielectric film and metal film, wherein the number of insulating dielectric film layers is at least two, and the number of metal film layers is at least one. A second metal layer is prepared on the upper surface of the core structural layer; The second metal layer, the core structure layer, and the first metal layer are etched, and the edge of the core structure layer is non-linear in the vertical direction.

9. The method for preparing an OTP memory as described in claim 8, characterized in that, The preparation of a core structure layer on the upper surface of the first metal layer includes: Step S11: Using the first metal layer as the target metal layer, deposit an insulating dielectric film layer on the upper surface of the target metal layer; Step S12: Deposit a metal film layer on the upper surface of the insulating dielectric film layer, use the metal film layer as the new target metal layer, and proceed to step S11 until the number of metal film layers reaches the first preset number of layers. Step S13: Deposit an insulating dielectric film on the upper surface of the metal film layer.

10. The method for preparing an OTP memory as described in claim 8, characterized in that, The preparation of a core structure layer on the upper surface of the first metal layer includes: Step S21: Using the first metal layer as the target metal layer, oxidize the target metal layer to form an insulating dielectric film layer; the oxidation thickness of the target metal layer is less than the thickness of the target metal layer. Step S22: Deposit a metal film layer on the insulating dielectric film layer, and use the metal film layer as a new target metal layer, and proceed to step S21 until the number of layers of the insulating dielectric film layer reaches the second preset number of layers.

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