Memory structure and method of forming, writing, erasing, reading
By designing a structure in NOR Flash devices with the first and second sub-gates arranged in close succession and the drain regions located on both sides of the word line, the problems of large memory structure area and low integration density are solved, achieving higher integration density and lower over-erase probability, and simplifying the process flow.
CN122161098APending Publication Date: 2026-06-05SEMICON MFG INT (BEIJING) CORP +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
Technical Problem
Existing NOR Flash devices suffer from problems such as large memory structure area, low integration density, and high probability of over-erasing.
Method used
Design a memory structure in which the first sub-gate and the second sub-gate are arranged in close succession, and the drain region is located on both sides of the word line. The drain region is reused as the source region by applying voltage, which simplifies the process flow and reduces the area of the memory structure.
Benefits of technology
It reduces the area of the memory structure, increases integration density, reduces the probability of over-erasing, simplifies the process flow, and improves memory performance.
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Smart Images
Figure CN122161098A_ABST
Abstract
A memory structure and a forming method, a writing method, an erasing method and a reading method thereof, wherein the memory structure comprises: a substrate with a vertical cross arrangement of bit line direction and word line direction, the substrate comprising a plurality of active regions arranged in parallel along the bit line direction and a plurality of isolation regions between the active regions; a plurality of mutually separated storage gates on the active regions, the storage gates comprising a first sub-storage gate and a second sub-storage gate arranged in close proximity, the storage gates crossing the active regions and arranged in parallel along the bit line direction; and drain regions on both sides of the storage gates, the drain regions arranged in parallel along the bit line direction. The first sub-storage gate and the second sub-storage gate are arranged in close proximity, and the drain regions are located on both sides of the word line, thereby saving the structure of the source region between the first sub-storage gate and the second sub-storage gate. The drain regions can be used as the source region by applying a voltage in the subsequent process, thereby reducing the area of the memory structure and facilitating the integration of the memory structure while ensuring the normal operation of the memory structure.
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