Vertical structure double heterojunction insulated gate diamond field effect transistor and preparation method thereof

Abstract

The application discloses a vertical structure double-heterojunction insulated gate diamond field effect transistor and a preparation method thereof, and relates to the technical field of diamond field effect transistors. The vertical structure double-heterojunction insulated gate diamond field effect transistor comprises a P-type diamond substrate, an N-type gallium oxide drift layer located on the P-type diamond substrate, P-type diamond located in the N-type gallium oxide drift layer close to both ends of the device, an N-type gallium oxide epitaxial layer located on the P-type diamond and the N-type gallium oxide drift layer, N+ square high-doped regions located in the N-type gallium oxide epitaxial layer at both ends of the device, a P-type diamond epitaxial layer located on the N-type gallium oxide epitaxial layer between the N+ square high-doped regions, a source electrode located on the N+ square high-doped regions at both ends of the device, an Al2O3 deposition layer located on the P-type diamond epitaxial layer, a gate electrode located on the Al2O3 deposition layer in a middle region, and a drain electrode located on a lower surface of the P-type diamond substrate. The vertical structure double-heterojunction insulated gate diamond field effect transistor has the advantages of a normally-off characteristic, a high breakdown voltage, a low on-resistance and excellent heat dissipation capacity.

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