A method and system for precise position marking of a wafer

Abstract

The present application relates to wafer marking technical field, disclose a kind of accurate position marking method and system of wafer.Method includes: based on the requirement of graphic design system file to wafer arrangement exposure area frame and cutting;The core grain of the region where target mark position is located is moved to form blank area, and the coordinate information in blank area is obtained;Model test key is moved to blank area, and the actual mark position is calculated based on the coordinate information in blank area and the vertex coordinate of model test key, and exposure is carried out in actual mark position to form accurate position mark.In design stage, frame is arranged based on requirement, and the actual coordinate position is calculated using the coordinate of model test key as relative coordinate, accurate position calibration can be realized, and wafer area is not occupied too much, and wafer utilization is high.The method has flexibility, and can better adapt to the diversified needs of different customers for mark position.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and system for precise location marking on wafers. Specifically, it can be applied to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench transistors (trench MOSFETs), and high-voltage components (such as power management integrated circuits) and related products and processes. Background Technology

[0002] Compared to traditional wire-bonded packages, wafer-level image sensors (CIS) offer advantages such as smaller package size, lower cost, and less susceptibility to contamination of the photosensitive area during downstream assembly, and are attracting increasing attention. Because CIS products require microlens fabrication in the later stages, foundries (FABs) need to create specific marks at specific locations on the wafer for calibration in subsequent processes. However, since foundries perform shot-by-shot exposure, precise wafer marking cannot be achieved within a single exposure area.

[0003] The existing approach involves placing the Graphical Design System (GDS) file into the Model Test Key (MTK). When arranging the exposure area frames, the foundry shifts the exposure areas to create blank spaces, and then uses the MTK to expose and create markers in these blank spaces. The drawback of this approach is that the marker position is usually determined by the arrangement of the exposure area frames. However, since the MTK cannot be moved to any arbitrarily precise position, it is often impossible to achieve precise marker placement.

[0004] Therefore, there is a need to improve wafer marking methods in the existing technology. Summary of the Invention

[0005] In view of this, the purpose of this invention is to propose a method and system for precise wafer positioning. Based on the required layout framework during the design phase, the actual coordinate position is calculated using the coordinates of the model test key as the relative coordinates. This can achieve precise positioning without occupying too much wafer area, resulting in high wafer utilization.

[0006] To achieve the above objectives, embodiments of the present invention provide a method for precise location marking on a wafer, comprising the following steps: S1 arranges the exposure area framework on the wafer and cuts it according to the requirements of the graphic design system file; S2 moves the core particles in the area where the target marker is located to form a blank area and obtains the coordinate information within the blank area; S3 moves the model test key to the blank area, calculates the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key, and exposes at the actual mark position to form a precise position mark.

[0007] In some implementations, arranging and cutting the wafer exposure area framework based on the requirements of the graphic design system file includes: Two target marker positions are obtained. Based on the requirements of the graphic design system file, the exposure area framework is arranged on the wafer. The two target marker positions are symmetrically distributed on the edge of the wafer exposure area. The wafer is then cut into multiple cores.

[0008] In some implementations, the model test key structure includes two symmetrical positioning markers, with the remaining area being a virtual region.

[0009] In some implementations, the positioning mark is a center mark, and the shape of the center mark includes a cross, a triangle, or a circle.

[0010] In some implementations, a method using masks and yellow light exposure is used to form precise location markers.

[0011] In some implementations, the graphical design system file includes chip layout and circuit pattern.

[0012] In some implementations, the core is removed using photomask lithography to create blank areas.

[0013] Another aspect of the present invention provides a wafer precise positioning marking system for marking wafers on which an exposure area frame is arranged, the system comprising: The coordinate acquisition module is used to move the core of the exposure area where the target mark is located to form a blank area and acquire the coordinate information within the blank area; The coordinate calculation module is used to move the model test key to the blank area and calculate the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key.

[0014] In some implementations, it also includes a calibration module for obtaining the actual coordinate position information of the coordinate calculation module and exposing it on the wafer to form a mark.

[0015] In some implementations, the acquisition module further includes a storage unit for storing coordinate information within the blank area.

[0016] The present invention has at least the following beneficial technical effects: The method of this invention provides customers with the coordinates to which the Model Test Key (MTK) can be moved, so that the marker position is no longer completely limited by the arrangement of the exposure area frame. By calculating the relative position of its internal calibration based on the MTK coordinates and drawing the specific calibration, customers can accurately draw the layout of specific markers within the MTK using the MTK coordinates as relative coordinates. The method of this invention provides a certain degree of flexibility in marker layout, which can better adapt to the diverse needs of different customers for marker position. It enables customers to customize the precise position and layout of markers according to their specific needs for products, such as the special requirements for marker layout under different product models and application scenarios, and also better meets the market demand for customized CIS product markers.

[0017] Specifically, this invention is applicable to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench MOSFETs, and high-voltage components (such as power management integrated circuits) and related products and processes. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram illustrating an embodiment of the precise location marking method for wafers provided by the present invention; Figure 2 A schematic diagram of an embodiment of the model test key provided by the present invention; Figure 3 This is a schematic diagram of an embodiment of the precise position marking system for wafers provided by the present invention.

[0020] Explanation of reference numerals in the attached figures: 1. Model test key; 2. Positioning marker. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. For example, terms such as “length,” “width,” “upper,” “lower,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” indicate orientations or positions based on the orientations or positions shown in the accompanying drawings and are for ease of description only, and should not be construed as limiting the technical solution.

[0023] The terms "comprising" and "having," and any variations thereof, used in the specification, claims, and accompanying drawings of this invention are intended to cover non-exclusive inclusion; the terms "first," "second," etc., used in the specification, claims, and accompanying drawings are used to distinguish different objects, not to describe a particular order. "A plurality of" means two or more, unless otherwise explicitly specified.

[0024] In the description and claims of this invention and the foregoing drawings, when an element is referred to as "fixed to," "mounted to," "disposed on," or "connected to" another element, it can be located directly or indirectly on that other element. For example, when an element is referred to as "connected to" another element, it can be directly or indirectly connected to that other element.

[0025] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] The common practice in existing technologies is to move the core at the target location in an entire row, creating a blank space, and then use MTK's method to expose and create a mark in the upper left corner of the blank space. However, the drawback of this existing approach is that the size of the exposure area is fixed when the product design is completed and the frame is arranged for production, so the vertex coordinates of each exposure area are fixed. The position of the mark created by this method is determined by the frame arrangement, and it is impossible to expose and create the mark at precise coordinates.

[0027] To address the problems in existing technologies, this invention proposes a method for precise location marking on wafers, such as... Figure 1 As shown, it includes the following steps: S1 arranges the exposure area framework on the wafer and cuts it according to the requirements of the graphic design system file; S2 moves the core particles in the area where the target marker is located to form a blank area and obtains the coordinate information within the blank area; S3 moves the model test key to the blank area, calculates the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key, and exposes at the actual mark position to form a precise position mark.

[0028] Furthermore, in S1, the wafer layout and cutting of the exposure area framework based on the requirements of the graphic design system file includes: Two target marker positions are obtained. Based on the requirements of the Graphic Design System (GDS) file, the exposure area framework is arranged on the wafer. The two target marker positions are symmetrically distributed along the edge of the wafer exposure area. The wafer is then diced into multiple chips. Specifically, the Graphic Design System file is first interpreted and preprocessed. Given the layered architecture of the GDS file, it is meticulously disassembled and analyzed at different levels. The type of circuit element corresponding to each layer is accurately identified, such as defining the unique graphic data for metal interconnect layers, active area layers, and insulating layers. Key geometric shapes (rectangles, polygons, etc.) and corresponding attributes (such as metal layer thickness, resistivity, active area doping concentration, etc.) are extracted and converted into a data format that can be directly referenced in the subsequent exposure area framework arrangement. Next, according to the circuit layout data extracted from the GDS file, the chip pattern is laid out. In the wafer coordinate system, based on the desired arrangement direction of the chip on the wafer, the starting coordinates and orientation angle of each exposure area framework are determined. Finally, by closely referring to the layout of the exposed area framework and the chip layout in the GDS file, the dicing positions between chips are precisely located to complete the wafer cutting.

[0029] Furthermore, such as Figure 2 The diagram illustrates an embodiment of the model test key provided by this invention. The model test key 1 structure includes two symmetrical positioning marks 2, with the remaining area being a dummy pattern. The dummy pattern is the portion of the MTK (Metal Transport Technology) excluding the two positioning marks, and is typically composed of a series of dummy patterns. In some embodiments, the positioning marks are central marks, and the shape of the central mark includes a cross, a triangle, or a circle. Preferably, the central mark is cross-shaped. Cross-shaped marks have high contrast in optical inspection systems and can be quickly and accurately identified by the device in both bright-field and dark-field optical inspection modes. This high recognizability allows the cross-shaped mark to stand out in complex wafer surface environments, reducing alignment errors caused by blurred or difficult-to-identify marks.

[0030] Furthermore, using masks and photolithography to create precise location markers allows for accurate replication of the shape and size of these markers on the wafer, which is crucial for manufacturing high-precision chips. For example, in manufacturing advanced processor chips, precise location markers ensure alignment accuracy between different circuit layers, reducing chip performance degradation or failure due to positional deviations.

[0031] Furthermore, the graphic design system files include chip layout and circuit patterns.

[0032] Further, the core particles are removed using photolithography to create blank areas. The core particles at the target markings are precisely located, and a mask is designed using EDA software. The area corresponding to the core particle is opaque, creating a quartz substrate mask. A silicon wafer is selected, cleaned with RCA, and then coated with photoresist according to the process requirements, followed by spin coating and soft baking. The wafer is loaded into the photolithography machine, and using an optical alignment system, it is finely adjusted according to the existing markings, with alignment errors at the sub-micron level. Exposure is performed using yellow light at a preset dosage. A developer solution is selected based on the photoresist's properties, and the core particles are removed using dry or wet etching to create blank areas.

[0033] The method of this invention provides customers with the coordinates to which the Model Test Key (MTK) can be moved, so that the marker position is no longer completely limited by the arrangement of the exposure area frame. By calculating the relative position of its internal calibration based on the MTK coordinates and drawing the specific calibration, customers can accurately draw the layout of specific markers within the MTK using the MTK coordinates as relative coordinates. The method of this invention provides a certain degree of flexibility in marker layout, which can better adapt to the diverse needs of different customers for marker position. It enables customers to customize the precise position and layout of markers according to their specific needs for products, such as the special requirements for marker layout under different product models and application scenarios, and also better meets the market demand for customized CIS product markers.

[0034] In another aspect, the present invention provides a wafer precision positioning marking system for marking wafers on which an exposure area frame is arranged. The system is as follows: Figure 3 As shown, it includes: The coordinate acquisition module 011 is used to move the core of the exposure area where the target mark is located to form a blank area and acquire the coordinate information within the blank area; The coordinate calculation module 012 is used to move the model test key to the blank area and calculate the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key.

[0035] Furthermore, the system also includes a calibration module, which is used to obtain the actual coordinate position information of the coordinate calculation module and expose it on the wafer to form a mark.

[0036] Furthermore, the acquisition module also includes a storage unit for storing coordinate information within the blank area.

[0037] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0038] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0039] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0040] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for precise location marking on a wafer, characterized in that, include: S1 arranges the exposure area framework on the wafer and cuts it according to the requirements of the graphic design system file; S2 moves the core particles in the area where the target marker is located to form a blank area and obtains the coordinate information within the blank area; S3 moves the model test key to the blank area, calculates the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key, and exposes at the actual mark position to form a precise position mark.

2. The precise position marking method for a wafer according to claim 1, characterized in that, Based on the requirements of the graphic design system files, the wafer layout and cutting of the exposure area framework includes: Two target marker positions are obtained. Based on the requirements of the graphic design system file, the exposure area framework is arranged on the wafer. The two target marker positions are symmetrically distributed on the edge of the wafer exposure area. The wafer is then cut into multiple cores.

3. The precise position marking method for a wafer according to claim 1, characterized in that, The model test key structure includes two symmetrical positioning marks, and the remaining area is a virtual area.

4. The precise position marking method for a wafer according to claim 3, characterized in that, The positioning mark is a center mark, and the shape of the center mark includes a cross, a triangle, and a circle.

5. The precise position marking method for a wafer according to claim 1, characterized in that, Precise location markers are created using masking and yellow light exposure methods.

6. The precise position marking method for a wafer according to claim 1, characterized in that, The graphic design system files include chip layout and circuit patterns.

7. The precise position marking method for a wafer according to claim 1, characterized in that, The core is removed using photomask lithography to create a blank area.

8. A wafer precision positioning marking system for marking wafers, wherein an exposure area frame is arranged on the wafer, characterized in that, include: The coordinate acquisition module is used to move the core of the exposure area where the target mark is located to form a blank area and acquire the coordinate information within the blank area; The coordinate calculation module is used to move the model test key to the blank area and calculate the actual mark position based on the coordinate information in the blank area and the vertex coordinates of the model test key.

9. The wafer precise positioning marking system according to claim 8, characterized in that, Also includes: The calibration module is used to obtain the actual coordinate position information of the coordinate calculation module and expose it on the wafer to form a mark.

10. The wafer precise positioning marking system according to claim 9, characterized in that, The acquisition module further includes a storage unit for storing coordinate information within the blank area.

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