Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: forming a plastic package structure, the plastic package structure comprising a chip unit and a plastic package layer, the chip unit comprising at least one chip; the chip comprising a chip front surface, a chip back surface opposite to the chip front surface and a plurality of chip side surfaces connecting the chip front surface and the chip back surface, the chip front surface being provided with a plurality of bonding pads; the plastic package layer at least encapsulating the chip side surfaces; forming a redistribution layer, a plurality of conductive pillars and an insulating layer on the side of the plastic package structure away from the chip front surface; the redistribution layer being electrically connected with the bonding pads; each conductive pillar being located on the side of the redistribution layer away from the plastic package layer and being electrically connected with the redistribution layer; the insulating layer at least covering part of the side surface of the redistribution layer, and all the side surfaces and the surface of each conductive pillar away from the plastic package layer not being covered by the insulating layer; forming a solder layer, the solder layer covering all the side surfaces and the surface of each conductive pillar away from the plastic package layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] A chip packaging structure includes a chip, a molding compound layer encapsulating at least the sides of the chip, a redistribution layer located on the front side of the chip and electrically connected to solder pads on the front side of the chip, conductive bumps located on the side of the redistribution layer away from the molding compound layer, an insulating layer covering the redistribution layer and the conductive bumps, and a tin plating layer. The surface of the conductive bumps away from the redistribution layer is not covered by the insulating layer but is covered by the tin plating layer.

[0003] The aforementioned chip packaging structure is prone to board mounting defects during soldering to the circuit board. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for manufacturing the same.

[0005] According to a first aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0006] A molding compound structure is formed, the molding compound structure including a chip unit and a molding compound layer, the chip unit including at least one chip; the chip including a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads; the molding compound layer at least encapsulates the chip side sides;

[0007] A redistribution layer, a plurality of conductive bumps, and an insulating layer are formed on one side of the molding compound located on the front side of the chip; the redistribution layer is electrically connected to the solder pads; each of the conductive bumps is located on the side of the redistribution layer away from the molding compound and is electrically connected to the redistribution layer; the insulating layer covers at least a portion of the side surface of the redistribution layer, and all side surfaces of each conductive bump and the surface away from the molding compound are not covered by the insulating layer;

[0008] A solder layer is formed, which covers all sides of each of the conductive protrusions and the surface away from the encapsulation layer.

[0009] In one embodiment, the redistribution layer includes a plurality of spaced traces, each of which is electrically connected to at least one of the conductive protrusions; among the traces electrically connected to the same chip cell, the gap between two adjacent traces is filled by the insulating layer, and the area of ​​the surface of two adjacent traces away from the molding compound adjacent to the gap is covered by the insulating layer.

[0010] In one embodiment, forming a redistribution layer, multiple conductive bumps, and an insulating layer on the side of the molding compound located on the front side of the chip includes:

[0011] A redistribution layer is formed on one side of the molding compound located on the front side of the chip;

[0012] An insulating layer is formed, the insulating layer at least covering a portion of the sidewalls of the redistribution layer;

[0013] A dielectric layer is formed, the dielectric layer covering the surface of the redistribution layer away from the molding compound, the side surface of the insulating layer, and the surface away from the molding compound;

[0014] A plurality of vias are formed in the dielectric layer on the side of the redistribution layer away from the molding compound layer. Each via exposes a portion of the surface of the redistribution layer, and each via is spaced apart from the insulating layer.

[0015] Conductive protrusions are formed in each of the through holes; the distance from the surface of the conductive protrusion away from the molding layer to the molding layer is greater than the distance from the surface of the insulating layer away from the molding layer to the molding layer.

[0016] Remove the dielectric layer.

[0017] In one embodiment, among the traces electrically connected to the same chip cell, the side of each trace away from the pad to which it is electrically connected is not covered by the insulating layer but by the solder layer; or,

[0018] In the traces electrically connected to the same chip unit, each side of each trace is covered by the insulating layer.

[0019] In one embodiment, the molding compound includes multiple chip units;

[0020] After the solder layer is formed, the method for manufacturing the semiconductor structure further includes: cutting the obtained structure along the dicing path to obtain a plurality of semiconductor structures, each of the semiconductor structures including one of the chip units;

[0021] The orthographic projection of the cut track on a plane perpendicular to the thickness direction of the redistribution layer does not overlap with the orthographic projection of the redistribution layer on the same plane or the orthographic projection of the solder layer on the same plane.

[0022] In one embodiment, prior to forming the insulating layer, the method of manufacturing the semiconductor structure further includes: forming a connection structure at least partially located on the dicing track; each of the redistribution layers being electrically connected to the connection structure; and the connection structure being covered by the insulating layer.

[0023] The formation of the solder layer includes: connecting the connection structure to the electroplating electrode and forming the solder layer using an electroplating process;

[0024] In the step of cutting the obtained structure along the cutting path, the connecting structure is removed.

[0025] According to a second aspect of the embodiments of this application, a semiconductor structure is provided, the semiconductor structure comprising:

[0026] A chip unit includes at least one chip, each chip including a front side, a back side opposite to the front side, and a plurality of side surfaces connecting the front side and the back side, wherein the front side of the chip is provided with a plurality of solder pads;

[0027] A molding compound layer, at least encapsulating the sides of the chip;

[0028] A redistribution layer is located on one side of the front of the chip;

[0029] An insulating layer that at least covers a portion of the sidewalls of the redistribution layer;

[0030] Multiple conductive protrusions are located on the side of the redistribution layer away from the molding layer and are electrically connected to the redistribution layer, and all sides of each conductive protrusion and the surface away from the molding layer are not covered by the insulating layer;

[0031] A solder layer covers each side of the conductive protrusion and the surface away from the encapsulation layer.

[0032] In one embodiment, the redistribution layer includes a plurality of spaced traces, each of which is electrically connected to at least one of the conductive protrusions; among the traces electrically connected to the same chip cell, the gap between two adjacent traces is filled by the insulating layer, and the area of ​​the surface of two adjacent traces away from the molding compound adjacent to the gap is covered by the insulating layer.

[0033] In one embodiment, the distance from the surface of the conductive protrusion away from the molding layer to the molding layer is greater than the distance from the surface of the insulating layer away from the molding layer to the molding layer.

[0034] In one embodiment, among the traces electrically connected to the same chip cell, the side of each trace away from the pad to which it is electrically connected is not covered by the insulating layer but is covered by the solder layer; or,

[0035] In the traces electrically connected to the same chip unit, all sides of each trace are covered by the insulating layer.

[0036] The main technical effects achieved by the embodiments of this application are:

[0037] The semiconductor structure and manufacturing method provided in this application embodiment are such that, since all sides of each conductive protrusion and the surface away from the molding compound are not covered by the insulating layer, and the solder layer covers all sides of each conductive protrusion and the surface away from the molding compound, the solder can climb to each side of each conductive protrusion during the process of soldering the obtained semiconductor structure to the circuit board. This can effectively avoid the problem of poor solder climbing to the semiconductor structure, which would cause the semiconductor structure to shift or tilt relative to the circuit board, as well as the problem of voids in the solder layer between the semiconductor structure and the circuit board, thereby improving the quality of the semiconductor structure on the board. Attached Figure Description

[0038] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of this application;

[0039] Figure 2 This is a partial cross-sectional view of the first intermediate structure provided in an exemplary embodiment of this application;

[0040] Figure 3 This is a partial cross-sectional view of the second intermediate structure provided in an exemplary embodiment of this application;

[0041] Figure 4 This is a partial cross-sectional view of the third intermediate structure provided in an exemplary embodiment of this application;

[0042] Figure 5 This is a partial cross-sectional view of the fourth intermediate structure provided in an exemplary embodiment of this application;

[0043] Figure 6 This is a partial cross-sectional view of the fifth intermediate structure provided in an exemplary embodiment of this application;

[0044] Figure 7 This is a partial cross-sectional view of the sixth intermediate structure provided in an exemplary embodiment of this application;

[0045] Figure 8 This is a partial cross-sectional view of the sixth intermediate structure provided in another exemplary embodiment of this application;

[0046] Figure 9 This is a partial cross-sectional view of the seventh intermediate structure provided in an exemplary embodiment of this application;

[0047] Figure 10 This is a partial cross-sectional view of the eighth intermediate structure provided in an exemplary embodiment of this application;

[0048] Figure 11 This is a partial cross-sectional view of the ninth intermediate structure provided in an exemplary embodiment of this application;

[0049] Figure 12 yes Figure 11A partial structural diagram of the ninth intermediate structure is shown.

[0050] Figure 13 yes Figure 11 A partial structural diagram of the ninth intermediate structure is shown.

[0051] Figure 14 This is a partial cross-sectional view of the tenth intermediate structure provided in an exemplary embodiment of this application;

[0052] Figure 15 This is a cross-sectional view of a semiconductor structure provided in an exemplary embodiment of this application. Specific Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0054] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0055] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0056] This application provides a method for manufacturing a semiconductor structure. For example... Figure 1 As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 130.

[0057] In step 110, a molding compound structure is formed, the molding compound structure including a chip unit and a molding compound layer, the chip unit including at least one chip; the chip including a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads; the molding compound layer at least encapsulates the chip side sides.

[0058] In step 120, a redistribution layer, a plurality of conductive bumps, and an insulating layer are formed on the side of the molding compound located on the front side of the chip; the redistribution layer is electrically connected to the solder pads; each of the conductive bumps is located on the side of the redistribution layer away from the molding compound and is electrically connected to the redistribution layer; the insulating layer covers at least a portion of the side surface of the redistribution layer, and all side surfaces of each conductive bump and the surface away from the molding compound are not covered by the insulating layer.

[0059] In step 130, a solder layer is formed that covers all sides of each of the conductive protrusions and the surface away from the encapsulation layer.

[0060] The semiconductor structure manufacturing method provided in this application embodiment has the following advantages: since all sides of each conductive protrusion and the surface away from the molding compound are not covered by an insulating layer, and the solder layer covers all sides of each conductive protrusion and the surface away from the molding compound, the solder can climb to each side of each conductive protrusion during the soldering process of the obtained semiconductor structure to the circuit board. This effectively avoids the problem of poor solder climbing to the semiconductor structure, which could lead to the semiconductor structure shifting or tilting relative to the circuit board, as well as the problem of voids in the solder layer between the semiconductor structure and the circuit board. This can improve the board mounting quality of the semiconductor structure. Furthermore, this application embodiment does not require the formation of an insulating film layer covering the conductive protrusions, which helps to simplify the process and shorten the process time.

[0061] The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail below.

[0062] In step 110, a molding compound structure is formed, the molding compound structure including a chip unit and a molding compound layer, the chip unit including at least one chip; the chip including a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads; the molding compound layer at least encapsulates the chip side sides.

[0063] In one embodiment, the step of forming the encapsulated structure may include the following process:

[0064] First, the chip unit is mounted on the carrier board with the front side of the chip facing the carrier board.

[0065] This step yields the following result: Figure 2 The first intermediate structure shown. (As shown) Figure 2As shown, the chip unit 101 is mounted on the carrier board 22 via an adhesive layer 21; the front side of the chip 10 has multiple solder pads 11; the front side of the chip 10 also has a protective layer 12, which has multiple openings 121, each opening 121 corresponding to a solder pad 11, and each opening 121 exposing at least a portion of the surface of a solder pad 11. Multiple chip units 101 can be mounted on the carrier board 22 simultaneously. Figure 2 In the illustrated embodiment, each chip unit 101 includes one chip 10. In other embodiments, each chip unit 101 may include multiple chips 10.

[0066] In one embodiment, the adhesive layer 21 may be made of an easily peelable material to facilitate the subsequent peeling of the first carrier plate 22. For example, the adhesive layer 21 may be made of a heat-removable material that can be de-adhesive by heating.

[0067] Subsequently, a molding layer is formed.

[0068] This step yields the following result: Figure 3 The second intermediate structure shown. (As shown) Figure 3 As shown, the molding compound 30 encapsulates the chip side and chip back of each chip 10.

[0069] In one embodiment, before forming the molding compound 30, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surface of the chip 10 so that the molding compound 30 and the chip 10 can be more closely connected and there will be no delamination or cracking.

[0070] In one embodiment, the material of the encapsulation layer 30 can be a polymer resin, a resin composite material, or a polymer composite material. For example, the encapsulation layer 30 can be a resin with fillers, wherein the fillers can be inorganic particles. The encapsulation layer 30 can be formed by injection molding, compression molding, or transfer molding.

[0071] Then, the carrier board is removed.

[0072] After removing the carrier board, the solder pads 11 of chip 10 are exposed.

[0073] In step 120, a redistribution layer, a plurality of conductive bumps, and an insulating layer are formed on the side of the molding compound located on the front side of the chip; the redistribution layer is electrically connected to the solder pads; each of the conductive bumps is located on the side of the redistribution layer away from the molding compound and is electrically connected to the redistribution layer; the insulating layer covers at least a portion of the side surface of the redistribution layer, and all side surfaces of each conductive bump and the surface away from the molding compound are not covered by the insulating layer.

[0074] In one embodiment, prior to step 120, the obtained molding structure is first mounted on a carrier plate, which provides support for the molding structure in step 120 and subsequent steps.

[0075] This step yields the following result: Figure 4 The third intermediate structure shown. (As shown in the image) Figure 4 As shown, the encapsulation structure is attached to the carrier plate 24 via the adhesive layer 23, with the front side of each chip 10 facing away from the carrier plate 24.

[0076] In one embodiment, the adhesive layer 23 may be made of an easily peelable material to facilitate the subsequent peeling of the first carrier plate 24. For example, the adhesive layer 23 may be made of a heat-removable material that can be de-adhesive by heating.

[0077] In one embodiment, the step of forming a redistribution layer, a plurality of conductive bumps, and an insulating layer on the side of the molding compound located on the front side of the chip may include the following process:

[0078] First, a redistribution layer is formed on the side of the molding compound located on the front side of the chip.

[0079] This step yields the following result: Figure 5 The fourth intermediate structure is shown. (As shown in the image.) Figure 5 As shown, the redistribution layer 40 includes a plurality of traces 41, each trace 41 being electrically connected to a pad 11 of the chip 10 via a conductive portion 42 located within an opening 121. A trace 41 may be electrically connected to one pad 11 of the chip 10, or to two or more pads 11.

[0080] Subsequently, an insulating layer is formed, which at least covers a portion of the sidewalls of the redistribution layer.

[0081] In this step, the initially formed insulating layer can cover the sides of the redistribution layer and the surface away from the molding compound, resulting in... Figure 6 The fifth intermediate structure is shown. (As shown in the image.) Figure 6 As shown, the insulating layer 50 covers the sides of each trace 41 and the surface away from the molding compound 30. The insulating layer is then etched to remove at least the portion of the insulating layer on the side of the redistribution layer away from the molding compound, resulting in the following... Figure 7 or Figure 8 The sixth intermediate structure shown. (As shown in the image) Figure 7 As shown, the insulating layer 50 covers a portion of the side surface of the trace 41; as Figure 8 As shown, the insulating layer 50 covers all sides of each of the traces 41.

[0082] In one embodiment, Figure 7In the sixth intermediate structure shown, among the traces 41 electrically connected to the same chip unit 101, the side of each trace 41 away from the solder pad 11 to which it is electrically connected is not covered by the insulating layer 50 (see [link]). Figure 13 In this embodiment, the sides of each trace 41 are ultimately covered by the solder layer. During the soldering of the semiconductor structure to the circuit board, the solder climbs up the sides of the conductive protrusions and the sides of the traces 41, generating a pulling force on the semiconductor structure. Since the sides of each trace 41 are covered by the solder layer, and the traces 41 are basically uniformly distributed in the semiconductor structure, the solder covering the sides of each trace 41 is basically uniformly distributed in the edge region of the semiconductor structure. This ensures that the forces on each side of the semiconductor structure are uniform, which helps to avoid the problem of the semiconductor structure tilting relative to the circuit board.

[0083] In another embodiment, Figure 8 In the sixth intermediate structure shown, each side of the trace 41 electrically connected to the same chip unit 101 is covered by the insulating layer. In this embodiment, since the sides of each trace 41 are covered by the insulating layer 50, no solder layer is formed on the sides of each trace 41. When soldering the semiconductor structure to the circuit board, the solder only creeps towards the sides of the conductive protrusions. The conductive protrusions in the final semiconductor structure are basically evenly distributed, which makes the force on each side of the semiconductor structure uniform and avoids the problem of the semiconductor structure tilting relative to the circuit board. In this embodiment, since no solder layer is formed on the sides of each trace 41, the problem of a small distance between the solder layer and the dicing channel when a solder layer is formed on the sides of the trace 41 can be avoided. This would prevent the subsequent cutting of the solder layer on the side of the trace 41 during the semiconductor structure cutting process, resulting in metal wires. The metal wires would fall between adjacent traces 41, causing short circuits between adjacent traces 41. Furthermore, since each side of the trace 41 is covered by an insulating layer, it is not necessary to control the distance between the insulating layer and the side of the trace 41 when forming the insulating layer, thus reducing the requirements for process precision.

[0084] In one embodiment, the insulating layer is made of green oil. Thus, the insulating layer can be etched using an exposure and development process, which is easy to implement.

[0085] Subsequently, a dielectric layer is formed that covers the surface of the redistribution layer away from the molding compound, the side surface of the insulating layer, and the surface away from the molding compound.

[0086] In one embodiment, the dielectric layer is prefabricated, and in this step, the prefabricated dielectric layer can be attached to the sixth intermediate structure by lamination.

[0087] Subsequently, a plurality of vias are formed on the portion of the dielectric layer located on the side of the redistribution layer away from the molding compound layer. Each via exposes a portion of the surface of the redistribution layer, and each via is spaced apart from the insulating layer.

[0088] This step yields the following result: Figure 9 The seventh intermediate structure is shown. (As shown in the image.) Figure 9 As shown, the dielectric layer 60 has a plurality of through holes 61, each through hole 61 exposing a trace 41 on a portion of the surface away from the molding layer 30; since each through hole 61 is spaced apart from the insulating layer 50, it can be ensured that after the conductive protrusions are formed in the through holes 61 and the dielectric layer 60 is removed, the side of each conductive protrusion is exposed.

[0089] It should be noted that, Figure 9 The structure shown and the structure formed by subsequent steps are only based on Figure 7 The sixth intermediate structure shown is illustrated as an example.

[0090] Subsequently, conductive protrusions are formed in each of the through holes; the distance from the surface of the conductive protrusion away from the molding layer to the molding layer is greater than the distance from the surface of the insulating layer away from the molding layer to the molding layer.

[0091] This step yields the following result: Figure 10 The eighth intermediate structure is shown. (As shown in the image.) Figure 10 As shown, each through hole 61 has a conductive protrusion 70 formed therein, and the surface of the conductive protrusion 70 away from the molding layer 30 is flush with the surface of the dielectric layer 60 away from the molding layer 30.

[0092] Since the dielectric layer 60 covers the surface of the insulating layer 50 away from the molding layer 30, that is, the distance from the surface of the dielectric layer 60 away from the molding layer 30 to the molding layer 30 is greater than the distance from the surface of the insulating layer 50 to the molding layer 30, the distance from the surface of the conductive protrusion 70 formed in the through hole 61 of the dielectric layer 60 away from the molding layer 30 to the molding layer 30 is greater than the distance from the surface of the insulating layer 50 to the molding layer 30, that is, the conductive protrusion 70 protrudes relative to the insulating layer 50.

[0093] Subsequently, the dielectric layer is removed.

[0094] This step yields the following result: Figures 11 to 13 The ninth intermediate structure shown. (As shown) Figure 11 As shown, none of the sides of each conductive protrusion 70 are covered by the insulating layer 50.

[0095] In one embodiment, when the dielectric layer is prefabricated, it can be directly peeled off in this step, making it easy to remove the dielectric layer.

[0096] By employing the above steps to form a redistribution layer, multiple conductive bumps, and an insulating layer, the conductive bumps 70 protrude relative to the insulating layer 50. After the solder layer is finally formed, the conductive bumps 70 and the solder layer covering them protrude relative to the insulating layer 50. Thus, when the semiconductor structure is soldered to the circuit board, it is easier to solder, reducing the amount of solder applied to the circuit board. Furthermore, when the semiconductor structure is tilted relative to the circuit board, the solder more easily climbs to the sides of the conductive bumps during the soldering process, helping to straighten the semiconductor structure when it is tilted relative to the circuit board.

[0097] In one embodiment, the difference between the distance from the surface of the conductive protrusion 70 away from the molding compound 30 and the distance from the surface of the insulating layer 50 to the molding compound 30 ranges from 10 μm to 20 μm. This setting avoids situations where a small difference would prevent the amount of solder applied to the circuit board from being effectively reduced and the semiconductor structure alignment effect from being ineffective; it also avoids situations where a large difference would result in an excessively long electroplating time for forming the conductive protrusion. In some embodiments, the difference can be 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc.

[0098] In one embodiment, such as Figure 11 As shown, in the traces 41 electrically connected to the same chip unit 101, the gap between two adjacent traces 41 is filled by the insulating layer 50, and the area adjacent to the gap on the surface of two adjacent traces 41 away from the molding compound 30 is covered by the insulating layer 50. This configuration avoids the problem of short circuits occurring when the distance between two adjacent traces 41 electrically connected to the same chip unit 101 is too small during the subsequent electroplating process to form the solder layer.

[0099] In step 130, a solder layer is formed that covers all sides of each of the conductive protrusions and the surface away from the encapsulation layer.

[0100] This step yields the following result: Figure 14 The tenth intermediate structure is shown. (As shown in the image.) Figure 14 As shown, each side of the conductive protrusion 70 and the surface away from the molding compound 30 are covered by the solder layer 80, and the side of the trace 41 not covered by the insulating layer 50 is covered by the solder layer 80.

[0101] In one embodiment, the solder layer 80 is made of tin.

[0102] In one embodiment, prior to forming the insulating layer, the method for manufacturing the semiconductor structure further includes: forming a connection structure located on the dicing trace; and electrically connecting each of the redistribution layers to the connection structure. The step of forming the solder layer includes: connecting the connection structure to an electroplating electrode and forming the solder layer using an electroplating process. Thus, by providing the connection structure, each trace can be electrically connected, thereby electrically connecting all conductive protrusions located on the side of each trace away from the molding compound. Electrically connecting the connection structure to the electroplating electrode allows solder layers to be formed simultaneously on the side surfaces of each conductive protrusion and the surface away from the molding compound, simplifying the operation.

[0103] In one embodiment, each trace electrically connected to the same chip cell can be surrounded by a connection structure. This ensures that each trace is electrically connected to the connection structure.

[0104] In one embodiment, the connection structure is formed simultaneously with the redistribution layer. This helps simplify the fabrication process. In one embodiment, such as Figure 14 As shown, the plastic encapsulation structure includes multiple chip units 101. After forming the solder layer, the method for manufacturing the semiconductor structure further includes the following steps: cutting the obtained structure along the dicing path to obtain multiple semiconductor structures, each of the semiconductor structures including one chip unit.

[0105] Figure 14 The portion between the two opposing cutting edge lines 91 shown is the cutting track; the portion between cutting edge line 92 and the adjacent cutting edge line (not shown in the figure) is the cutting track; and the portion between cutting edge line 93 and the adjacent cutting edge line (not shown in the figure) is the cutting track. This step yields the following... Figure 15 The semiconductor structure is shown. It should be noted that the carrier plate 24 is peeled off before cutting the obtained structure along the dicing path.

[0106] In one embodiment, such as Figures 12 to 14 As shown, the orthographic projection of the dicing track on a plane perpendicular to the thickness direction of the redistribution layer 40 does not overlap with the orthographic projections of the redistribution layer 40 and the solder layer 80 on the same plane. That is, there is a gap between the redistribution layer 40 and the dicing track, and there is also a gap between the portion of the solder layer 80 located on the side of the trace 41 and the dicing track. This configuration prevents the redistribution layer 40 and the solder layer 80 from being cut during the cutting process, thus avoiding the problem of metal wires falling between adjacent traces 41 and causing short circuits.

[0107] In one embodiment, the distance between the redistribution layer 40 and the adjacent cut track may be approximately 20 μm.

[0108] In one embodiment, the connecting structure is covered by the insulating layer 50. This arrangement ensures that even when the connecting structure is cut along the cutting path, minimal metal wire breakage occurs.

[0109] In one embodiment, during the step of cutting the obtained structure along the cutting path, the connecting structure is removed.

[0110] This application also provides a semiconductor structure. For example... Figure 15 As shown, the semiconductor structure includes a chip unit 101, a molding compound 30, a redistribution layer 40, an insulating layer 50, a plurality of conductive protrusions 70, and a solder layer 80.

[0111] The chip unit 101 includes at least one chip 10. Each chip 10 includes a front side, a back side opposite to the front side, and multiple side surfaces connecting the front and back sides. The front side has multiple solder pads 11. The molding compound 30 at least encapsulates the side surfaces. The redistribution layer 40 is located on one side of the front side. The insulating layer 50 at least covers a portion of the side surfaces of the redistribution layer 40. The multiple conductive protrusions 70 are located on the side of the redistribution layer 40 away from the molding compound 30 and are electrically connected to the redistribution layer 40. The side surfaces and surfaces of the conductive protrusions 70 away from the molding compound 30 are not covered by the insulating layer 50. The solder layer 80 covers each side surface and surface of each conductive protrusion 70 away from the molding compound 30.

[0112] In one embodiment, such as Figure 15 As shown, the redistribution layer 40 includes a plurality of spaced traces 41, each of which is electrically connected to at least one conductive protrusion 70; among the traces 41 electrically connected to the same chip cell, the gap between two adjacent traces 41 is filled by the insulating layer 50, and the area of ​​the surface of two adjacent traces 41 away from the molding compound 30 adjacent to the gap is covered by the insulating layer 50.

[0113] In one embodiment, such as Figure 15 As shown, the distance from the surface of the conductive protrusion 70 away from the molding layer 30 to the molding layer 30 is greater than the distance from the surface of the insulating layer 50 away from the molding layer 30 to the molding layer 30.

[0114] In one embodiment, such as Figure 15 As shown, among the traces 41 electrically connected to the same chip unit 101, the side of each trace 41 away from the pad 11 to which it is electrically connected is not covered by the insulating layer 50, but is covered by the solder layer 80.

[0115] In another embodiment, all sides of each trace 41 electrically connected to the same chip unit 101 are covered by the insulating layer 50.

[0116] The embodiments of the semiconductor structure provided in this application and the embodiments of the semiconductor structure manufacturing method belong to the same inventive concept. The descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0117] It should be noted that, in the embodiments of this application, Figures 2 to 15 The sectional views shown are all obtained by cutting the corresponding three-dimensional structure along a direction perpendicular to the back of the chip.

[0118] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0119] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method for manufacturing the semiconductor structure includes: A molding compound structure is formed, the molding compound structure including a chip unit and a molding compound layer, the chip unit including at least one chip; the chip including a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, the chip front side having a plurality of solder pads; the molding compound layer at least encapsulates the chip side sides; A redistribution layer, a plurality of conductive bumps, and an insulating layer are formed on one side of the molding compound located on the front side of the chip; the redistribution layer is electrically connected to the solder pads; each of the conductive bumps is located on the side of the redistribution layer away from the molding compound and is electrically connected to the redistribution layer; the insulating layer covers at least a portion of the side surface of the redistribution layer, and all side surfaces of each conductive bump and the surface away from the molding compound are not covered by the insulating layer; A solder layer is formed, which covers all sides of each of the conductive protrusions and the surface away from the encapsulation layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The redistribution layer includes a plurality of spaced traces, each of which is electrically connected to at least one of the conductive protrusions; among the traces electrically connected to the same chip cell, the gap between two adjacent traces is filled by the insulating layer, and the area of ​​the surface of two adjacent traces away from the molding compound that is adjacent to the gap is covered by the insulating layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The process of forming a redistribution layer, multiple conductive bumps, and an insulating layer on the side of the molding compound located on the front side of the chip includes: A redistribution layer is formed on one side of the molding compound located on the front side of the chip; An insulating layer is formed, the insulating layer at least covering a portion of the sidewalls of the redistribution layer; A dielectric layer is formed, the dielectric layer covering the surface of the redistribution layer away from the molding compound, the side surface of the insulating layer, and the surface away from the molding compound; A plurality of vias are formed in the portion of the dielectric layer located on the side of the redistribution layer away from the molding compound layer. Each via exposes a portion of the surface of the redistribution layer, and each via is spaced apart from the insulating layer. Conductive protrusions are formed within each of the through holes; the distance from the surface of the conductive protrusion away from the molding layer to the molding layer is greater than the distance from the surface of the insulating layer away from the molding layer to the molding layer. Remove the dielectric layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In traces electrically connected to the same chip cell, the side of each trace away from the pad it is electrically connected to is not covered by the insulating layer, but is covered by the solder layer; or, In the traces electrically connected to the same chip unit, each side of each trace is covered by the insulating layer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The encapsulated structure includes multiple chip units; After the solder layer is formed, the method for manufacturing the semiconductor structure further includes: cutting the obtained structure along the dicing path to obtain a plurality of semiconductor structures, each of the semiconductor structures including one of the chip units; The orthographic projection of the cut track on a plane perpendicular to the thickness direction of the redistribution layer does not overlap with the orthographic projection of the redistribution layer on the same plane or the orthographic projection of the solder layer on the same plane.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, Before forming the insulating layer, the method of manufacturing the semiconductor structure further includes: forming a connection structure at least partially located in the dicing track; each of the redistribution layers being electrically connected to the connection structure; and the connection structure being covered by the insulating layer. The formation of the solder layer includes: connecting the connection structure to the electroplating electrode and forming the solder layer using an electroplating process; In the step of cutting the obtained structure along the cutting path, the connecting structure is removed.

7. A semiconductor structure, characterized in that, The semiconductor structure includes: A chip unit includes at least one chip, each chip including a front side, a back side opposite to the front side, and a plurality of side surfaces connecting the front side and the back side, wherein the front side of the chip is provided with a plurality of solder pads; A molding compound layer, at least encapsulating the sides of the chip; A redistribution layer is located on one side of the front of the chip; An insulating layer that at least covers a portion of the sidewalls of the redistribution layer; Multiple conductive protrusions are located on the side of the redistribution layer away from the molding layer and are electrically connected to the redistribution layer, and all sides of each conductive protrusion and the surface away from the molding layer are not covered by the insulating layer; A solder layer covers each side of the conductive protrusion and the surface away from the encapsulation layer.

8. The semiconductor structure according to claim 7, characterized in that, The redistribution layer includes a plurality of spaced traces, each of which is electrically connected to at least one of the conductive protrusions; among the traces electrically connected to the same chip cell, the gap between two adjacent traces is filled by the insulating layer, and the area of ​​the surface of two adjacent traces away from the molding compound that is adjacent to the gap is covered by the insulating layer.

9. The semiconductor structure according to claim 7, characterized in that, The distance from the surface of the conductive protrusion away from the molding layer to the molding layer is greater than the distance from the surface of the insulating layer away from the molding layer to the molding layer.

10. The semiconductor structure according to claim 7, characterized in that, In traces electrically connected to the same chip cell, the side of each trace away from the pad it is electrically connected to is not covered by the insulating layer, but is covered by the solder layer; or, In the traces electrically connected to the same chip unit, all sides of each trace are covered by the insulating layer.

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