Clock monitoring subsystem for a system-on-a-chip to support dynamic clock scaling and clock gating

Abstract

A method of a clock monitoring subsystem of a system-on-a-chip (SoC) to support dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing, by one or more clock routing subsystems, a selected clock of the set of clocks for frequency measurement. The method also includes adjusting a frequency of the selected clock after the selected clock is routed by the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 509,245, filed November 14, 2023, entitled “CLOCK MONITORING SUBSYSTEM FORSYSTEM-ON-CHIP SUPPORTING DYNAMIC CLOCK SCALING AND CLOCK GATING,” the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0002] Various aspects of this disclosure relate to clock monitoring units, and more specifically, to clock monitoring subsystems for supporting system-on-chip (SoC) with dynamic clock scaling and voltage gating. Background Technology

[0003] Vehicle or automotive control systems are subject to more stringent electrical operating requirements. This is because errors in such vehicle or automotive control systems can result in serious injury or death to humans occupying the associated vehicle, as well as to humans, animals, and property that may collide with such a vehicle. These stringent electrical operating requirements address system redundancy, provide greater resistance to electrical and software failures, and improve the monitoring of such systems, to name just a few. One subcomponent of such systems is a clock generator, which produces timing signals (often referred to as "clock signals," or simply "clock") to drive the various signal processing cores of an integrated circuit (IC) or system-on-a-chip (SoC). Summary of the Invention

[0004] A method is described for a clock monitoring subsystem for a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating. The method includes generating a set of clocks. The method also includes routing a selected clock from the set of clocks via one or more clock routing subsystems for frequency measurement. The method further includes adjusting the frequency of the selected clock after routing it via the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

[0005] A non-transitory computer-readable medium is described, on which program code for a clock monitoring subsystem of a system-on-a-chip (SoC) supporting dynamic clock scaling and voltage gating is recorded. The program code is executed by a processor. The non-transitory computer-readable medium includes program code for generating a set of clocks. The non-transitory computer-readable medium also includes program code for routing a selected clock from the set of clocks via one or more clock routing subsystems for frequency measurement. The non-transitory computer-readable medium also includes program code for adjusting the frequency of the selected clock after routing the selected clock via the clock routing subsystems. The non-transitory computer-readable medium also includes program code for conveying sideband signals to indicate the adjusted frequency of the selected clock.

[0006] A transportation system is described. The transportation system includes a transportation control subsystem. The transportation system also includes one or more digital signal processing cores coupled to the transportation control subsystem. The transportation system further includes a set of clock generators for generating a set of clocks, wherein the set of clock generators is coupled to the one or more digital signal processing cores. The transportation system also includes one or more clock routing subsystems, in which a selected clock from the set of clocks is routed for frequency measurement. The transportation system further includes a clock monitoring unit for adjusting the frequency of the selected clock after routing it through the clock routing subsystems and for transmitting sideband signals to indicate the adjusted frequency of the selected clock.

[0007] This has broadly outlined the features and technical advantages of this disclosure in order to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for performing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0008] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings.

[0009] Figure 1 This is a block diagram illustrating various aspects of a system-on-a-chip (SoC) according to this disclosure.

[0010] Figure 2 This further illustrates various aspects of this disclosure. Figure 1 Block diagram of the Automotive Clock Monitoring Unit (ACMU).

[0011] Figure 3 This is a block diagram illustrating examples of clock monitoring systems for system-on-chips (SoCs) that support dynamic clocking and scaling, as well as voltage gating, according to various aspects of this disclosure.

[0012] Figure 4 This is a block diagram illustrating a clock controller configured using frequency word multiplexing functionality according to various aspects of this disclosure.

[0013] Figures 5A to 5C Examples of various aspects according to this disclosure are shown. Figure 1 and Figure 2 A flowchart illustrating the operation of the control unit clock monitoring state machine (CMSM).

[0014] Figure 6A and Figure 6B A flowchart illustrating a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating processes is shown according to various aspects of this disclosure.

[0015] Figure 7A and Figure 7B This is a block diagram illustrating the clock frequency monitoring process according to various aspects of this disclosure.

[0016] Figure 8 This is a block diagram of an example transportation system based on various aspects of this disclosure.

[0017] Figure 9 This is a process flowchart illustrating a method for a clock monitoring subsystem of a system-on-chip (SoC) that supports dynamic clock scaling and voltage gating, according to various aspects of this disclosure.

[0018] Figure 10 This is a block diagram illustrating an exemplary wireless communication system in which the configuration of this disclosure can be advantageously employed.

[0019] Figure 11 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. Detailed Implementation

[0020] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0021] As described herein, the use of the term “and / or” is intended to indicate “inclusive or”, and the use of the term “or” is intended to indicate “exclusive or”. As described herein, the term “exemplary” as used throughout the description means “used as an example, instance, or illustration” and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” as used throughout the description means “direct or indirectly connected via an intermediate connection (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Furthermore, a connection can permanently or releasably connect objects. Connections can be made via switches. As described herein, the term “proximity” as used throughout the description means “adjacent, very close, adjacent, or near.” As described herein, the term “on” as used throughout the description means “directly on” in some configurations and “indirectly on” in others.

[0022] Electronic circuits designed for vehicle or automotive control or other safety-related applications may be subject to more stringent specifications. These stringent specifications are in place because malfunctions in automotive control circuits can lead to serious injury or death. Government organizations that regulate electronic circuits for automotive control and other safety-related applications include the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC).

[0023] For example, ISO has specified the international standard ISO 26262, entitled "Road vehicles - Functional safety," which provides specifications for the functional safety of electrical and / or electronic systems in continuously manufactured road vehicles. IEC has specified the international standard IEC 61508, entitled "Functional Safety of Electrical / Electronic / Programmable Electronic Safety-related Systems," which outlines methods for applying, designing, deploying, and maintaining automated protection systems known as safety-related systems. Both ISO 26262 and IEC 61508 specify the continuous monitoring of certain safety-related systems during operation to ensure proper functioning.

[0024] This continuous monitoring specification also includes continuous monitoring of the clock of the data processing core of the System-on-Chip (SoC) used in automotive control or other safety-related systems. As described, a “clock” (often also referred to as a “clock signal”) is a timing signal that drives various operations within the SoC, such as data processing, data transmission, etc. Integrated circuits (ICs) or SoCs may employ a clock monitoring unit (CMU) to measure the clock frequency and other relevant parameters and provide interrupts to the error management module (EMM) or designated safety processor within the SoC. These devices respond to clock failure interrupts and, taking into account the nature and characteristics of the interrupt, take measures to ensure the safe operation of the automotive control or safety-related systems. Such clock failures may include clock frequency drift due to phase-locked loop (PLL) jitter, momentary clock stops, and PLL loss of its lock.

[0025] During implementation, the CMU is configured and maintained by safety manager software, which operates at a higher level of security compared to the subsystem software that manages dynamic frequency scaling based on subsystem clocks. Any frequency change without communication between the subsystem hardware / software and the CMU will cause the CMU to report a clock failure. In other words, to support dynamic frequency scaling (DFS) based on subsystem clock frequency changes, communication between the subsystem hardware / software and the CMU is specified. Software-level communication between the subsystem software and the safety manager software is a high-latency process and involves significant software overhead. The latency involved may violate the Fault Detection Time Interval (FDTI) level defined in the ISO 26262 standard. A hardware-based communication solution is desired for seamlessly transitioning the Automotive Clock Monitoring Unit (ACMU) to different frequency monitoring nodes without software latency, while complying with FDTI specifications and having minimal hardware overhead.

[0026] Various aspects of this disclosure relate to a clock monitoring subsystem for a system-on-a-chip (SoC) supporting dynamic clocking and scaling, as well as voltage gating. According to various aspects of this disclosure, a method for a clock monitoring subsystem for a SoC supporting dynamic clocking and scaling, as well as voltage gating, is described. This clock monitoring subsystem method includes generating a set of clocks. Once generated, a selected clock from this set of clocks is routed via one or more clock routing subsystems for frequency measurement. The clock monitoring subsystem method adjusts the frequency of the selected clock after it has been routed via the clock routing subsystems. According to various aspects of this disclosure, the clock monitoring subsystem method transmits sideband signals to indicate the adjusted frequency of the selected clock for an automotive chip with clock monitoring.

[0027] Figure 1This is a block diagram illustrating a system-on-a-chip (SoC) 100 according to various aspects of this disclosure. The SoC 100 can be used in automotive control systems or other types of safety-related systems. The SoC 100 may include a set of subsystems (not shown) for performing various operations according to the design specifications of the SoC 100. For example, in the case of vehicle control, this set of subsystems may include semi-autonomous or autonomous driving subsystems (e.g., advanced driver assistance systems (ADAS)), such as forward collision warning (FCW), lane departure warning (LDW), blind spot detection (BSD) subsystems (e.g., ADAS level "0" subsystem); adaptive cruise control (ACC) and lane keeping assist (LKA) subsystems (e.g., ADAS level "1" subsystem); ACC with lane keeping and traffic jam assist subsystems (e.g., ADAS level "2" subsystem); highway autonomous driving and traffic jam navigation subsystems (e.g., ADAS level "3" subsystem); full highway autonomous driving and full city autonomous driving subsystems (e.g., ADAS level "4" subsystem); and autonomous taxi / shuttle and autonomous delivery fleet subsystems (e.g., ADAS level "5" subsystem).

[0028] In various aspects of this disclosure, SoC 100 also includes a security subsystem clock controller 110, a central clock controller (CCC) 140, a security monitoring subsystem (SMSS) 170, and an automotive clock monitoring unit (ACMU) 200. The security subsystem clock controller 110 includes a security subsystem (SS) clock 112, a clock multiplexer (MUX) 120, a clock divider (CDIV) 122, and a clock gating control (CGC) 130. Similarly, CCC 140 includes a CCC clock 142, a clock MUX 150, a clock divider (CDIV) 152, and a clock gating control (CGC) 160. Additionally, SMSS 170 includes an SMSS clock 172, a clock MUX 180, a clock divider (CDIV) 182, and a clock gating control (CGC) 190.

[0029] In operation, the Clock Monitoring State Machine (CMSM) 230 of the ACMU 200 supplies corresponding CGC enable signals, divider (DIV) value signals, and MUX select (SEL) signals to control clock generation from the security subsystem clock controller 110, CCC 140, and SMSS 170. In various aspects of this disclosure, the security subsystem clock controller 110 supplies a CGC input signal 132 to the clock MUX 150 of the CCC 140, and the CCC 140 supplies a CGC input signal 162 to the clock MUX 180 of the SMSS 170. In various aspects of this disclosure, the SMSS 170 supplies a CGC input signal 192 to the frequency measurement unit (FMU) 220 of the ACMU 200.

[0030] A set of clock dividers 122 / 152 / 182 in the SoC 100 includes clock inputs coupled to the clock outputs of a set of clock multiplexers 120 / 150 / 180, respectively. The set of clock dividers 122 / 152 / 182 includes a set of clock divider value inputs configured to receive divider value signals from a set of clock divider value outputs of the CMSM 230 to control the division ratio N of the set of clock dividers 122 / 152 / 182, respectively. The division ratio N is the frequency of the input clock of the clock divider divided by the frequency of the output clock of the clock divider. The set of clock dividers 122 / 152 / 182 is configured to divide a selected clock such that the frequency of the clock supplied to the ACMU 200 is within a specified limit. For example, the specified frequency limit of the clock applied to the ACMU 200 may be 200 MHz. For example, if the clock frequency is one (1) gigahertz (1 GHz), then the total division ratio of the set of clock dividers 122 / 152 / 182 should be five (5) or greater.

[0031] The set of clock gating circuits (CGCs) 130 / 160 / 190 includes clock inputs coupled to the clock outputs of the set of clock dividers 122 / 152 / 182, respectively. The set of clock gating circuits 130 / 160 / 190 includes a set of clock gating enable inputs configured to receive a CGC enable signal from the CMSM 230 to control the gating operation of the set of CGCs 130 / 160 / 190, respectively. For example, if a selected clock is generated by the set of CGCs 130 / 160 / 190 for routing to the ACMU 200, the CGC enable signal is configured to control the set of CGCs 130 / 160 / 190 to allow the selected clock to pass and block other corresponding input clocks so as not to unnecessarily consume clock power. The ACMU 200 includes an FMU 220, which receives a reference clock from the CGC 190 of the SMSS 170. FMU 220 is configured to process a selected clock, or more specifically, to measure the frequency of a selected clock based on a selected reference clock, and to generate a value indicating such frequency at a frequency measurement output coupled to the input of CMSM 230. According to various aspects of this disclosure, ACMU 200 in Figure 2 Further examples are provided below.

[0032] Figure 2 This further illustrates various aspects of this disclosure. Figure 1 Block diagram of ACMU 200. Clock Monitoring State Machine (CMSM) 230 is configured to, for example, configure the processor (from software (SW)). Figure 2 The SW configuration (not shown) is received to control the operation of clock frequency measurement. For example, for a specific measurement period, the SW configuration can provide information to the CMSM 230 using a monitoring mode signal (e.g., monitoring mode enabled), such as which clock(s)(MUX SEL) to measure (MUX SEL override), the corresponding clock divider value (DIV value override), and the corresponding clock gating control (CGC) status (CGC enabled). In this example, the SW configuration provides one set of information for the CCC 140 and SMSS 170, and broadcasts another set of information for other clock controllers. In response to this software configuration, the CMSM 230 generates corresponding clock selection (MUX SEL override), divider value (DIV value override), and control gate enable (CGC enabled) signals.

[0033] like Figure 2As illustrated, the CMSM 230 receives a programmable timer signal from the programmable timer 232 and an input selector MUX signal from the input selector MUX 234 to generate, at a set of state outputs: a clock fault interrupt (CLK fault IRQ) in response to the detection of a subsystem clock fault (the frequency deviation of the measured clock exceeds a specified margin); and a self-test failure interrupt (self-test failure IRQ) in response to a reference clock fault (the frequency deviation of the measured reference clock exceeds a specified margin). Similarly, the CMSM 230 generates a phase-locked loop (PLL) unlock interrupt (PLL unlock IRQ) in response to receiving a PLL aggregation lock signal. The interrupts can be provided to the error management module (EMM) or a designated security processor (…). Figure 2 (not shown in the image) to provide an appropriate response to interruptions in order to ensure human safety in accordance with security-related applications.

[0034] In this example, the output signal from the frequency measurement unit (FMU) 220 is supplied to the CMSM 230 to generate a CLK fault IRQ signal, a PLL unlock IRQ signal, a self-test failure IRQ signal, and a cmu_busy signal. Figure 2 As shown, the FMU220 receives a core clock signal (Cmu_core_clk), a measurement clock signal (Cmu_measure_clk), and reference clock signals (acmu_ref1_clk, acmu_ref2_clk, acmu_ref3_clk, and acmu_ref4_clk). The reference clock signals (acmu_ref1_clk, acmu_ref2_clk, acmu_ref3_clk, and acmu_ref4_clk) are received through a first multiplexer stage 240 and a second multiplexer stage 250, including the measurement clock signal (e.g., Cmu_measure_clk) to provide the measurement clock signal (Fmu_measure_clk) and the reference clock signal (Fmu_ref_clk). In addition, reference clock signals (acmu_ref1_clk, acmu_ref2_clk, acmu_ref3_clk and acmu_ref4_clk) and core clock signals (e.g., Cmu_core_clk) are provided to programmable timer 232.

[0035] like Figure 2As shown, current in-chip clock monitoring solutions involve routing safety-critical clocks from different subsystems to the ACMU 200 in a converged manner. Although the ACMU is shown as a single device, it should be recognized that multiple ACMUs within the ACMU 200 are typically implemented in the SoC for redundancy reasons (e.g., monitoring the same clock by two clock monitors) and to cover a wide clock set across the SoC. In operation, the ACMU 200 sends multiplexing select (MUXSEL override), divider value (DIV value override), and clock gating enable (CGC enable) signals to the subsystems. Additionally, the ACMU 200 monitors the selected clock for any frequency changes that correspond to the expected frequency recorded in an internal lookup table (LUT). In various aspects of this disclosure, the ACMU 200 selects different clocks for monitoring in a polling manner. In other aspects, as specified, continuous monitoring is performed by dedicating certain ACMUs to certain specific clocks. In implementation, the ACMU 200 can be incorporated into an automotive chip.

[0036] Automotive System-on-Chip (SoC) running safety-critical applications includes multiple safety features in the hardware to provide automotive safety integrity level (ASIL-A / ASIL-B / ASIL-C / ASIL-D) compliance. One important design aspect for the safety functionality of any chip is the generation and propagation of clocks for digital logic. Automotive SoCs can use an Automotive Clock Monitoring Unit (ACMU) as an on-chip hardware safety feature to detect and report any faults in the clocks used by safety-critical subsystems. Current ACMU hardware is designed under the assumption that the clock frequency and clock operating state are static and remain static during the continuous operation of the safety-critical subsystems. Unfortunately, static voltage and frequency conditions can lead to thermal problems that require hardware mitigation in the form of voltage / frequency reductions to save energy. Furthermore, different safety-critical subsystems involve different voltage and frequency specifications, making fixed-frequency solutions suboptimal in terms of power consumption.

[0037] Various aspects of this disclosure relate to providing a clock monitoring subsystem for providing dynamic clock voltage scaling (DCVS) and / or dynamic frequency scaling (DFS) (DCVS / DFS) support in automotive chips. In various aspects of this disclosure, DCVS / DFS schemes are described in which distributed software / hardware entities dynamically change the clock frequency without the knowledge of a centralized power management or voltage / clock control entity. In various aspects of this disclosure, the ACMU is configured and maintained by security manager software that operates with a higher level of security compared to subsystem software that manages dynamic frequency scaling of the subsystem clock.

[0038] Figure 3 This is a block diagram illustrating examples of a clock monitoring system 300 according to various aspects of the present disclosure. The clock monitoring system 300 supports a DFS interface 302 from the security subsystem clock controller 110 to the CCC 140 to the SMSS 170 to the ACMU 200. According to various aspects of the present disclosure, the clock monitoring system 300 operates by funneling frequency words (FREQ_WORD) (e.g., SS_FREQ_WORD[15:0]) from a frequency word multiplexer of the security subsystem clock controller 110 to the ACMU 200. For example, the security subsystem clock controller 110 includes a frequency word multiplexer (FREQ_WORD_MUX) 320 that funnels SS_FREQ_WORD to the CCC 140 via the DFS interface 302. Additionally, the CCC 140 includes a FREQ_WORD_MUX 350 that funnels the CCC frequency words (CCC_FREQ_WORD[15:0]) to the SMSS 170. Similarly, the SMSS 170 includes the FREQ_WORD_MUX 380, which aggregates the SMSS frequency words (SMSS_FREQ_WORD[15:0]) into the ACMU 200.

[0039] In various aspects of this disclosure, FREQ_WORD is aggregated from the security subsystem clock controller 110 to the ACMU 200 in the same manner as the subsystem clock is aggregated. Specifically, the aggregation of FREQ_WORD can use the same MUX selection value used for aggregation clocks. In any time frame, the FREQ_WORD arriving at the ACMU 200 corresponds to the clock selected by the ACMU 200 for monitoring. In various aspects of this disclosure, each FREQ_WORD_MUX (e.g., 320, 350, 380) and each clock debugging MUX (e.g., 120, 150, 190) shares the same multiplexer select line to receive the multiplexer (MUX) select signal.

[0040] Figure 4 This is a block diagram illustrating a clock controller configured according to various aspects of this disclosure, utilizing frequency word multiplexing functionality. For example... Figure 4 As shown, the clock controller 400 receives an input clock signal from the root clock generator (RCG) 402. This input clock signal is routed to a first clock branch control (CBC) 410 and a clock divider 404, which routes the divided clock signal to a second CBC 412. In this example, the first CBC 410 outputs clock signal A (CLK_A) to the ACMU CLK MUX 420, and the second CBC 412 outputs clock signal B (CLK_B) to the ACMU CLK MUX.

[0041] In various aspects of this disclosure, the CLK_A signal includes an associated frequency word (FREQ_WORD_A) carrying frequency information of the CLK_A signal in a predefined format. Similarly, the CLK_B signal includes an associated frequency word (FREQ_WORD_B) carrying frequency information of the CLK_B signal in a predefined format. In this example, FREQ_WORD_A and FREQ_WORD_B are routed to the FREQ WORD MUX 430, which outputs the selected frequency word in response to the multiplexer select (ACMU_CLK_MUX_SEL) signal. Additionally, the ACMU_CLK_MUX_SEL signal also selects the associated clock signal (e.g., CLK_A / CLK_B).

[0042] In various aspects of this disclosure, the FREQ_WORD format is defined as follows. For example, in this FREQ_WORD format, FREQ_WORD

[15] indicates CLK_DISABLE (e.g., the clock is gated). Additionally, FREQ_WORD[14:1] provides a frequency field to indicate the specified adjusted clock frequency level. For example, the clock frequency level can be defined using multiples of 1.92. In this example, 500MHz is represented in binary as 300 / 1.92 = 156. Similarly, FREQ_WORD[0] = 1 is an invalid bit used to indicate whether the frequency level provided by FREQ_WORD[14:1] is invalid.

[0043] In various aspects of this disclosure, the subsystem software driver is responsible for configuring frequency changes to the subsystem clock. For example, the subsystem software driver may execute the following sequence to configure a frequency change. First, the subsystem software driver sets FREQ_WORD[14:1] to specified values, and the FREQ_WORD[0] bit is set to “0x1” to indicate invalidity to abort clock monitoring. Once these fields of FREQ_WORD are set, the subsystem software driver initiates a frequency change. Once initiated, the subsystem software driver is configured to perform a check that monitors whether the frequency change is complete. Once the frequency change is complete, the subsystem software driver clears the FREQ_WORD[0] bit field with the value “0x0” to indicate that the clock is ready for monitoring.

[0044] In some aspects of this disclosure, if the frequency is being changed by a hardware entity, the subsystem hardware includes a mechanism for hardware-generated FREQ_WORDs of a specified format.

[0045] As shown in Table I, the Automotive Clock Monitoring Unit (ACMU) is designed to support a variety of clock monitoring options according to various aspects of this disclosure. For example, the columns of Table I include change type, change reason, motivation, monitoring mode, ACMU expectations, and usage assumptions. In this example, the first row of Table I refers to the frequency change type, which is a software (SW)-initiated frequency change for a preferred frequency level. The motivation for the frequency change may include power saving and / or thermal saving, which are the motivations for each change type indicated in Table I.

[0046] As shown in the Monitoring Mode column of Table 1, the monitored node refers to the clock-gated circuit output (e.g., clock branch unit (CBC) / power switch CBC (PSCBC) output and / or phase-locked loop (PLL) output). As shown in the ACMU Expectations column of Table I, the ACMU 200 skips monitoring during transition phases and resumes monitoring during steady state. As shown in the Usage Assumptions column of Table I, the software (SW) developed and the clock control (CC) configuration status register (CSR) trigger conforms to the Automotive Safety Integrity Level (ASIL). The remaining rows of Table I refer to the software (SW) / hardware (HW) / firmware (FW) based output clock shutdown for providing dynamic clock voltage scaling (DCVS).

[0047] Figures 5A to 5C Examples of various aspects according to this disclosure are shown. Figure 1 and Figure 2 The flowchart of the operation process of the control unit clock monitoring state machine (CMSM) 230 is shown in Figure 500. (See also...) Figure 1 and Figure 2 According to various aspects of this disclosure, the ACMU 200 performs clock monitoring based on the hardware configuration scheme of the CMSM 230. Initially, the control unit CMSM 230 enters an idle state 502 in response to a reset signal, which also resets the associated timer to track the elapsed time during the current measurement cycle. In response to a start signal asserted in the software configuration register (e.g., start, stop = 10), the control unit CMSM 230 enables timer enable (TIMER_ENABLE state 504). In timer_enable state 504, the software configuration processor clears the timer expiration interrupt (TIMER_EXP_IRQ) ​​and starts the timer. Additionally, in timer_enable state 504, the control unit CMSM 230 asserts a busy signal to indicate to the software configuration processor that clock frequency measurement has begun. In this example, the control unit CMSM 230 sets a loop counter to zero (0); this loop counter identifies the clock whose frequency is currently being measured during the measurement cycle.

[0048] In timer_enable state 504, control unit CMSM 230 determines whether the self-test bit (Self_test == 1) is asserted in the SW configuration register. If control unit CMSM 230 determines that the self-test signal is asserted, control unit CMSM 230 enters self-test (SELF_TEST) mode 506. In this example, based on the self-test, control unit CMSM 230 provides instructions and initiates FMU 220 to perform a frequency measurement on the selected measurement reference clock (the frequency to be measured) based on the selected measurement reference clock (the clock used as the measurement reference). The selected measurement reference clock is the reference clock that will be used to measure the frequency of the selected subsystem clock according to the current measurement cycle. During the self-test, control unit CMSM 230 determines whether the programmed delay timer has expired (decision box 508). The programmed delay is the time delay between initiating FMU 220 and determining whether FMU has completed the execution of the reference clock frequency measurement.

[0049] In this example, if the programmed delay timer has not yet expired, the control unit CMSM 230 remains in self-test state 506. If the programmed delay time has expired, the control unit CMSM 230 determines whether FMU 220 has completed the frequency measurement (decision box 510). If FMU 220 has not yet completed the reference clock frequency measurement, the control unit CMSM 230 remains in self-test state 506. If the control unit CMSM 230 determines that FMU 220 has completed the reference clock frequency measurement, the control unit CMSM 230 determines whether the frequency of the selected measurement reference clock is within specifications (e.g., the measured frequency is within the target frequency ± margin), for example, whether self_test_fail has occurred (decision box 512). If the measured frequency is within specifications (no self_test_fail), the control unit CMSM 230 proceeds to read configuration state 516 to begin frequency measurement of the selected subsystem clock. If the measured frequency is outside the specification (a self_test_fail occurs), the control unit CMSM 230 generates a self-test failure interrupt (SELF_TEST_FAIL_IRQ) ​​(box 514). The control unit CMSM 230 remains in self-test state 506 until the software configuration processor asserts and deasserts the stop_monitoring signal and returns the control unit CMSM 230 to self-test state 506. The software configuration processor can then clear the self-test failure interrupt.

[0050] According to the read configuration state 516, the control unit CMSM 230 increments the cycle count (e.g., when the read configuration state 516 is first reached, the cycle count is set to one (1)) and reads the measurement configuration to determine whether the clock identified by the cycle count is set for measurement. If the clock is not enabled for measurement, the control unit CMSM 230 increments the cycle count and again determines whether the clock identified by the cycle count is enabled for measurement. The control unit CMSM 230 continues this process until it determines the clock identified by the cycle count that is enabled. In this case, the control unit CMSM 230 determines whether the cycle count is greater than the maximum number of clocks (decision box 518). If the cycle count is greater than the maximum number of clocks, then all clocks for the current measurement cycle have been measured. If the cycle count is not greater than the maximum value, the control unit CMSM 230 proceeds to the clock setting state 520.

[0051] In all respects of this disclosure, Figures 5A to 5C Process 500 has been modified to support a clock monitoring subsystem for a system-on-chip (SoC) that supports dynamic clock scaling and voltage gating. In various aspects of this disclosure, the clock monitoring subsystem process supports dynamic clock voltage scaling (DCVS) and / or dynamic frequency scaling (DFS) (DCVS / DFS) processes, where distributed software / hardware entities dynamically change the clock frequency without the knowledge of a centralized software entity, such as... Figure 6A and Figure 6B As further illustrated below. The clock monitoring subsystem process 600 consists of process blocks 602 to 642, which are inserted between process blocks 520 and 522 of process 500, as shown below. Figure 6A and Figure 6B Further examples are provided.

[0052] Based on clock setting state 520, control unit CMSM 230 reads the software configuration register to generate a clock selection signal (CLK_SEL), a divider value (DIV_VAL) signal, and a gate enable signal (GATE_EN) to route (and divide) the clock identified by the current cycle count to FMU 220 for frequency measurement. Once the clock identified by the current cycle count is routed to FMU 220, control unit CMSM 230 waits for several clock cycles and then enables FMU 220 to perform frequency measurement (EN_FMU) state 522. Control unit CMSM 230 then proceeds to the current measurement complete state (CURRENT_MEASUREMENT_DONE) 524 and subsequently determines whether the frequency of the clock identified by the current cycle count is within specifications (decision box 526).

[0053] If the measured frequency is within specifications, the control unit CMSM 230 proceeds to read configuration state 516 to increment the cycle count and determines, based on the current SW configuration, whether the clock identified by the cycle count is enabled for measurement, as previously discussed. If the measured frequency is not within specifications, the control unit CMSM 230 generates a clock fault interrupt (Clk_fault_intreq) (process block 528). The control unit CMSM 230 then enters micro-idle state 530, in which it stops the timer and de-asserts the busy signal. The control unit CMSM 230 also determines whether the continue_on_fault bit in the software configuration register is asserted (decision block 532). If the continue_on_fault bit is asserted at decision block 532, the control unit CMSM 230 proceeds to process block 528 and then proceeds to increment cycle count state 535, before returning to read configuration state 516. As noted above, read configuration state 516 determines, based on the current software configuration, whether the clock identified by increment cycle count state 535 is enabled for measurement. If the continue_on_fault bit is not asserted at decision box 532, the control unit CMSM 230 remains in micro-idle state 530 and waits for software intervention.

[0054] If, in decision block 518, control unit CMSM 230 determines that the loop count is greater than the maximum value, then control unit CMSM 230 proceeds to the All_measurement_done state 534, in which it asserts the done signal. Control unit CMSM 230 then determines whether the stop monitoring signal has been asserted (decision block 536). If the stop monitoring signal has been asserted, control unit CMSM 230 proceeds back to the idle state 502. If the stop monitoring signal has not been asserted, control unit CMSM 230 determines whether the timer has expired (decision block 539). If the timer has not expired, control unit CMSM 230 returns to the All_measurement_done state 534. If the timer has expired, control unit CMSM 230 determines whether to assert the one_shot signal or extended mode in the software configuration register (block 540). If the timer has not expired, control unit CMSM 230 proceeds back to the idle state 502. If the one_shot signal is asserted, the control unit CMSM 230 returns to the All_measurement_done state 534. In this case, the SW processor needs to clear any generated interrupts (box 538) and assert and deassert the stop monitoring bit to return the control unit CMSM 230 to the idle state 502.

[0055] like Figures 5A to 5C As shown, process 500 was modified to support clock monitoring subsystem process 600, in which the distributed software / hardware entity dynamically changes the clock frequency without the knowledge of the centralized software entity, such as... Figure 6A and Figure 6B Further illustrated. In various aspects of this disclosure, when decision block 526 determines that the clock is out of range, micro-idle state 530 is modified. Instead of returning to read configuration state 516, decision block 650 is added to determine whether the fault iteration flag is equal to zero (Fault_iteration_flag == 0). If the fault iteration flag is equal to zero, control flow proceeds to increment loop count state 535 and returns to read configuration state 516, as described above. If the fault iteration flag is not equal to zero, control flow proceeds to process block 652, where the pre-interrupt iteration count (num_iteration_before_irq) is incremented and the clock fault interrupt request (clk_fault_intreq) is stored. Once incremented and stored, control flow returns to read configuration state 516.

[0056] In various aspects of this disclosure, from micro-idle state 530, decision box 654 is added to determine whether to assert the remonitoring flag during a fault (Re_monitor_during_fault == 1). When this flag is asserted, decision box 656 determines whether the num_iteration_before_irq value is less than the maximum iteration before interruption (Max_iteration_before_irq) value. When decision box 656 is true, the control flow branches to process box 652. Otherwise, the control flow branches to process box 528, as described above.

[0057] Figure 6A and Figure 6B A flowchart illustrating a clock monitoring subsystem process 600 supporting dynamic clock scaling and voltage gating for a System-on-Chip (SoC) is provided according to various aspects of this disclosure. In various aspects of this disclosure, the clock monitoring subsystem process 600 provides a solution in which distributed software / hardware entities dynamically change the clock frequency without the knowledge of a centralized software entity. Additionally, Figure 6A and Figure 6B The clock monitoring subsystem process 600 shown provides a hardware-based communication solution for seamlessly transitioning the ACMU 200 to different frequency monitoring nodes without software latency, while adhering to the Fault Detection Time Interval (FDTI) specification and with minimal hardware overhead.

[0058] like Figure 6A and Figure 6BAs shown, decision box 602 determines whether Dynamic Clock Voltage Scaling (DCVS) is enabled (DCVS_EN=1). If DCVS is disabled, the control branch proceeds to... Figure 5B The frequency measurement (EN_FMU) state 522 of process 500 is shown. Otherwise, DCVS is enabled, and the frequency word (LATCH_FREQ_WORD) is latched at process block 610. At decision block 620, it is determined whether the clock is disabled (CLK_DISABLE==1). When decision block 620 is true (e.g., CLK_DISABLE==1), at block 622, it is determined whether clock gating monitoring is being performed (e.g., clock_gating_monitor=1). When clock gating is enabled, at block 624, a wait is performed to complete the guard band, e.g., as shown. Figure 7A and Figure 7B As shown. Once the protection band is complete, at process block 626, the disable flag is set to zero (Flag_disable=0), and the frequency word is replaced with zero to count up to perform clock gating, after which it transitions to the EN_FMU state 522. Otherwise, the loop count increments (at block 628), and the control flow returns to the read configuration state 516.

[0059] Referring again to decision block 620, when the clock is enabled (e.g., CLK_DISABLE == 0), decision block 630 determines whether the frequency word is invalid (e.g., Invalid = 1). When the frequency word is invalid, a timer is started at block 632 (e.g., START_CLK_INVALID_TIMER). At decision block 634, it is determined whether the timer has expired (e.g., CLK_INVALID_TIMER_EXHAUST = 1). If the timer has expired, control flow returns to process block 610. Otherwise, control flow branches to micro-idle state 530. Referring again to decision block 630, if the frequency word is valid (e.g., Invalid == 0), then at process block 636, a wait is performed to complete the guard band, e.g., as... Figure 7A and Figure 7BAs shown. Once completed, at process block 638, the disable flag is set to one (Flag_disable=1), and the frequency word is replaced with DCVS up-counting, after which it transitions to EN_FMU state 522. When decision box 612 is true (e.g., if (skip_clk_when_invalid=0) & (invalid==1) & dcvs enabled & ((CLK_DISABLE=0) || ((CLK_DISABLE==1) & flag_disable==1) ?), a wait for the protection band to complete is executed at process box 614. Otherwise, control flow returns to EN_FMU state 522. Additionally, when decision box 640 is true (e.g., if (skip_clk_when_invalid=1) & (invalid=1) & dcvs enabled & (CLK_DISABLE=0)), the loop counter is incremented, and then a wait for the protection band to complete is executed at process box 642. Otherwise, control flow returns to EN_FMU state 522.

[0060] Figure 7A and Figure 7B This is a block diagram illustrating a clock frequency monitoring process 700 according to various aspects of this disclosure. In operation, the ACMU 200 obtains target frequency information from a local lookup table (LUT) register space configured by the security manager software. (See Figures 5 to...) Figure 7B As shown, the ACMU 200 continuously monitors the incoming FREQ_WORD of the selected clock between the preamble and tail guard bands for any changes. Any changes in FREQ_WORD are detected as an indication that the clock is undergoing a frequency change, and therefore the ongoing monitoring is discarded. For example, as... Figure 7A and Figure 7B As shown, after the pre-protection band 702, the ACMU 200 monitors the incoming FREQ_WORD that is set to invalid (e.g., 0x0) and determines that the clock is stable and ready for monitoring during monitoring window 704. In response, the ACMU 200 monitors clock A at process block 710.

[0061] In this example, the tail guard band triggers the end of monitoring window 704, after which a new FREQ_WORD is latched before non-monitoring window 716. After latching, the control unit CMSM 230 of ACMU 200 determines at step 714 that the INVALID bit of the new FREQ_WORD changed during tail guard band 712. In response, ACMU 200 discards monitoring of the current clock during process block 720 and continues to the next clock. According to various aspects of this disclosure, the control unit CMSM 230 of ACMU 200 may decide to wait for the frequency of the current clock to stabilize or continue monitoring to the next clock. In these aspects of this disclosure, the control unit CMSM 230 of ACMU 200 latches FREQ_WORD at the beginning of the monitoring window and continuously checks for changes in FREQ_WORD during the monitoring window. For example, the INVALID bit indicator in FREQ_WORD indicates that the frequency information carried by the FREQ_WORD bus is invalid / unreliable.

[0062] Refer again Figure 7A and Figure 7B A leading guard band 722 marks the end of the non-monitoring window 716 and the initiation of the next monitoring window 726, in which the incoming FREQ_WORD is set to invalid (e.g., 0x0), and the clock is stable and ready for monitoring. During the next monitoring window 726, the next clock B is monitored at process block 730. As noted, at step 724, monitoring of the next clock B is successfully completed at process block 730. Next, a trailing guard band 732 is followed by a leading guard band 742, which triggers monitoring of clock C at process block 740. However, in this example, during the non-monitoring window 746, the INVALID bit indicator in FREQ_WORD is asserted (e.g., 0x1). The INVALID bit indicator triggers the discarding of monitoring of clock C, and the process continues to the next clock at process block 750.

[0063] like Figure 7A and Figure 7BAs shown, during the preamble 752, the setting of the INVALID bit indicator is detected at step 754. Therefore, no monitoring is performed during the non-monitoring window 756 until a valid clock is detected at process block 760. In this example, the preamble 762 of the next monitoring window 766 is shown. In the next monitoring window 766, the INVALID bit indicator is deasserted (e.g., 0x0), and the clock is stable and ready for monitoring. Therefore, clock A is monitored at process block 770. However, at step 772, the INVALID bit indicator is asserted, which initiates the non-monitoring window 776. During the non-monitoring window 776, a wait is performed to make the clock valid. Next, the preamble 782 initiates the next monitoring window 786, in which the INVALID bit indicator is deasserted, and the clock is stable and ready for monitoring. At process block 790, clock A is monitored again, and the monitoring of clock A is successfully completed at step 784. The next monitoring window 786 is terminated by the trailing protection belt 792.

[0064] like Figure 7A and Figure 7B As shown, the clock frequency monitoring process 700 involves several decisions that the ACMU 200 can make when a frequency change is encountered. For example, as shown in process blocks 760 and 780, the ACMU 200 waits for the clock (or FREQ_WORD) to stabilize and then re-monitors the same clock, as shown in process blocks 770 and 790. Alternatively, the ACMU 200 can discard the current monitoring and move on to monitoring the next clock, as shown in process blocks 720 and 750. Additionally, the ACMU 200 records the history of frequency changes of the clock being monitored. Also as... Figure 7A and Figure 7B As illustrated, guard band windows (e.g., 702, 712, 722, 732, 742, 752, 762, 782, and 792) are added to the control unit CMSM 230 to accommodate any differences between the clock and FREQ_WORD propagation delays. Advantageously, FREQ_WORD can be asynchronously routed from the subsystem clock controller to the ACMU 200 without the overhead of timing checks. The presence of test logic for FREQ_WORD and the mux selection structure further enhances the reliability of the ACMU 200 design.

[0065] In various aspects of this disclosure, the ACMU 200 supports Dynamic Frequency Scaling (DFS) using external frequency information (e.g., on a per-clock basis), allowing DFS features to be selectively applied to certain clocks. In operation, communication from the subsystem clock controller to the ACMU 200 is performed in hardware and occurs over a predetermined time period (e.g., hundreds of nanoseconds). In contrast, software-based solutions produce significant variable delays down to milliseconds. Furthermore, the proposed solution is scalable to include additional subsystems in the DFS scheme without altering the design of the ACMU 200 or the control unit CMSM 230.

[0066] Figure 8 A block diagram illustrating an example transportation system 800 according to various aspects of this disclosure is shown. In this example, the transportation system 800 belongs to an automobile system; however, it should be understood that other types of systems may employ clock monitoring systems as described herein.

[0067] The vehicle system 800 includes an integrated circuit (IC) 810, which can be configured as a system-on-a-chip (SoC). The IC 810 includes one or more central processing unit (CPU) / graphics processing unit (GPU) / neural signal processor (NSP) / digital signal processing (DSP) cores 820, which in turn include a set of clock generators driven by a set of phase-locked loops (PLLs). This set of clock generators generates clocks CLK0 to CLKN to drive the data processing operations of the set of CPU / GPU / NPU / DSP cores 820.

[0068] IC 810 also includes a set of one or more clock monitoring units (e.g., ACMU 830-0 to ACMU 830-N) configured to receive the set of clocks CLK0 to CLKN, for example, via multiple clock routing lines, as discussed. ACMU 830-0 to ACMU 830-N are also configured to receive PLL lock detection / status signals PLL0 to PLLN from the set of PLLs, respectively. Each of ACMU830-0 to ACMU 830-N can use SMSS 170 according to ACMU 200 (e.g., as...). Figure 1 and Figure 2 The IC 810 also includes a software (SW) configuration processor 840 to configure the set of ACMUs 830-0 to 830-N as previously discussed. ACMUs 830-0 to 830-N are configured to generate a set of interrupts IRQ0 to IRQN, as previously discussed, in the event of any clock failure, PLL failure, timer expiration failure, and / or self-test failure, as well as a change in clock frequency.

[0069] IC 810 also includes an Error Management Module (EMM) 850 (or Safety Processor) configured to receive one or more interrupts from the set of interrupts IRQ0 to IRQN in the event that one or more corresponding faults are detected by the set of ACMUs 830-0 and 830-N. The EMM 850 generates a fault response (FAULT_RESP) based on the received interrupts from the set of interrupts IRQ0 to IRQN. For example, the CPU / GPU / NPU / DSP core 820 may generate one or more warnings to the operator (driver) associated with the vehicle system 800, and / or disable any one or more components of the vehicle control subsystem 860, and / or activate some components and / or deactivate other components of the vehicle control subsystem 860. This is done to ensure the safety of the occupants of the associated vehicle and others who may collide with the vehicle.

[0070] The vehicle control subsystem 860 may include components such as a cruise control subsystem, a forward collision warning (FCW) subsystem, a lane departure warning (LDW) subsystem, a blind spot detection (BSD) warning subsystem, an adaptive cruise control (ACC) subsystem, a lane keeping assist (LKA) subsystem, an ACC subsystem with lane keeping, a traffic jam assist subsystem, a full highway automated driving subsystem, a full city automated driving subsystem, an automated taxi / shuttle subsystem, and an autonomous delivery fleet subsystem. The processes or operations of ACMU 830, for example, in... Figure 9 As shown in the image.

[0071] Figure 9 This is a process flowchart illustrating a method for a monitoring unit with an architecture in which clock and voltage are dynamically scaled, according to various aspects of this disclosure. Method 900 begins at block 902, where a set of clocks is generated. For example, as... Figure 8 As shown, IC 810 also includes a set of one or more clock monitoring units (e.g., ACMU 830-0 to ACMU 830-N) configured to receive the set of clocks CLK0 to CLKN, for example, via the serial clock routing pipeline in question.

[0072] At box 904, a selected clock from this set of clocks is routed via one or more clock routing subsystems for frequency measurement. For example, as... Figure 1 As shown, FMU 220 is configured to process a selected clock, or more specifically, to measure the frequency of a selected clock based on a selected reference clock, and to generate a value indicating such frequency at a frequency measurement output coupled to the input of CMSM 230. According to various aspects of this disclosure, ACMU 200 in Figure 2 Further examples are provided below.

[0073] At box 906, after routing the selected clock via the clock routing subsystem, the frequency of the selected clock is adjusted. For example, as... Figure 4 As shown, the FREQ_WORD format is defined as follows. For example, in this FREQ_WORD format, FREQ_WORD

[15] indicates CLK_DISABLE (e.g., the clock is gated). Additionally, FREQ_WORD[14:1] provides a frequency field to indicate the specified adjusted clock frequency level. For example, the clock frequency level can be defined using multiples of 1.92. In this example, 500MHz is represented in binary as 300 / 1.92 = 156. Similarly, FREQ_WORD[0] = 1 is an invalid bit used to indicate whether the frequency level provided by FREQ_WORD[14:1] is invalid.

[0074] At box 908, a sideband signal is communicated to indicate the adjusted frequency of the selected clock. For example, as... Figure 3 As shown, FREQ_WORD is aggregated from the security subsystem clock controller 110 to the ACMU 200 in the same manner as the subsystem clock is aggregated. Specifically, the aggregation of FREQ_WORD can use the same MUX selection value used for aggregation clocks. In any time frame, the FREQ_WORD arriving at the ACMU 200 corresponds to the clock selected by the ACMU 200 for monitoring. In various aspects of this disclosure, each FREQ_WORD_MUX (e.g., 320, 350, 380) and each clock debugging MUX (e.g., 120, 150, 190) shares the same multiplexer selection line to receive the multiplexer (MUX) selection signal.

[0075] Figure 10 This is a block diagram illustrating an exemplary wireless communication system 1000 in which aspects of this disclosure may be advantageously employed. For illustrative purposes, Figure 10 Three remote units 1020, 1030, and 1050 and two base stations 1040 are shown. It should be understood that wireless communication systems may have more remote units and base stations. Remote units 1020, 1030, and 1050 include integrated circuit (IC) devices 1025A, 1025C, and 1025B, which include the disclosed dynamic clock voltage scaling architecture. It will be appreciated that other devices may also include the dynamic clock voltage scaling architecture, such as base station 1040, switching devices, and network equipment. Figure 10 The forward link signal 1080 from base station 1040 to remote units 1020, 1030 and 1050 and the reverse link signal 1090 from remote units 1020, 1030 and 1050 to base station 1040 are shown.

[0076] exist Figure 10 In the diagram, remote unit 1020 is shown as a mobile phone, remote unit 1030 is shown as a portable computer, and remote unit 1050 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a communication device, a personal digital assistant (PDA), a fixed-location data unit (such as a meter reading device), or other devices that store or retrieve data or computer instructions, or combinations thereof. Figure 10 Remote units according to aspects of this disclosure are illustrated, but this disclosure is not limited to these exemplary illustrated units. Aspects of this disclosure can be suitably used in many devices including the disclosed dynamic clock voltage scaling architecture.

[0077] Figure 11 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components, such as the inductor device structure disclosed above. Design workstation 1100 includes a hard disk 1101 containing operating system software, support files, and design software (such as Cadence or OrCAD). Design workstation 1100 also includes a display 1102 to facilitate the design of circuits 1110 (such as vehicles with a dynamic clock voltage scaling architecture). Storage medium 1104 is provided for tangibly storing the design of circuit 1110 (e.g., a dynamic clock voltage scaling architecture). The design of circuit 1110 or DCVS component 1112 can be stored on storage medium 1104 in file formats such as GDSII or GERBER. Storage medium 1104 can be a compact optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), hard disk, flash memory, or another suitable device. Furthermore, design workstation 1100 includes a drive device 1103 for accepting input from storage medium 1104 or writing output to storage medium 1104.

[0078] Data recorded on storage medium 1104 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. Data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 1104 helps facilitate the design of circuit 1110 or DCVS component 1112 by reducing the number of processes required to design semiconductor wafers.

[0079] Specific implementation examples are described in the following numbered clauses: 1. A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating, the method comprising: Generate a set of clocks; A selected clock from the set of clocks is routed via one or more clock routing subsystems for frequency measurement; After routing the selected clock through the clock routing subsystem, the frequency of the selected clock is adjusted; and The sideband signal is transmitted to indicate the adjusted frequency of the selected clock.

[0080] 2. The method according to Clause 1, wherein transmitting the sideband signal includes transmitting the sideband signal as a multiplexer (MUX) selection signal.

[0081] 3. The method according to any one of Clauses 1 or 2, the method further comprising communicating the sideband signal to initiate clock gating.

[0082] 4. The method according to any one of clauses 1 to 3, wherein conveying the sideband signal comprises: Generate frequency words to encode the adjusted frequency; and The frequency word is transmitted as a multiplexer (MUX) selection signal.

[0083] 5. The method according to Clause 4, wherein generating the frequency word comprises: Set the frequency field of the frequency word to the specified adjusted clock frequency level; and Set the invalid bit of the frequency word to invalid to stop clock monitoring.

[0084] 6. The method according to any one of clauses 1 to 5, wherein adjusting the frequency comprises: Frequency changes are initiated by the subsystem software driver; and The subsystem software driver performs a check to monitor whether the frequency change has been completed.

[0085] 7. The method according to Clause 6, further comprising: clearing invalid bits of the frequency word by the subsystem software driver to restore clock monitoring after the frequency change is completed.

[0086] 8. The method according to any one of clauses 1 to 7, wherein the method further comprises: Generate a set of reference clocks, wherein the frequency of the selected clock is determined based on the selected reference clock in the set of reference clocks; and The frequency of the selected reference clock in the set of reference clocks is determined based on another reference clock in the set of reference clocks.

[0087] 9. The method according to any one of clauses 1 to 9, the method further comprising communicating the sideband signal to reset the adjusted frequency of the selected clock.

[0088] 10. A non-transitory computer-readable medium having program code recorded thereon for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating, the program code being executed by a processor and comprising: Program code used to generate a set of clocks; Program code for routing a selected clock from the set of clocks via one or more clock routing subsystems for frequency measurement; Program code for adjusting the frequency of the selected clock after routing the selected clock through the clock routing subsystem; and Program code used to convey sideband signals to indicate the adjusted frequency of the selected clock.

[0089] 11. The non-transitory computer-readable medium according to Clause 10, wherein the program code for conveying the sideband signal includes: transmitting the sideband signal as a multiplexer (MUX) selection signal.

[0090] 12. The non-transitory computer-readable medium according to any one of Clauses 10 or 11, the non-transitory computer-readable medium further comprising program code for conveying the sideband signal to initiate clock gating.

[0091] 13. The non-transitory computer-readable medium according to any one of clauses 10 to 12, wherein the program code for conveying the sideband signal comprises: Generate frequency words to encode the adjusted frequency; and The frequency word is transmitted as a multiplexer (MUX) selection signal.

[0092] 14. The non-transitory computer-readable medium according to Clause 13, wherein the program code for generating the frequency word comprises: Program code used to set the frequency field of the frequency word to the specified adjusted clock frequency level; and Program code used to invalidate the invalid bit of the frequency word to stop clock monitoring.

[0093] 15. The non-transitory computer-readable medium according to any one of clauses 10 to 14, wherein the program code for adjusting the frequency comprises: Program code used for frequency changes initiated by the subsystem software driver; Program code for executing, by the subsystem software driver, a check to monitor whether the frequency change has been completed; and Program code used by the subsystem software driver to clear invalid bits of the frequency word to restore clock monitoring after the frequency change is completed.

[0094] 16. The non-transitory computer-readable medium according to any one of clauses 10 to 15, wherein the non-transitory computer-readable medium further comprises: Program code for generating a set of reference clocks, wherein the frequency of the selected clock is determined based on a selected reference clock from the set of reference clocks; and Program code for determining the frequency of a selected reference clock in the set of reference clocks based on another reference clock in the set of reference clocks.

[0095] 17. A transportation system, the transportation system comprising: Vehicle control subsystem; A set of one or more digital signal processing cores, the set of one or more digital signal processing cores being coupled to the vehicle control subsystem; A set of clock generators for generating a set of clocks, wherein the set of clock generators is coupled to the set of one or more digital signal processing cores; One or more clock routing subsystems, wherein a selected clock from the set of clocks is routed in the one or more clock routing subsystems for frequency measurement; and A clock monitoring unit is configured to adjust the frequency of a selected clock after it has been routed through the clock routing subsystem and to transmit a sideband signal to indicate the adjusted frequency of the selected clock.

[0096] 18. The system according to Clause 17, wherein the clock monitoring unit comprises: Clock Monitoring State Machine (CMSM); and A frequency measurement unit (FMU) is configured to process a selected clock to measure the frequency of the selected clock based on a selected reference clock, and to generate a value indicating such frequency at a frequency measurement output coupled to the input of the CMSM.

[0097] 19. The system according to any one of Clauses 17 or 18, wherein the clock monitoring unit is further configured to transmit the sideband signal as a multiplexer (MUX) selection signal.

[0098] 20. The system according to any one of Clauses 17 to 19, wherein the clock monitoring unit is further configured to generate a frequency word to encode the adjusted frequency and transmit the frequency word as a multiplexer (MUX) selection signal.

[0099] For specific firmware and / or software implementations, these methods can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media that tangibly embody instructions can be used to implement the methods described herein. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used herein, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type of memory or a particular number of memories, or the type of medium for storing memories.

[0100] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium. Examples include computer-readable media encoding data structures and computer-readable media encoding computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium that a computer can access. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compressed optical disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or other media that may be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and optical discs include: compressed optical discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, utilize lasers to reproduce data. Combinations of these should also be included within the scope of computer-readable media.

[0101] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals included on a transmission medium in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0102] Although this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made herein without departing from the technology of this disclosure as defined in the appended claims. For example, relational terms such as “above” and “below” are used for substrates or electronic devices. Of course, if the substrate or electronic device is reversed, above becomes below, and vice versa. Additionally, if it is laterally oriented, above and below may refer to the sides of the substrate or electronic device. Furthermore, the scope of this application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods, and steps described in the specification. As will be readily understood by one of ordinary skill in the art from the content of this disclosure, processes, machines, manufactures, material compositions, components, methods, or steps that currently exist or will be developed later can be utilized to perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0103] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been broadly described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0104] Using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or any combination thereof, designed to perform the functions described herein, various exemplary logic blocks, modules, and circuits described in connection with the disclosure herein can be implemented or executed. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0105] The steps or algorithms of the methods described in this disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, compressed optical disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a user terminal. Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0106] In one or more exemplary designs, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a general-purpose or special-purpose computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compressed optical disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that may be used to carry or store specified program code components in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of media. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, utilize lasers to reproduce data. Combinations of these should also be included within the scope of computer-readable media.

[0107] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating, the method comprising: Generate a set of clocks; A selected clock from the set of clocks is routed via one or more clock routing subsystems for frequency measurement; After routing the selected clock through the clock routing subsystem, the frequency of the selected clock is adjusted; as well as The sideband signal is transmitted to indicate the adjusted frequency of the selected clock.

2. The method of claim 1, wherein transmitting the sideband signal comprises transmitting the sideband signal as a multiplexer (MUX) selection signal.

3. The method of claim 1, further comprising communicating the sideband signal to initiate clock gating.

4. The method of claim 1, wherein transmitting the sideband signal comprises: Generate frequency words to encode the adjusted frequencies; as well as The frequency word is transmitted as a multiplexer (MUX) selection signal.

5. The method of claim 4, wherein generating the frequency word comprises: Set the frequency field of the frequency word to the specified adjusted clock frequency level; as well as Set the invalid bit of the frequency word to invalid to stop clock monitoring.

6. The method of claim 1, wherein adjusting the frequency comprises: Frequency changes are initiated by the subsystem software driver; as well as The subsystem software driver performs a check to monitor whether the frequency change has been completed.

7. The method of claim 6, further comprising clearing invalid bits of the frequency word by the subsystem software driver to restore clock monitoring after the frequency change is completed.

8. The method according to claim 1, further comprising: A set of reference clocks is generated, wherein the frequency of the selected clock is determined based on a selected reference clock from the set of reference clocks; as well as The frequency of the selected reference clock in the set of reference clocks is determined based on another reference clock in the set of reference clocks.

9. The method of claim 1, further comprising communicating the sideband signal to reset the adjusted frequency of the selected clock.

10. A non-transitory computer-readable medium having program code recorded thereon for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating, the program code being executed by a processor and comprising: Program code used to generate a set of clocks; Program code for routing a selected clock from the set of clocks via one or more clock routing subsystems for frequency measurement; Program code for adjusting the frequency of the selected clock after routing the selected clock through the clock routing subsystem; and Program code used to convey sideband signals to indicate the adjusted frequency of the selected clock.

11. The non-transitory computer-readable medium of claim 10, wherein the program code for conveying the sideband signal comprises: The sideband signal is transmitted as a multiplexer (MUX) selection signal.

12. The non-transitory computer-readable medium of claim 10, further comprising program code for conveying the sideband signal to initiate clock gating.

13. The non-transitory computer-readable medium of claim 10, wherein the program code for conveying the sideband signal comprises: Generate frequency words to encode the adjusted frequencies; as well as The frequency word is transmitted as a multiplexer (MUX) selection signal.

14. The non-transitory computer-readable medium of claim 13, wherein the program code for generating the frequency word comprises: Program code used to set the frequency field of the frequency word to a specified adjusted clock frequency level; and Program code used to invalidate the invalid bit of the frequency word to stop clock monitoring.

15. The non-transitory computer-readable medium of claim 10, wherein the program code for adjusting the frequency comprises: Program code used for frequency changes initiated by the subsystem software driver; Program code for executing by the subsystem software driver to check whether the frequency change has been completed; and Program code used by the subsystem software driver to clear invalid bits of the frequency word to restore clock monitoring after the frequency change is completed.

16. The non-transitory computer-readable medium of claim 10, further comprising: Program code for generating a set of reference clocks, wherein the frequency of the selected clock is determined based on a selected reference clock from the set of reference clocks; and Program code for determining the frequency of a selected reference clock in the set of reference clocks based on another reference clock in the set of reference clocks.

17. A transportation system, the transportation system comprising: Vehicle control subsystem; A set of one or more digital signal processing cores, the set of one or more digital signal processing cores being coupled to the vehicle control subsystem; A set of clock generators for generating a set of clocks, wherein the set of clock generators is coupled to the set of one or more digital signal processing cores; One or more clock routing subsystems, wherein a selected clock from the set of clocks is routed in the one or more clock routing subsystems for frequency measurement; and A clock monitoring unit is configured to adjust the frequency of a selected clock after it has been routed through the clock routing subsystem and to transmit a sideband signal to indicate the adjusted frequency of the selected clock.

18. The system of claim 17, wherein the clock monitoring unit comprises: Clock Monitoring State Machine (CMSM); and A frequency measurement unit (FMU) is configured to process a selected clock to measure the frequency of the selected clock based on a selected reference clock, and to generate a value indicating such frequency at a frequency measurement output coupled to the input of the CMSM.

19. The system of claim 17, wherein the clock monitoring unit is further configured to transmit the sideband signal as a multiplexer (MUX) selection signal.

20. The system of claim 17, wherein the clock monitoring unit is further configured to generate a frequency word to encode the adjusted frequency, and to transmit the frequency word as a multiplexer (MUX) selection signal.

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