Multilayer ceramic capacitor

Abstract

In the base portion (110), side edge portions (S1, S2) between the first side surface (113) on the width direction (W) and the plurality of internal electrode layers (150) and between the second side surface (114) and the plurality of internal electrode layers (150) are composed of the clad layer (160) containing Si and K.

Description

Technical Field

[0001] This disclosure relates to multilayer ceramic capacitors. Background Technology

[0002] As prior art literature disclosing the structure of a stacked electronic component, there is Japanese Patent Application Publication No. 2021-19010 (Patent Document 1). The stacked electronic component described in Patent Document 1 has a ceramic substrate and external electrodes. In the ceramic substrate, ceramic layers and internal electrode layers are alternately stacked. Side edges are formed by sintering ceramic blanks.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-19010 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Ceramic blanks contain ceramic particles, which are sintered to form side edges. However, if moisture seeps into the interface between the sintered ceramic grains, a problem arises where reliability is reduced. Therefore, it is necessary to form the side edges by including multiple ceramic grains in the thickness direction of the side edges. Consequently, the side edges need to be set to a certain thickness or more, allowing for further miniaturization and scaling up of multilayer ceramic capacitors.

[0008] This disclosure was made in view of the above-mentioned problems, and its purpose is to provide a multilayer ceramic capacitor that is miniaturized and has a large capacitance by thinning the side edges, ensuring moisture resistance, and expanding the configurable area of ​​the internal electrode layer.

[0009] Solution for solving the problem

[0010] The multilayer ceramic capacitor based on this disclosure includes a substrate and external electrodes. The substrate comprises multiple dielectric layers and multiple internal electrode layers stacked in a stacking direction, and has a first main surface and a second main surface opposite each other in the stacking direction, a first side surface and a second side surface opposite each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite each other in a length direction orthogonal to both the stacking direction and the width direction. External electrodes are respectively disposed on the first end surface and the second end surface and are electrically connected to the multiple internal electrode layers. In the substrate, the side edges located between the first side surface and the multiple internal electrode layers in the width direction and between the second side surface and the multiple internal electrode layers are composed of a cladding layer containing Si and K.

[0011] The effects of the invention

[0012] According to this disclosure, in multilayer ceramic capacitors, it is possible to suppress the reduction of moisture resistance and to make them smaller and have larger capacitance. Attached Figure Description

[0013] Figure 1 This is a perspective view schematically showing the appearance of a stacked ceramic capacitor according to an embodiment.

[0014] Figure 2 This is a perspective view schematically showing the substrate portion of a multilayer ceramic capacitor according to an embodiment.

[0015] Figure 3 Observe from the direction of the arrow on line III-III Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0016] Figure 4 Observe from the direction of the arrow on line IV-IV Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0017] Figure 5 Observe from the direction of the arrow on the VV line Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0018] Figure 6 Observe from the direction of the arrow on line VI-VI Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0019] Figure 7 This is a schematic cross-sectional view illustrating the details of the side edge portion of the multilayer ceramic capacitor used to explain the embodiment.

[0020] Figure 8 This is a schematic cross-sectional view illustrating the details of the outer layer of the multilayer ceramic capacitor used to explain the embodiments.

[0021] Figure 9 This is a schematic cross-sectional view illustrating the details of the end edges and external electrodes of the multilayer ceramic capacitor used to explain the embodiments.

[0022] Figure 10 This is a schematic cross-sectional view showing the detailed structure of the external electrodes of the multilayer ceramic capacitor according to the embodiment.

[0023] Figure 11 This is a schematic cross-sectional view used to illustrate the offset in the width direction of the protruding portion of the internal electrode layer in the multilayer ceramic capacitor of the embodiment.

[0024] Figure 12 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment.

[0025] Figure 13 This is a schematic cross-sectional view illustrating the details of the end edge and external electrodes of a modified example of a multilayer ceramic capacitor.

[0026] Figure 14 This is a flowchart illustrating a modified example of a multilayer ceramic capacitor manufacturing method. Detailed Implementation

[0027] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the figures. Furthermore, in the embodiments shown below, the same reference numerals are used to label the same or common parts, and their descriptions will not be repeated. In the figures, L represents the length direction of the base portion described later, W represents the width direction of the base portion, and T represents the stacking direction of the base portion.

[0028] Figure 1 This is a perspective view schematically showing the appearance of a stacked ceramic capacitor according to an embodiment. Figure 2 This is a perspective view schematically showing the substrate portion of a multilayer ceramic capacitor according to an embodiment. Figure 3 Observe from the direction of the arrow on line III-III Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown. Figure 4 Observe from the direction of the arrow on line IV-IV Figure 1 A schematic cross-sectional view of the stacked ceramic capacitor shown. Figure 5 Observe from the direction of the arrow on the VV line Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown. Figure 6 Observe from the direction of the arrow on line VI-VI Figure 3 A schematic cross-sectional view of the stacked ceramic capacitor shown.

[0029] like Figures 1 to 6 As shown, the multilayer ceramic capacitor 100 of the embodiment includes a substrate 110 and external electrodes. The multilayer ceramic capacitor 100 includes a first external electrode 120 and a second external electrode 130 as external electrodes.

[0030] like Figure 1 As shown, the base portion 110 has a generally cuboid shape. The base portion 110 has a first main surface 111 and a second main surface 112 that are opposite each other in the stacking direction T, a first side surface 113 and a second side surface 114 that are opposite each other in the width direction W that is orthogonal to the stacking direction T, and a first end surface 115 and a second end surface 116 that are opposite each other in the length direction L that is orthogonal to the stacking direction T and the width direction W.

[0031] Preferably, the base portion 110 has rounded corners at its corners and edges. Here, the corners are the parts where three sides of the base portion 110 intersect, and the edges are the parts where two sides of the base portion 110 intersect.

[0032] like Figure 1 and Figures 3-6 As shown, the first external electrode 120 is disposed on the first end face 115. Specifically, the first external electrode 120 is formed entirely on the first end face 115, and is formed in such a manner that it extends from the first end face 115 around to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. Figure 5 and Figure 6 As shown, the first external electrode 120 includes an extension portion 120E extending from the first end face 115 toward the first side face 113 and the second side face 114, respectively.

[0033] like Figure 1 and Figures 3-6 As shown, the second external electrode 130 is disposed on the second end face 116. Specifically, the second external electrode 130 is formed integrally on the second end face 116, and is formed such that it extends from the second end face 116 around to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. Figure 5 and Figure 6 As shown, the second external electrode 130 includes an extension portion 130E extending from the second end face 116 toward the first side face 113 and the second side face 114, respectively.

[0034] Furthermore, the detailed structures of the first external electrode 120 and the second external electrode 130 will be described later.

[0035] like Figures 2-6 As shown, the substrate 110 includes a laminate 101 and a cladding layer 160. The cladding layer 160 contains Si and K.

[0036] The laminate 101 has a pair of main surfaces 101a and 101b opposite each other in the lamination direction T, a pair of side surfaces 101c and 101d opposite each other in the width direction, and a pair of end surfaces 101e and 101f opposite each other in the length direction. The pair of main surfaces 101a and 101b, the pair of side surfaces 101c and 101d, and the pair of end surfaces 101e and 101f are covered by a cover layer 160. The cover layer 160 is located on the first side surface 113, the second side surface 114, the first main surface 111, and the second main surface 112. At the first end surface 115 and the second end surface 116, a plurality of dielectric layers 140 are covered by the cover layer 160.

[0037] like Figures 2 to 4 As shown, the laminate 101 has a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 that are alternately stacked along the stacking direction T.

[0038] The plurality of internal electrode layers 150 include a plurality of first internal electrode layers 151 and a plurality of second internal electrode layers 152. The plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are stacked alternately in the stacking direction T.

[0039] Multiple first internal electrode layers 151 are led out to end face 101e. The multiple first internal electrode layers 151 are electrically connected to the first external electrode 120. Multiple second internal electrode layers 152 are led out to end face 101f. The multiple second internal electrode layers 152 are electrically connected to the second external electrode 130. The two ends of the multiple first internal electrode layers 151 and the multiple second internal electrode layers 152 in the width direction W are exposed on the side surfaces 101c and 101d.

[0040] In addition, Figures 2 to 4 The example shown depicts seven sheets of each of the first internal electrode layer 151 and the second internal electrode layer 152, but the number of sheets of each is not limited to seven. The number of internal electrode layers 150 is preferably one or more and 1000 or more. The thickness of the internal electrode layer 150 is preferably 0.3 μm or more and 0.8 μm or less.

[0041] like Figure 5 As shown, the first internal electrode layer 151 includes a first opposing portion 151C and a first lead-out portion 151X. The first opposing portion 151C opposes a second internal electrode layer 152 adjacent in the stacking direction T. The first lead-out portion 151X connects the first opposing portion 151C and the first external electrode 120. The first lead-out portion 151X extends toward the first end face 115. The first opposing portion 151C and the first lead-out portion 151X are integrally formed.

[0042] The first inner electrode layer 151 has a first narrow portion 151N on the side opposite to the side connected to the first outer electrode 120 in the length direction L. The width of the first narrow portion 151N in the width direction W is narrower than the width of the central portion in the length direction L of the first inner electrode layer 151 in the width direction W. In the width direction W, the width W2 of the first narrow portion 151N is smaller than the width W1 of the first opposing portion 151C.

[0043] like Figure 5 As shown, the region in the substrate portion 110 on the second end face 116 side where the adjacent internal electrode layers 150 do not overlap in the stacking direction T, i.e. the region from the end of the region where the adjacent internal electrode layers 150 overlap in the stacking direction T to the second end face 116 side, is defined as Lgap.

[0044] Alternatively, the first narrow portion 151N may not need to be formed, and the width of the portion where the first narrow portion 151N is formed may also be W1. In this case, it is preferable that the length of the protrusion 120E of the first external electrode 120 in the longitudinal direction L is shorter than the length of Lgap along the longitudinal direction L, or that the protrusion 120E is not formed.

[0045] like Figure 6 As shown, the second internal electrode layer 152 includes a second opposing portion 152C and a second lead-out portion 152X. The second opposing portion 152C opposes the first internal electrode layer 151 adjacent in the stacking direction T. The second lead-out portion 152X connects the second opposing portion 152C and the second external electrode 130. The second lead-out portion 152X extends towards the second end face 116. The second opposing portion 152C and the second lead-out portion 152X are integrally formed.

[0046] The second inner electrode layer 152 has a second narrow portion 152N on the side opposite to the side connected to the second outer electrode 130 in the length direction L. The width of the second narrow portion 152N in the width direction W is narrower than the width of the central portion in the length direction L of the second inner electrode layer 152 in the width direction W. In the width direction W, the width W4 of the second narrow portion 152N is smaller than the width W3 of the second opposing portion 152C.

[0047] like Figure 6 As shown, the region in the substrate portion 110 on the first end face 115 side where the adjacent internal electrode layers 150 do not overlap in the stacking direction T, that is, the region from the end of the region where the adjacent internal electrode layers 150 overlap in the stacking direction T to the first end face 115, is defined as Lgap.

[0048] Alternatively, the second narrow portion 152N may not need to be formed, and the width of the portion where the second narrow portion 152N is formed may also be W3. In this case, it is preferable that the length of the protrusion 130E of the second external electrode 130 in the longitudinal direction L is shorter than the length of Lgap along the longitudinal direction L, or that the protrusion 130E is not formed.

[0049] The first internal electrode layer 151 and the second internal electrode layer 152 each comprise a metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy comprising that metal. In this embodiment, the first internal electrode layer 151 and the second internal electrode layer 152 each comprise Ni as the main component. Alternatively, the first internal electrode layer 151 and the second internal electrode layer 152 may also comprise dielectric particles of the same composition as the ceramic contained in the dielectric layer 140. Furthermore, the first internal electrode layer 151 and the second internal electrode layer 152 may each comprise Sn at the interface between themselves and the dielectric layer 140.

[0050] The plurality of dielectric layers 140 includes an outer dielectric layer located between the inner electrode layer 150 on the side closest to the first main surface 111 in the stacking direction T and the inner electrode layer 150 on the side closest to the second main surface 112 in the stacking direction T, and an inner dielectric layer located between adjacent inner electrode layers 150 in the stacking direction T. The number of dielectric layers 140 is preferably 100 or more and 1000 or less. The thickness of the dielectric layer 140 is preferably 0.4 μm or more and 0.8 μm or less.

[0051] Each of the multiple dielectric layers 140 can use a dielectric ceramic as the ceramic material, for example, containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, materials formed by adding by-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components can also be used.

[0052] like Figure 3 and Figure 4 As shown, the substrate portion 110 is divided into an inner layer portion C, a first outer layer portion X1 and a second outer layer portion X2, a first side edge portion S1 and a second side edge portion S2, a first end edge portion E1 and a second end edge portion E2. The inner layer portion C has electrostatic capacitance by being stacked in the lamination direction T through the first opposing portion 151C of the first internal electrode layer 151 (described later) and the second opposing portion 152C of the second internal electrode layer 152 (described later).

[0053] The first outer layer X1 and the second outer layer X2 sandwich the inner layer C in the stacking direction T. The first outer layer X1 is located outside the inner layer C in the stacking direction T, on the side of the first main surface 111. That is, the first outer layer X1 is located closer to the first main surface 111 than the inner electrode layer 150 located closest to the first main surface 111 in the stacking direction T. The second outer layer X2 is located outside the inner layer C in the stacking direction T, on the side of the second main surface 112. That is, the second outer layer X2 is located closer to the second main surface 112 than the inner electrode layer 150 located closest to the second main surface 112 in the stacking direction T.

[0054] The first outer layer X1 and the second outer layer X2 extend in the length direction L and the width direction W respectively, in a manner that includes the ridge portion of the base portion 110. The thickness of each of the first outer layer X1 and the second outer layer X2 is preferably 10 μm or more and 30 μm or less.

[0055] Both the first outer layer X1 and the second outer layer X2 include an outermost outer layer disposed on the outermost side and an inner outer layer disposed inside the outermost outer layer. The outermost outer layer is composed of a covering layer 160. The inner outer layer is composed of an outer dielectric layer.

[0056] like Figure 3 As shown, the first end edge E1 and the second end edge E2 clamp the inner layer C in the length direction L. The first end edge E1 is located outside the inner layer C in the length direction L, on the side of the first end face 115. The second end edge E2 is located outside the inner layer C in the length direction L, on the side of the second end face 116.

[0057] like Figures 4 to 6 As shown, the side edges in the substrate 110 are located between the first side surface 113 in the width direction W and the plurality of internal electrode layers 150, and between the second side surface 114 and the plurality of internal electrode layers 150. The side edges are formed by a covering layer 160. The covering layer 160 covers both ends of the plurality of internal electrode layers 150 in the width direction W.

[0058] Specifically, a first side edge S1 is provided on the side surface 101c of the aforementioned laminate. The first side edge S1 is provided in such a way that it completely covers the side surface 101c. The first side edge S1 exists in the substrate portion 110 from one end of the inner electrode layer 150 on one side in the width direction W to the first side surface 113. That is, a covering layer 160 is formed on one end in the width direction W of the central portion in the length direction L of each of the plurality of inner electrode layers 150.

[0059] A second side edge portion S2 is provided on the side surface 101d of the aforementioned laminate. The second side edge portion S2 is provided in such a way that it completely covers the side surface 101d. The second side edge portion S2 exists in the substrate portion 110 from the other end of the inner electrode layer 150 located on the other side in the width direction W to the second side surface 114. That is, a covering layer 160 is formed on the other end of the width direction W of the central portion in the length direction L of each of the plurality of inner electrode layers 150.

[0060] The specifications of the multilayer ceramic capacitor 100, which includes a substrate 110, a first external electrode 120 and a second external electrode 130, are not particularly limited, but the following ranges can be used for example.

[0061] like Figure 3 As shown, the length dimension L (length dimension L0) of the multilayer ceramic capacitor 100 is, for example, 0.1 mm or more and 3.2 mm or less. The thickness dimension T (thickness dimension T0) of the multilayer ceramic capacitor 100 in the stacking direction is 0.05 mm or more and 1.6 mm or less. Figure 4 As shown, the width dimension W (width dimension W0) of the multilayer ceramic capacitor 100 is, for example, 0.05 mm or more and 1.6 mm or less.

[0062] The multilayer ceramic capacitor 100 has, for example, specifications with a length L0 of 0.1 mm, a width W0 of 0.05 mm, and a thickness T0 of 0.05 mm; or specifications with a length L0 of 0.6 mm, a width W0 of 0.3 mm, and a thickness T0 of 0.3 mm; or specifications with a length L0 of 1.0 mm, a width W0 of 0.5 mm, and a thickness T0 of 0.5 mm; or specifications with a length L0 of 1.6 mm, a width W0 of 0.8 mm, and a thickness T0 of 0.8 mm; or specifications with a length L0 of 3.2 mm, a width W0 of 1.6 mm, and a thickness T0 of 1.6 mm. Furthermore, tolerances are taken into account for the above specifications.

[0063] Figure 7 This is a schematic cross-sectional view illustrating the detailed appearance of the side edges of the multilayer ceramic capacitor used in the embodiment. Figure 7 The diagram shows a cross-section of the second side surface 114 of the base portion 110, parallel to the lamination direction T and the width direction W. In the following description, the second side edge S2 side will be described, but the same applies to the first side edge S1 side.

[0064] like Figure 7 As shown, the second side edge S2 is composed of a cladding layer 160 containing Si and K. The composition of the cladding layer 160 can be confirmed by EDX (Energy Dispersive X-ray Spectroscopy). The cladding layer 160 is amorphous, which can be confirmed by Raman spectroscopy. Furthermore, the fact that no specific crystal pattern can be detected by X-ray diffraction of the cladding layer 160 also confirms that the cladding layer 160 is amorphous.

[0065] The second side edge S2 protrudes in contact with the ends of the plurality of internal electrode layers 150 in the width direction W. Thus, a portion 161 of the covering layer 160, which covers the ends of the plurality of internal electrode layers 150 in the width direction W, is sandwiched between adjacent dielectric layers 140 in the stacking direction T of the plurality of dielectric layers 140. This shape is chosen because the shrinkage rate of the internal electrode layers 150 during firing is greater than that of the dielectric layers 140. This side edge shape increases the fixing force of the side edge relative to the sides 101c, 101d of the laminate 101. Furthermore, it helps to suppress peeling of the side edge.

[0066] The minimum thickness TS of the covering layer 160 located at the end of the plurality of internal electrode layers 150 in the width direction W is 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, the minimum thickness TS is more preferably 0.1 μm or more, and even more preferably 0.3 μm or more. The shortest distance TP between the plurality of internal electrode layers 150 and the first side surface S1 and the shortest distance TP between the plurality of internal electrode layers 150 and the second side surface S2 is 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, the shortest distance TP is more preferably 0.1 μm or more, and even more preferably 0.3 μm or more. In addition, the numerical range of the minimum thickness TS and the shortest distance TP is not limited to the above ranges.

[0067] use Figure 7 The relationship between the shape and thickness described above can be confirmed by grinding the substrate 110 from the side of the first external electrode 120 to the center of the length direction L, and observing a cross-section of the substrate 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The thinnest thickness of the coating layer 160 measured in an image obtained using a SEM (Scanning Electron Microscope) at the center of the stacking direction T of this cross-section, where the first inner electrode layer 151 or the second inner electrode layer 152 enters approximately 10 images of the field of view, is defined as the minimum thickness TS. Similarly, in this image, the shortest distance measured between the inner electrode layer 150 and the first side surface S1 or the second side surface S2 is defined as the shortest distance TP.

[0068] Figure 8 This is a schematic cross-sectional view illustrating the details of the outer layer of the multilayer ceramic capacitor used to explain the embodiment. Figure 8 The diagram shows a cross-section of the first outer layer X1 side of the substrate 110, parallel to the lamination direction T and the width direction W. In the following description, the first outer layer X1 side will be described, but the second outer layer X2 side will be described similarly.

[0069] like Figure 8 As shown, the first outer layer X1 includes an outermost layer Xa disposed on the outermost side and an inner outer layer Xb located inside the outermost layer Xa. The outermost layer Xa is composed of a covering layer 160. The inner outer layer Xb is composed of an outer dielectric layer 140.

[0070] The outer surface of the inner outer layer Xb has fine irregularities caused by the dielectric grains of the outer dielectric layer 140. The cladding layer 160 is amorphous and covers the inner outer layer Xb in a way that fills the irregularities on its outer surface, so there are almost no irregularities on the outer surface of the outermost layer Xa. Therefore, the maximum height Ha of the irregularities on the outer surface of the outermost layer Xa is smaller than the maximum height Hb of the irregularities on the outer surface of the inner outer layer Xb. As a result, the impact resistance of the outermost layer Xa can be improved, and the reduction in the moisture resistance of the multilayer ceramic capacitor 100 can be suppressed.

[0071] The minimum thickness TM of the covering layer 160 in the stacking direction T of each of the first outer layer X1 and the second outer layer X2 is 0.01 μm or more and 0.5 μm or less. Furthermore, the value range of the minimum thickness TM is not limited to the above range.

[0072] use Figure 8 The relationship between the shape and thickness described above can be confirmed by grinding the substrate 110 from the side of the first external electrode 120 to the center of the length direction L, and observing a cross-section of the substrate 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The thinnest thickness TM of the coating layer 160 in the stacking direction T, measured in an image obtained by taking a picture using a SEM (Scanning Electron Microscope) at the end of the stacking direction T of this cross-section where the first outer layer X1 or the second outer layer X2 enters the field of view, is defined as the minimum thickness TM.

[0073] Figure 9 This is a schematic cross-sectional view illustrating the detailed features of the end edges and external electrodes of the multilayer ceramic capacitor used to explain the embodiments. Figure 9 The diagram shows a cross-section of the second end edge E2 side of the substrate portion 110, parallel to the lamination direction T and the length direction L. In the following description, the second end edge E2 side will be described, but the same applies to the first end edge E1 side.

[0074] like Figure 9As shown, the external electrode includes a Cu layer 10, which contains Cu component 11 as the main component and glass component 12. The composition of the Cu layer 10 can be confirmed by EDX. A cladding layer 160 is disposed on the second end face 116, and a portion 13 of the Cu layer 10 penetrates the cladding layer 160 and is electrically connected to the second internal electrode layer 152. The cladding layer 160 is located between the plurality of dielectric layers 140 and the external electrode. Specifically, the cladding layer 160 is located between the plurality of dielectric layers 140 and the Cu layer 10. The thickness of the Cu layer 10 is 30 μm or more and 100 μm or less at the center of the stacking direction T and the width direction W. In addition, the numerical range of the thickness of the Cu layer 10 is not limited to the above range. The Cu layer 10 may also be a resin layer containing Cu component and glass component. In this case, a base metal layer is formed between the resin layer and the cladding layer 160.

[0075] Figure 7 The minimum thickness TS of the cladding layer 160 located at the ends of the plurality of internal electrode layers 150 in the width direction W is shown to be... Figure 9 The minimum thickness TE of the cladding layer 160 located between the plurality of dielectric layers 140 and the Cu layer 10 serving as an external electrode is shown.

[0076] use Figure 9 The relationship between the shape and thickness described above can be confirmed by grinding the substrate 110 from the first side 113 to the center of the width direction W, and observing a cross-section of the substrate 110 parallel to the stacking direction T and the length direction L using an electron microscope or the like. The thinnest thickness TE of the coating layer 160, measured in an image obtained by SEM at the center of the stacking direction T and the end of the length direction L of this cross-section, where the first internal electrode layer 151 or the second internal electrode layer 152 enters the field of view in about 10 images, is defined as the minimum thickness TE.

[0077] Become like Figure 9 The reason for the shape shown is that, because the cladding layer 160 contains K, the melting point of the Si contained in the cladding layer 160 is lowered to below the firing temperature of the Cu layer 10. Therefore, during the firing of the Cu layer 10, the cladding layer 160 melts, and the shrinkage force of the Cu layer 10 acts on the molten cladding layer 160, with a portion 13 of the Cu layer 10 penetrating the cladding layer 160 and connecting to the second inner electrode layer 152.

[0078] The K contained in the cladding layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. That is, the glass component 12 contains K. The closer to the second end face 116, the higher the concentration of K contained in the glass component 12. In addition, a portion of the Si contained in the cladding layer 160 enters into the Cu layer 10 to bond with the glass component 12 in the Cu layer 10. Cu diffuses from the Cu layer 10 into the Ni in the inner electrode layer 150. As a result, the adhesion between the Cu layer 10 and the inner electrode layer 150 is increased. Furthermore, the peeling of the first outer electrode 120 and the second outer electrode 130 can be suppressed.

[0079] Figure 7 The Si concentration ratio of the cladding layer 160 located at the ends of the plurality of internal electrode layers 150 in the width direction W shown is... Figure 9 The cladding layer 160 shown, located between the multiple dielectric layers 140 and the external electrode, has a high Si concentration.

[0080] Figure 7 The K concentration ratio shown is that of the coating layer 160 located at the ends of the plurality of internal electrode layers 150 in the width direction W. Figure 9 The coating layer 160 shown, located between the multiple dielectric layers 140 and the external electrode, has a high K concentration.

[0081] The concentration distribution of Si and K can also be observed from images captured by TEM (Transmission Electron Microscope) or EDX. For example, in an image obtained by TEM with the first internal electrode layer 151 or the second internal electrode layer 152 within a field of view of about one square meter, the concentration gradient of Si and K can be determined by TEM as a molar ratio of 100 mol of Ti contained in the dielectric layer 140.

[0082] With the aforementioned structure of the coating layer 160 and the external electrode, moisture resistance can be ensured using a thinner side edge, and electrical connection between the internal electrode layer 150 and the external electrode can be ensured without removing the coating layer 160 at the first end face 115 and the second end face 116 by means of sandblasting. Furthermore, the configurable area of ​​the internal electrode layer 150 can be expanded, making the multilayer ceramic capacitor 100 smaller and with a larger capacitance.

[0083] Figure 10 This is a schematic cross-sectional view showing the detailed structure of the external electrodes of the multilayer ceramic capacitor according to an embodiment. Figure 10 The diagram shows a cross-section of the substrate 110 on the side of the second external electrode 130, parallel to the lamination direction T and the length direction L. In the following description, the side of the second external electrode 130 will be described, but the same applies to the side of the first external electrode 120.

[0084] like Figure 10 As shown, the first external electrode 120 and the second external electrode 130 include a Cu layer 10 disposed on the substrate portion 110, a Ni plating layer 20 disposed on the Cu layer 10, and a Sn plating layer 30 disposed on the Ni plating layer 20.

[0085] Furthermore, the material constituting the coating can also be a metal or an alloy containing the metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au. The combined thickness of the Ni coating 20 and the Sn coating 30 is, for example, 3 μm or more and 20 μm or less.

[0086] In this embodiment, such as Figure 6 As shown, when viewed in the width direction W, the protrusion 120E overlaps only with a narrow portion 152N of the second internal electrode layer 152, which is not electrically connected to the first external electrode 120 containing the protrusion 120E, among the plurality of internal electrode layers 150. Figure 5 and Figure 10 As shown, when viewed in the width direction W, the protrusion 130E overlaps only with the narrow portion 151N of the first internal electrode layer 151, which is not electrically connected to the second external electrode 130 containing the protrusion 130E, among the plurality of internal electrode layers 150.

[0087] Therefore, it is possible to suppress the situation where the protrusion 120E is electrically connected to the end of the second inner electrode layer 152 in the width direction W and short-circuit occurs. Similarly, it is possible to suppress the situation where the protrusion 130E is electrically connected to the end of the first inner electrode layer 151 in the width direction W and short-circuit occurs.

[0088] Figure 11 This is a schematic cross-sectional view illustrating the offset in the width direction of the protruding portion of the internal electrode layer in the multilayer ceramic capacitor used to explain the embodiment. Additionally, in Figure 11 The diagram is provided for illustrative purposes to show the offset of the protruding part; the position of the protruding part is not limited to [specific location]. Figure 11 As shown in the diagram.

[0089] like Figure 11 As shown, the offset D1 in the width direction W between the protrusion 130E located on the first side 113 and the protrusion 130E located on the second side 114 is 3 μm or more. The same offset is also present in the protrusions 120E. Thus, the ends of the protrusions 120E and 130E in the width direction W are not aligned in the stacking direction T, but are offset in the width direction W.

[0090] On the other hand, such as Figure 4As shown, in a cross section of the substrate 110 located at the center of the substrate 110 along the length direction L, parallel to the stacking direction T and the width direction W, the offset of the inner electrode layers 150 adjacent to each other in the stacking direction T along the width direction W is less than 3 μm.

[0091] That is, the positional offset of the first narrow portion 151N and the second narrow portion 152N in the width direction W is greater than the positional offset of the central portion in the length direction L of the plurality of internal electrode layers 150 in the width direction W.

[0092] Therefore, it is preferable that the widths of the first narrow portion 151N and the second narrow portion 152N are greater than the maximum conceived positional offset in the width direction W of the first narrow portion 151N and the second narrow portion 152N, and are narrower than the width of the central portion in the length direction L of the plurality of internal electrode layers 150. This allows for the stable suppression of a short circuit due to electrical connection between the protrusion 120E and the end in the width direction W of the second internal electrode layer 152. Similarly, it allows for the stable suppression of a short circuit due to electrical connection between the protrusion 130E and the end in the width direction W of the first internal electrode layer 151.

[0093] The following describes a method for manufacturing the multilayer ceramic capacitor 100 according to this embodiment. Figure 12 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment.

[0094] like Figure 12 As shown, a ceramic dielectric slurry is prepared (step S1). Specifically, a ceramic dielectric slurry is prepared by dispersing and mixing ceramic dielectric powder, additive powder, binder resin, and solvent. The ceramic dielectric powder is, for example, perovskite-structured dielectric particles such as BaTiO3, CaTiO3, SrTiO3, CaZrO3, or CaHfO3. The additive powder is, for example, composed of at least one of Si compounds, Mg compounds, Mn compounds, Fe compounds, Cr compounds, Ni compounds, and Co compounds. As the binder resin, polyurethane resin, urea resin, melamine resin, epoxy resin, vinyl acetate resin, acrylic resin, or water-based polymers such as polyvinyl alcohol (PVA) or polyvinyl butyral (PVB) can be used. They can be used alone or in mixtures of two or more. The ceramic dielectric slurry can be either solvent-based or water-based. When the ceramic dielectric slurry is designed as a water-based coating, it is prepared by mixing water-soluble binders and dispersants with water-soluble dielectric raw materials.

[0095] Next, a ceramic dielectric sheet is formed (step S2). Specifically, a ceramic dielectric sheet is formed by using an extrusion coater, gravure coater, or microgravure coater to form a ceramic dielectric slurry into a sheet on a carrier film and then drying it. From the viewpoint of miniaturization and high capacitance of multilayer ceramic capacitors, the thickness of the ceramic dielectric sheet is preferably 0.4 μm or more and 0.8 μm or less.

[0096] Next, a master sheet is formed (step S3). Specifically, a master sheet with a predetermined internal electrode pattern is formed by coating a ceramic dielectric sheet with a conductive paste in a predetermined pattern. The conductive paste includes Ni powder, solvent, dispersant, and binder, and is prepared in a constant viscosity manner. As a binder, polyvinyl butyral (PVB) or polyvinyl alcohol (PVA) is used. As a coating method for the conductive paste, screen printing, inkjet printing, or gravure printing can be used. From the viewpoint of miniaturization and high capacitance of multilayer ceramic capacitors, the thickness of the internal electrode pattern is preferably 0.3 μm or more and 0.8 μm or less. In addition to preparing the master sheet with the internal electrode pattern, a ceramic dielectric sheet that has not undergone step S3 is also prepared as the master sheet.

[0097] Next, multiple master wafers are stacked (step S4). Specifically, a predetermined number of master wafers consisting only of ceramic dielectric sheets without internal electrode patterns are stacked, for example, with a thickness of 10 μm or more and 30 μm or less. A predetermined number of master wafers with internal electrode patterns are then stacked on top of these. The number of stacked master wafers with internal electrode patterns is, for example, one or more and 1000 or less. Furthermore, a predetermined number of master wafers consisting only of ceramic dielectric sheets without internal electrode patterns are then stacked on top of these, for example, with a thickness of 10 μm or more and 30 μm or less. This constitutes a master wafer group.

[0098] Next, a dielectric block is formed by pressing the master wafer assembly (step S5). Specifically, the master wafer assembly is pressed together in the stacking direction by isostatic pressing or rigid pressing to form the dielectric block. At this time, ceramic dielectric sheets are pressed at a predetermined temperature to make them adhere tightly to each other. In addition, by placing a ceramic dielectric sheet of a certain thickness on the outermost layer in the stacking direction and pressing it, the dielectric sheet with the internal electrode pattern formed can be protected.

[0099] Next, the dielectric block is broken to form a chip (step S6). Specifically, the dielectric block is broken into multiple chips in a matrix shape by cutting, dicing, or laser cutting. The dielectric block can also be broken while it is being heated to soften it.

[0100] Next, the chip is burned (step S7). Specifically, the chip is heated, thereby burning the dielectric and conductive materials contained in the chip to form a laminate 101. The burning temperature is appropriately set corresponding to the dielectric and conductive materials.

[0101] Next, a coating layer 160 is formed on the sintered chip (step S8). Specifically, the sintered laminate 101 is immersed in a solution containing Si and K, and then dried. The solution is, for example, water glass containing K.

[0102] Next, a paste that forms a Cu layer 10 is coated onto the chip (step S9). Specifically, a paste containing Cu particles and glass components is coated onto the first end face 115 and the second end face 116 of the dried substrate portion 110 and then dried.

[0103] Next, a chip coated with a paste that forms the Cu layer 10 is fired (process S10). Specifically, the substrate 110 coated with the paste that forms the Cu layer 10 is fired at a temperature of 600°C or higher and 800°C or lower. As a result, the metal components contained in the paste that forms the Cu layer 10 are sintered, and the coating layer 160 is melted. The first internal electrode layer 151 and the Cu layer 10 are electrically connected at the first end face 115, and the second internal electrode layer 152 and the Cu layer 10 are electrically connected at the second end face 116.

[0104] Next, external electrodes are formed (step S11). By sequentially plating Ni and Sn onto the Cu layer 10, a Ni plating layer 20 and a Sn plating layer 30 are formed, thereby forming the first external electrode 120 and the second external electrode 130.

[0105] By going through the series of processes described above, the multilayer ceramic capacitor 100 of the embodiment can be manufactured.

[0106] The following describes a modified example of a multilayer ceramic capacitor according to this embodiment. Furthermore, the modified multilayer ceramic capacitor has a base electrode layer containing Ni as the main component formed on the first end face 115 and the second end face 116 of the substrate portion 110. This is the main difference from the multilayer ceramic capacitor 100 of this embodiment; therefore, the same structure as the multilayer ceramic capacitor 100 of this embodiment will not be described again.

[0107] Figure 13 This is a schematic cross-sectional view illustrating the detailed features of the end edges and external electrodes of a modified example of a multilayer ceramic capacitor. Figure 13 The diagram shows a cross-section of the second end edge E2 side of the substrate portion 110, parallel to the lamination direction T and the length direction L. In the following description, the second end edge E2 side will be described, but the same applies to the first end edge E1 side.

[0108] like Figure 13 As shown, the external electrode comprises a base electrode layer 40 and a Cu layer 10. The base electrode layer 40 contains Ni as the main component, and the Cu layer 10 contains Cu component 11 as the main component and glass component 12. Alternatively, the base electrode layer 40 may also contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 140.

[0109] A base electrode layer 40 is formed on the second end face 116, a cladding layer 160 is formed on the base electrode layer 40, and a Cu layer 10 is formed on the cladding layer 160. The base electrode layer 40 is covered by the Cu layer 10.

[0110] Figure 7 The minimum thickness TS of the cladding layer 160 located at the ends of the plurality of internal electrode layers 150 in the width direction W is shown to be... Figure 13 The minimum thickness TF of the cladding layer 160 located between the base electrode layer 40 and the Cu layer 10 is shown.

[0111] like Figure 13 As shown, a portion 13 of the Cu layer 10 penetrates the cladding layer 160 and is electrically connected to the base electrode layer 40. The Cu layer 10 is electrically connected to the second inner electrode layer 152 via the base electrode layer 40.

[0112] In this modified example, the base electrode layer 40 is formed by extending from the second end face 116 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. Similarly, the base electrode layer 40 is formed by extending from the first end face 115 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114.

[0113] In the modified multilayer ceramic capacitor, the Cu layer 10 and the second inner electrode layer 152 are electrically connected via a base electrode layer 40 covering the entire second end face 116, thus enabling a stable electrical connection between the second inner electrode layer 152 and the second outer electrode 130. Similarly, the Cu layer 10 and the first inner electrode layer 151 are electrically connected via a base electrode layer 40 covering the entire first end face 115, thus enabling a stable electrical connection between the first inner electrode layer 151 and the first outer electrode 120.

[0114] The K contained in the cladding layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. A portion of the Si contained in the cladding layer 160 enters the Cu layer 10 to bond with the glass component 12 in the Cu layer 10. Cu diffuses from the Cu layer 10 into the Ni in the substrate electrode layer 40. This increases the adhesion between the Cu layer 10 and the substrate electrode layer 40. Consequently, peeling of the first external electrode 120 and the second external electrode 130 can be suppressed.

[0115] The following describes the manufacturing method of the multilayer ceramic capacitor of this modified example. Figure 14 This is a flowchart illustrating a modified example of a multilayer ceramic capacitor manufacturing method.

[0116] like Figure 14 As shown, the manufacturing method of the modified multilayer ceramic capacitor is the same as steps S1 to S6 of the manufacturing method of the multilayer ceramic capacitor 100.

[0117] After step S6, a paste is coated onto the chip to form the base electrode layer (step S17). Specifically, a paste containing Ni particles is coated onto the end faces 101e and 101f of the laminate 101 and then dried.

[0118] Next, the chip coated with a paste that forms the base electrode layer 40 is fired (step S18). Specifically, the chip is heated, thereby firing the paste containing Ni particles together with the dielectric and conductive materials contained in the chip to form the laminate 101 and the base electrode layer 40.

[0119] Next, a coating layer 160 is formed on the chip to which the base electrode layer 40 is formed (step S19). Specifically, the laminate 101 to which the base electrode layer 40 is formed is immersed in a solution containing Si and K, and then dried. The solution is, for example, water glass containing K.

[0120] Next, a paste containing Cu particles and glass components is coated onto the chip to form the Cu layer 10 (step S20). Specifically, a paste containing Cu particles and glass components is coated and dried such that it covers the base electrode layers 40 of the first end face 115 and the second end face 116 through the coating layer 160.

[0121] Next, a chip coated with a paste that forms the Cu layer 10 is fired (step S21). Specifically, the chip coated with the paste that forms the Cu layer 10 is fired at a temperature of 600°C or higher and 800°C or lower. As a result, the metal components contained in the paste that forms the Cu layer 10 are sintered, and the coating layer 160 is melted, and the base electrode layer 40 is electrically connected to the Cu layer 10.

[0122] Next, external electrodes are formed (step S22). By sequentially plating Ni and Sn onto the Cu layer 10, a Ni plating layer 20 and a Sn plating layer 30 are formed, thereby forming the first external electrode 120 and the second external electrode 130.

[0123] (Postscript)

[0124] Those skilled in the art will understand that the above exemplary embodiments are specific examples of the following solutions.

[0125] <1>

[0126] A multilayer ceramic capacitor includes: a substrate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; and external electrodes respectively disposed on the first end surface and the second end surface and electrically connected to the plurality of internal electrode layers, wherein the side edges of the substrate located between the first side surface and the plurality of internal electrode layers in the width direction and between the second side surface and the plurality of internal electrode layers are composed of a coating layer containing Si and K.

[0127] <2>

[0128] According to <1>, the multilayer ceramic capacitor comprises: a first outer layer located closer to the first main surface than the inner electrode layer of the plurality of inner electrode layers located on the first main surface side in the stacking direction; and a second outer layer located closer to the second main surface than the inner electrode layer of the plurality of inner electrode layers located on the second main surface side in the stacking direction, wherein the first outer layer and the second outer layer are respectively composed of a portion of the plurality of dielectric layers and the covering layer.

[0129] <3>

[0130] According to <1> or <2>, in the multilayer ceramic capacitor, the cladding layer is located between the plurality of dielectric layers and the external electrode.

[0131] <4>

[0132] The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the shortest distance between the plurality of internal electrode layers and the first side surface and the shortest distance between the plurality of internal electrode layers and the second side surface are 0.01 μm or more and 0.5 μm or less.

[0133] <5>

[0134] According to the multilayer ceramic capacitor described in <2>, the minimum thickness of the coating layer in the stacking direction of each of the first outer layer and the second outer layer is 0.01 μm or more and 0.5 μm or less.

[0135] <6>

[0136] The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the cladding layer is amorphous.

[0137] Through the series of processes described above, it is possible to manufacture modified multilayer ceramic capacitors.

[0138] In the above description of the embodiments, the combinable structures can also be combined with each other.

[0139] The embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The scope of the invention is defined by the claims rather than by the foregoing description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0140] Explanation of reference numerals in the attached figures

[0141] 10. Cu layer; 11. Cu composition; 12. Glass composition; 20. Ni plating; 30. Sn plating; 40. Substrate electrode layer; 100. Multilayer ceramic capacitor; 101. Laminate; 101a, 101b. Main surface; 101c, 101d. Side surface; 101e, 101f. End face; 110. Substrate; 111. First main surface; 112. Second main surface; 113. S1. First side surface; 114. S2. Second side surface; 115. First end face; 116. Second end face; 120. First external electrode; 120E, 130E. Protrusion Part; 130, second external electrode; 140, dielectric layer; 150, internal electrode layer; 151, first internal electrode layer; 151C, first opposing part; 151N, 152N, narrow part; 151X, first lead-out part; 152, second internal electrode layer; 152C, second opposing part; 152X, second lead-out part; 160, covering layer; C, inner layer part; E1, first end edge part; E2, second end edge part; S1, first side edge part; S2, second side edge part; X1, first outer layer part; X2, second outer layer part; Xa, outermost layer part; Xb, inner outer layer part.

Claims

1. A multilayer ceramic capacitor, wherein, The multilayer ceramic capacitor includes: A substrate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; and External electrodes, respectively disposed on the first end face and the second end face, are electrically connected to the plurality of internal electrode layers. In the substrate portion, the side edges located between the first side surface and the plurality of internal electrode layers in the width direction and between the second side surface and the plurality of internal electrode layers are composed of a coating layer containing Si and K.

2. The multilayer ceramic capacitor according to claim 1, wherein, The base portion includes: The first outer layer is located closer to the first main surface than the inner electrode layer that is closest to the first main surface in the stacking direction among the plurality of inner electrode layers; and The second outer layer is located closer to the second main surface than the inner electrode layer that is closest to the second main surface in the stacking direction among the plurality of inner electrode layers. The first outer layer and the second outer layer are each composed of a portion of the plurality of dielectric layers and the covering layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The coating layer is located between the plurality of dielectric layers and the external electrode.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The shortest distance between the plurality of internal electrode layers and the first side surface and the shortest distance between the plurality of internal electrode layers and the second side surface are greater than 0.01 μm and less than 0.5 μm.

5. The multilayer ceramic capacitor according to claim 2, wherein, The minimum thickness of the covering layer in the stacking direction of each of the first outer layer and the second outer layer is 0.01 μm or more and 0.5 μm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The coating layer is amorphous.

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