Semiconductor laminate and method for manufacturing a semiconductor device
By designing a layer structure with a high etch selectivity in the semiconductor stack, the problem of back-side roughness of the semiconductor layer during etching is solved, achieving flat bonding between the semiconductor layer and the transfer substrate and easy transfer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- OKI ELECTRIC INDUSTRY CO LTD
- Filing Date
- 2024-12-02
- Publication Date
- 2026-06-05
AI Technical Summary
In the prior art, when the semiconductor layer is exposed to the etching solution, the back side tends to become rough, making it difficult to bond with the transfer substrate.
A semiconductor stack structure is adopted, wherein the second layer, which is made of the same material as at least the third layer, has a higher etch selectivity. The second layer is removed by etching and the semiconductor layer is separated from the substrate and then transferred to a different transfer substrate.
It maintains the flatness of the lower surface of the semiconductor layer, improves the bonding effect between the semiconductor layer and the transfer substrate, and simplifies the transfer process of the semiconductor layer.
Smart Images
Figure CN122162530A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to methods for manufacturing semiconductor laminates and semiconductor devices. Background Technology
[0002] Previously, there were techniques for growing a semiconductor thin film on a substrate with a sacrificial layer in between, removing the sacrificial layer by etching to peel the semiconductor thin film off the substrate, and transferring it to another substrate (for example, see Patent Document 1).
[0003] Existing technical documents
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-290232 (page 10) Figure 5 ) Summary of the Invention
[0006] The problem that the invention aims to solve
[0007] However, in previous technologies, the semiconductor layer was exposed to the etching solution, which sometimes made the back side of the semiconductor layer rough and difficult to bond with the transfer substrate.
[0008] Methods for solving problems
[0009] The semiconductor stack disclosed herein comprises: a substrate; a first layer stacked over the substrate; a second layer stacked on the first layer; a third layer stacked on the second layer; and a semiconductor layer stacked on the third layer, wherein at least the layer in contact with the third layer is made of the same material as the second layer, and, when using a specified etchant, the etch selectivity of the second layer relative to the third layer is greater than the etch selectivity of the second layer relative to the first layer.
[0010] The method for manufacturing a semiconductor device disclosed herein includes the following steps: removing a second layer from a semiconductor stack using a prescribed etchant, wherein the semiconductor stack has a first layer stacked on a substrate, a second layer stacked on the first layer, a third layer stacked on the second layer, and a semiconductor layer stacked on and at least in contact with the third layer, which is made of the same material as the second layer; separating the semiconductor layer and the third layer from the substrate; removing the third layer; and transferring the semiconductor layer to a transfer substrate different from the substrate.
[0011] Invention Effects
[0012] According to this disclosure, when transferring a semiconductor layer, it becomes easier to separate the semiconductor layer from the substrate that serves as the transfer source, thereby maintaining the flatness of the lower surface of the semiconductor layer, and thus, it becomes easier to bond the semiconductor layer to the transfer substrate. Attached Figure Description
[0013] Figure 1 This is a schematic diagram illustrating the stacked structure of a stacked wafer according to Embodiment 1, which has the structure of the semiconductor stack of the present invention.
[0014] Figure 2 (A)~(C) represent the meaning of "to". Figure 1 The stacked wafers are patterned into a 4×4 defined area. (A) is its top view, and (B) is its side view. In addition, (C) is a magnified view of a block shown in (B).
[0015] Figure 3 (A)~(C) represent the meaning of "to". Figure 2 The diagrams show the further patterned state of the stacked wafers (A) to (C), where (A) is a top view and (B) is a side view. Additionally, (C) is a magnified view of a block shown in (B).
[0016] Figure 4 (A) to (C) are diagrams showing the state in which a protective film is formed in each of the laminates, with (A) being a top view and (B) being a side view. In addition, (C) is a magnified view of a block shown in (B).
[0017] Figure 5 (A) to (C) are diagrams showing the state from the protective film formed in each layer to the formation of the underlying barrier layer and the retaining structure. (A) is a top view and (B) is a side view. In addition, (C) is a partial enlarged view of a block shown in (B).
[0018] Figure 6 yes Figure 5 (C) is a top view of a block of the stack shown.
[0019] Figure 7 (A) to (D) are diagrams used to illustrate the etch progress of the sacrificial layer and the retaining layer. (A) represents the state before etching, (B) and (C) represent the process of etching, and (D) represents the state after etching.
[0020] Figure 8 It is Figure 7 The enlarged view of the area near the end of the cone-shaped retaining layer shown in (C).
[0021] Figure 9 It means that in the formation of Figure 5The diagram shows a state in which the sacrificial layer is removed by etching in a stacked wafer with a retaining structure, and the retaining layer is removed in addition to the central portion.
[0022] Figure 10 It means from Figure 9 The state is further removed from the diagram that maintains the state of the structural part.
[0023] Figure 11 It is used for Figure 10 The accompanying diagram provides further explanation.
[0024] Figure 12 It means in Figure 10 or Figure 11 The diagram shows a semiconductor thin film with an imprint head attached.
[0025] Figure 13 This diagram illustrates the process of peeling a semiconductor thin film from the retaining layer using an imprinting head.
[0026] Figure 14 (A) to (C) are diagrams showing the process of removing the upper barrier layer of the semiconductor thin film that is peeled off by the imprint head by etching. (A) represents the state before etching, (B) represents the state during etching, and (C) represents the state after etching.
[0027] Figure 15 (A) to (C) are diagrams illustrating the process of attaching a semiconductor thin film with the upper barrier layer removed to a transfer substrate to form electrodes at specified locations. (A) is a diagram showing the state of transferring the semiconductor thin film to the transfer substrate. (B) is a diagram showing the state of removing the protective film. (C) is a diagram showing the state of forming two electrodes at each specified location.
[0028] Figure 16 It is processed into Figure 9 A top view of the stacked wafers in their current state.
[0029] Figure 17 This is a diagram used to illustrate the etch process in another example.
[0030] Figure 18 This is a diagram illustrating the etching process in yet another example.
[0031] Figure 19 This diagram illustrates the etch progress of the sacrificial and retaining layers.
[0032] Figure 20 This is a schematic diagram illustrating the stacked structure of a stacked wafer according to Embodiment 2, which has the structure of the semiconductor stack of the present invention.
[0033] Figure 21 (A)~(C) represent the meaning of "to". Figure 20 The stacked wafers are patterned into a 4×4 defined area. (A) is its top view, and (B) is its side view. In addition, (C) is a magnified view of a block shown in (B).
[0034] Figure 22 (A)~(C) represent the meaning of "to". Figure 21 The diagrams show the further patterned state of the stacked wafers (A) to (C), where (A) is a top view and (B) is a side view. Additionally, (C) is a magnified view showing the multiple blocks shown in (B).
[0035] Figure 23 (A) to (C) are diagrams showing the protective film formed on each segmented laminate, with (A) being a top view and (B) being a side view. Additionally, (C) is a magnified view showing a portion of the blocks shown in (B).
[0036] Figure 24 (A)~(C) represent in Figure 23 The diagrams (A) to (C) show the protective film and part of the upper barrier layer of each groove having elongated holes. (A) is a top view, and (B) is a side view. In addition, (C) is a magnified view of the multiple blocks shown in (B).
[0037] Figure 25 Figures (A) to (D) are diagrams illustrating the etch progress of the sacrificial and retaining layers, for example, equivalent to... Figure 24 The area enclosed by the dashed line in (B). (A) represents the state before etching, (B) and (C) represent the state during etching, and (D) represents the state after etching.
[0038] Figure 26 It is Figure 25 The enlarged view shown in (C) is a partial view of the etching process near the end of the cone-shaped retaining layer.
[0039] Figure 27 (A)~(C) represent the formation of Figure 24 The diagrams (A) to (C) show a stacked wafer with elongated vias where the sacrificial layer is removed by etching, and the retaining layer is removed except for the central portion. This is equivalent to... Figure 25 (D) is the stage of (A). (A) is its top view, and (B) is its side view. In addition, (C) is a partial enlarged view of the multiple blocks shown in (B).
[0040] Figure 28 It is equivalent to Figure 27 (C) Top view.
[0041] Figure 29 It means in Figure 27 The diagram shown in (C) depicts a semiconductor thin film with an imprint head attached.
[0042] Figure 30 This diagram illustrates the process of peeling a semiconductor thin film from the retaining layer using an imprinting head.
[0043] Figure 31 It means from Figure 30 The diagram shows the state of a semiconductor thin film held by an imprint head with its upper barrier layer removed.
[0044] Figure 32 This diagram shows the state of a semiconductor thin film with the upper barrier layer removed being pasted onto a transfer substrate.
[0045] Figure 33 This is a diagram showing the state of the electrode formed after the protective film is removed. Detailed Implementation
[0046] Implementation method 1.
[0047] Figure 1 This is a schematic diagram illustrating the stacked structure of a stacked wafer 100 having the structure of the semiconductor stack of the present invention, according to Embodiment 1.
[0048] exist Figure 1 In the stacked wafer 100, the growth substrate 111, which serves as the substrate, is a substrate on which an epitaxial layer is grown, and is an InP layer. On this growth substrate (InP) 111, a buffer layer 112 as an InP layer, a lower barrier layer 113 as an InGaAs (indium gallium arsenide) layer (i.e., the fourth layer), a retaining layer 114 as an InGaAsP (indium gallium arsenide phosphide) layer (i.e., the first layer), and a sacrificial layer 115 as an InP layer (i.e., the second layer) are sequentially formed by epitaxial growth. The thickness of the retaining layer (InGaAsP) 114 is thicker than the thickness of the sacrificial layer (InP) 115, preferably more than twice as thick, and the reason for this will be explained later.
[0049] In this embodiment, the thickness of the retaining layer (InGaAsP) 114 is 100 nm to 600 nm, and the thickness of the sacrificial layer (InP) 115 is 50 nm to 300 nm. Preferably, the thickness of the retaining layer (InGaAsP) 114 is 300 nm, and the thickness of the sacrificial layer (InP) 115 is 150 nm. Dry etching is required to excavate the upper barrier layer 116, the sacrificial layer (InP) 115, and the retaining layer (InGaAsP) 114, and the dry etching is stopped midway through the lower barrier layer 113. Therefore, the thickness of the lower barrier layer 113 is preferably 700 nm or more.
[0050] Furthermore, on the sacrificial layer (InP) 115, an upper barrier layer 116, serving as an InGaAs layer (the third layer), a cladding layer 117, serving as an n-InP layer, a light-absorbing layer 118, serving as an i-InGaAs layer, a cladding layer 119, serving as a p-InP layer, and a contact layer 120, serving as a p-InGaAs layer, are sequentially formed by epitaxial growth. For example, the thickness of the upper barrier layer 116 is 100 nm to 600 nm, preferably 300 nm. Regarding the composition ratio of each InGaAs layer in this embodiment, when the In concentration is set to 0.53, the Ga concentration is 0.47, and the As concentration is 1.
[0051] Next, a method for manufacturing the semiconductor device of this embodiment, based on the preparation of the aforementioned stacked wafer 100, will be described. Furthermore, the stacked wafer 100 shown in each figure is configured such that its stacking direction is vertically upward.
[0052] Figure 2 (A)~(C) represent the meaning of "to". Figure 1 The stacked wafer 100 is patterned into a 4×4 defined area. Figure 2 (A) is its top view. Figure 2 (B) is a side view. Additionally, Figure 2 (C) is to Figure 2 The diagram shown in (B) is an enlarged representation of a block (P1 enclosed by dashed lines).
[0053] like Figure 2 As shown in (A), in order to reach the lower barrier layer (InGaAs) 113 of the stacked wafer 100 Figure 2 The stack 130, divided into 16 (4×4) layers up to (C), is etched along the lattice-shaped separation area to form lattice-shaped grooves 131a. Furthermore, the lower barrier layer (InGaAs) 113 is set to a thickness sufficient to ensure that it will not penetrate even if the upper portion is etched away. The thickness of the lower barrier layer (InGaAs) 113 is preferably thicker than the thicknesses of the retaining layer (InGaAsP) 114, the sacrificial layer (InP) 115, and the upper barrier layer (InGaAs) 116.
[0054] Figure 3 (A)~(C) represent the meaning of "to". Figure 2 A diagram showing the further patterned state of the stacked wafer 100. Figure 3 (A) is its top view. Figure 3 (B) is a side view. Additionally, Figure 3 (C) is to Figure 3 (B) is a magnified partial view of a block (P1 surrounded by dashed lines).
[0055] like Figure 3 As shown in (C), in order to remove a predetermined step width L1 from the periphery of each of the four layers from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs (120)) of each stack 130, patterning is performed by etching. As a result, a trench 131b with a width wider than the trench 131a is formed around these four layers. Hereinafter, these four layers are sometimes referred to as functional layers 133 as semiconductor layers.
[0056] Here, at the bottom layer of functional layer 133, the cladding layer (n-InP) 117, which is connected to the upper barrier layer (InGaAs) 116, is formed of the same material as the sacrificial layer (InP) 115. The same material here only needs to be formed of indium phosphide (InP), so their composition ratio can be the same or different.
[0057] Furthermore, the relationship between the step width L1, which is the length in the first direction, of the stepped portion 116a formed on the upper surface of the upper barrier layer (InGaAs) 116 and the thickness L2, which is the thickness in the second direction, of the upper barrier layer 116 is formed in the following manner.
[0058] L1≥L2 (1)
[0059] also, Figure 3 This is a schematic diagram, therefore, it does not satisfy inequality (1), but it actually does. The reason for satisfying inequality (1) will be explained later.
[0060] Figure 4 Figures (A) to (C) represent the state in which a protective film 121 is formed in each of the laminates 130. Figure 4 (A) is its top view. Figure 4 (B) is a side view. Additionally, Figure 4 (C) is to Figure 4 (B) is a magnified partial view of a block (P1 surrounded by dashed lines).
[0061] like Figure 4As shown in (A) to (C), the protective film 121 is formed in a manner that covers the stepped portions 116a of the four layers from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs (120)) – namely, the functional layer 133 and the upper barrier layer (InGaAs) 116 – of each of the etched laminates 130. The protective film 121 is made of a material that is resistant to etchants capable of removing the sacrificial layer (InP) 115 (possessing the property of not being removed by the etchant). Specifically, the protective film 121... The material used is any one of Al2O3, SiN, SiO2, etc. The protective film 121 is resistant to the etchant only to the extent that it will not be removed to the extent that it can adequately protect the functional layer 133 before the sacrificial layer (InP) 115 is removed. Thus, it is possible to prevent the upper surface and sides of the four layers of each stack 130, from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs (120)), i.e. the functional layer 133, from the sacrificial layer (InP) 117 to the contact layer (p-InGaAs (120), from being etched when the sacrificial layer (InP) 115 is removed.
[0062] Figure 5 Figures (A) to (C) show the state from the formation of the protective film 121 on each of the laminates 130 to the formation of the lower barrier layer (InGaAs) 113 that maintains the structural part 122. Figure 5 (A) is its top view. Figure 5 (B) is a side view. Additionally, Figure 5 (C) is to Figure 5 (B) is a magnified partial view of a block (P1 surrounded by dashed lines).
[0063] like Figure 5 As shown in (C), a retaining structure 122 is formed from a photoresist or the like, extending from the protective film 121 covering the stepped portion 116a of the upper barrier layer (InGaAs) 116 to the groove portion 131a of the lower barrier layer (InGaAs) 113. This retaining structure 122 is formed by removing unwanted portions of the photoresist after coating each layer with a photoresist formed from an inorganic or organic insulating film.
[0064] Figure 6 yes Figure 5 A top view of a block of the stack 130 shown in (C). Figure 6 and Figure 5 As shown in (C), the central portion of the two opposing sidewalls of the four sidewalls of each laminate 130 is formed into an L-shaped long plate.
[0065] Figure 7 Figures (A) to (D) are diagrams illustrating the etching process of the sacrificial layer (InP) 115 and the retaining layer (InGaAsP) 114. Figure 7 (A) represents the state before etching. Figure 7 (B) and (C) represent the etching process. Figure 7 (D) indicates the state after etching is complete. In addition, for simplicity, the growth substrate 111, buffer layer 112 and functional layer 133 which is above the upper barrier layer 116 are not shown here.
[0066] Hydrochloric acid, a mixture of hydrochloric acid and phosphoric acid, or a mixture of hydrochloric acid and nitric acid are used as the etchant for this etching process. In this etching, the etch rate of the sacrificial layer (InP) 115 is faster and the difference is greater than that of the upper barrier layer (InGaAs) 116. Therefore, the upper barrier layer (InGaAs) 116 is hardly etched.
[0067] Here, regarding the etch rate in each layer, the etch rate of the sacrificial layer (InP) 115 is greater than the etch rate of the retaining layer (InGaAsP) 114. In addition, the etch rate of the sacrificial layer (InP) 115 is greater than the etch rate of the upper barrier layer (InGaAs) 116.
[0068] In this etchant, the etch rate of the sacrificial layer (InP) 115 is at least 1000 times that of the upper barrier layer (InGaAs) 116 (i.e., a selectivity of at least 1000), and the etch rate of the sacrificial layer (InP) 115 is at least 2 times and less than 1000 times that of the retaining layer (InGaAsP) 114 (i.e., a selectivity of at least 2 and less than 1000). Preferably, the etch rate of the sacrificial layer (InP) 115 is 2 to 4 times that of the retaining layer (InGaAsP) 114 (i.e., a selectivity of 2 to 4).
[0069] Furthermore, here, the lower barrier layer (InGaAs) 113 is also formed of the same material as the upper barrier layer (InGaAs) 116. Therefore, similarly, the etch rate of the sacrificial layer (InP) 115 is more than 1000 times that of the lower barrier layer (InGaAs) 113. As a result, it is hardly etched during the etching of the upper retaining layer (InGaAsP) 114. In addition, this protects the buffer layer (InP) 112 and the growth substrate (InP) 111, which are located below the lower barrier layer (InGaAs) 113, from being etched.
[0070] That is, when using a predetermined etchant, the etch selectivity of the sacrificial layer (InP) 115 relative to the upper barrier layer (InGaAs) 116 is greater than the etch selectivity of the sacrificial layer (InP) 115 relative to the retaining layer (InGaAsP) 114. Furthermore, the etch selectivity of the sacrificial layer (InP) 115 relative to the lower barrier layer (InGaAs) 113 is greater than the etch selectivity of the sacrificial layer (InP) 115 relative to the retaining layer (InGaAsP) 114.
[0071] Therefore, as the sacrificial layer (InP) 115 is etched, the retaining layer (InGaAsP) 114 is also etched, but since the sacrificial layer (InP) 115 is etched first, it is etched from its upper surface. However, since the lower barrier layer (InGaAs) 113 is not etched, the retaining layer (InGaAsP) 114 is not etched from its lower surface. As a result, as... Figure 7 As shown in (A) to (C), the retaining layer (InGaAsP) 114 is etched into a cone shape on both sides.
[0072] Figure 8 It is Figure 7 The enlarged partial view of (C) showing the etching process as a cone-shaped retaining layer (InGaAsP) 114 near the end (part P2 surrounded by dashed lines).
[0073] The thickness L4 of the retaining layer (InGaAsP) 114 relative to Figure 8 The etching of the end of the retaining layer (InGaAsP) 114 shown is performed as a tapered portion. The ratio of the depth L3 to the angle θ1 of the front end is tan(θ1), which varies depending on the thickness of the sacrificial layer (InP) 115 and the pattern size.
[0074] Through
[0075] 0 <x<1 (2)
[0076] 0 <y<1 (3)
[0077] The concentrations (composition ratios) of In and P are increased by adjusting x and y of the In(x)Ga(1-x)As(y)P(1-y) composition of the holding layer (InGaAsP) 114 within a certain range, and the angle θ1 becomes larger. Specifically, (to increase the concentration of In) it is preferable that 0.7 ≤ x, and (to increase the concentration of P) it is preferable that y ≤ 0.5. If it is within this range (x is 0.7 or more, y is 0.5 or less), then the θ1 of the holding layer (InGaAsP) 114 is greater than 0, that is, the holding layer 114 becomes triangular in shape, and therefore, the semiconductor thin film 135 (described later) can be peeled back with a smaller area (vertical portion). However, in this embodiment, the composition ratio of In and P of the holding layer (InGaAsP) 114 can be infinitely close to 0, and the angle θ1 can be infinitely close to 0.
[0078] In addition, the angle θ1 can be reduced by increasing the thickness of the sacrificial layer (InP) 115, but when the thickness of the retaining layer (InGaAsP) 114 is less than twice the thickness of the sacrificial layer (InP) 115, it may be impossible to retain the required height of the retaining layer (InGaAsP) 114.
[0079] Figure 9 It means that in the formation of Figure 5 The diagram shows a state in which the sacrificial layer (InP) 115 is removed by etching in the stacked wafer 100 with the retaining structure 122, and the retaining layer (InGaAsP) 114 is removed except in the center. Figure 10 It means from Figure 9 The state further removed the diagram that maintains the state of structural part 122. Figure 11 It is used for Figure 10 The accompanying diagram provides further explanation.
[0080] like Figure 9 As shown, in the formation of Figure 5 The stacked wafer 100 with the retaining structure 122 shown is in the process of holding the structure 122. Figure 7 During the etching described in (A) to (D), a gap is created between the upper barrier layer (InGaAs) 116 and the lower barrier layer (InGaAs) 113, which are supported by the holding structure 122. Furthermore, the stacked structure from the upper barrier layer (InGaAs) 116, which serves as the upper part of the gap, to the protective film 121 is sometimes referred to as a semiconductor thin film 135.
[0081] Next, when removing the retaining structure 122 by dry etching, as Figure 10As shown, the upper barrier layer (InGaAs) 116 is partially connected to the retaining layer (InGaAsP) 114. At this time, the lower surface of the upper barrier layer (InGaAs) 116 and the upper surface of the retaining layer (InGaAsP) 114 are coupled with a force weaker than that of a covalent bond and a sufficiently small contact area.
[0082] Therefore, in the process of removing the sacrificial layer (InP) 115 by etching, the area of the upper surface of the retaining layer (InGaAsP) 114, which is the second surface in contact with the upper barrier layer (InGaAs) 116, is made smaller than the area of the lower surface, which is the first surface in contact with the lower barrier layer (InGaAs) 113.
[0083] Furthermore, such as Figure 11 As shown, when the semiconductor thin film 135 is tilted, the lower surface of the upper barrier layer (InGaAs) 116 is coupled to a portion of the upper surface of the retaining layer (InGaAsP) 114 and the upper surface of the lower barrier layer (InGaAs) 113 with a force weaker than that of covalent bonds and a sufficiently small contact area.
[0084] Additionally, in the illustration Figure 11 In this illustration, because the size of the holding layer (InGaAsP) 114 relative to the semiconductor thin film 135 is shown as a larger ratio than the actual size, the semiconductor thin film 135 is depicted as tilted. The actual thickness of the holding layer (InGaAsP) 114 is sufficiently smaller than the size of the semiconductor thin film 135. For example, in this case, the thickness (height) of the holding layer (InGaAsP) 114 is less than 0.5 μm, and the width L5 of the semiconductor thin film 135 is 100 μm; therefore, the tilt angle θ2 is...
[0085] θ2 <arctan(0.5 / 50)≒0.57°
[0086] Therefore, no problems caused by the tilting of the semiconductor thin film 135 will occur in the next process described later.
[0087] Here, as Figure 11 As shown, an example of a tilted semiconductor thin film 135 is illustrated, but as... Figure 10 As shown, depending on the residual shape of the retaining layer (InGaAsP) 114, there may be cases where the semiconductor thin film 135 is not tilted. For example, the upper part of the retaining layer 114 may be planar. Furthermore, even if the semiconductor thin film 135 is tilted, for the reasons described above, no problems caused by this tilt will occur in the next process described later.
[0088] Furthermore, as described above, in the stage prior to etching, the thickness of the retaining layer (InGaAsP) 114 is preferably more than twice the thickness of the sacrificial layer (InP) 115. Therefore, in the stage where the sacrificial layer (InP) 115 is removed by etching, for example... Figure 11 As shown, a retaining layer (InGaAsP) 114 with the height required to support the semiconductor thin film 135 can remain.
[0089] Figure 12 It means in Figure 10 or Figure 11 The diagram shows the state in which the imprint head 140 is attached to the semiconductor thin film 135. Figure 13 This diagram shows the state in which the semiconductor thin film 135 is peeled off from the retaining layer (InGaAsP) 114 by the imprint head 140.
[0090] In order to peel and move the semiconductor thin film 135 from the holding layer (InGaAsP) 114, as Figure 12 As shown, an imprint head 140 is attached to the upper surface of the protective film 121 of the semiconductor thin film 135, such as... Figure 13 As shown, the semiconductor thin film 135 is peeled off from the retaining layer (InGaAsP) 114 by the imprint head 140.
[0091] At this time, the upper barrier layer (InGaAs) 116 is only connected to the upper surface of the retaining layer (InGaAsP) 114, and as... Figure 11 As shown, with the semiconductor thin film 135 slightly tilted, a portion of the upper surface of the lower barrier layer (InGaAs) 113 is coupled within a range where the force is weaker than that of covalent bonds and the contact area is sufficiently small. Therefore, it can be easily peeled off when the semiconductor thin film 135 is separated. In addition, the lower surface of the retention layer (InGaAsP) 114 is covalently coupled to the lower barrier layer (InGaAs) 113.
[0092] Figure 14 Figures (A) to (C) illustrate the process by which the upper barrier layer (InGaAs) 116 of the semiconductor thin film 135, which is peeled off by the imprint head 140, is removed by etching. Figure 14 (A) represents the state before etching. Figure 14 (B) indicates the state where etching is in progress. Figure 14 (C) indicates the state after etching is complete.
[0093] like Figure 14 As shown in (B), the upper barrier layer (InGaAs) 116 of the semiconductor thin film 135 is etched and separated from the semiconductor thin film 135 in two directions (arrow directions).
[0094] As described above, the step width L1 of the stepped portion 116a on the upper surface of the upper barrier layer (InGaAs) 116 and the thickness L2 of the upper barrier layer 116 satisfy the aforementioned inequality (1). Therefore, during etching, the etching from below in the vertical direction is completed before reaching the cladding layer (n-InP) 117 in the horizontal direction. As a result, at least the portion of the upper barrier layer (InGaAs) 116 that is in contact with the lower surface of the cladding layer (n-InP) 117 is removed only by etching from below in the vertical direction, thus allowing for uniform removal of this portion. Therefore, it is possible to remove the upper barrier layer (InGaAs) 116 by etching while maintaining the flatness of the back surface (lower surface) of the cladding layer (n-InP) 117.
[0095] Figure 15 Figures (A) to (C) illustrate the process of attaching a semiconductor thin film 135 with the upper barrier layer (InGaAs) 116 removed to a transfer substrate 141 to form electrodes at specified locations. Figure 15 (A) is a diagram showing the state in which the semiconductor thin film 135 is transferred onto the transfer substrate 141. Figure 15 (B) is a diagram showing the state after the protective film 121 has been removed. Figure 15 (C) is a diagram showing the state in which the first electrode 142 and the second electrode 143 are formed at each specified location.
[0096] like Figure 15 As shown in (A), the semiconductor thin film 135 after the upper barrier layer (InGaAs) 116 is etched is adhered to the transfer substrate 141, which is a Si substrate different from the growth substrate (InP) 111, by intermolecular forces. Next, as... Figure 15 As shown in (B), the imprint head 140 and the protective film 121 are removed, and a functional layer 133 consisting of an cladding layer (n-InP) 117, a light absorption layer (i-InGaAs (118), an cladding layer (p-InP) 119, and a contact layer (p-InGaAs (120)) is formed on the transfer substrate (Si) 141.
[0097] Then, as Figure 15 As shown in (C), a first electrode 142 is formed on the contact layer (p-InGaAs (120)) of the functional layer 133, and a second electrode 143 is formed on the cladding layer (n-InP) 117. Thus, a semiconductor device having a transfer substrate 141, a functional layer 133, a first electrode 142 and a second electrode 143 is formed.
[0098] The semiconductor devices mentioned here are, for example, photodiodes or LEDs (light-emitting diodes). These semiconductor devices are used in, for example, image sensors, LED printheads, LED displays, etc.
[0099] Figure 16 It was processed into Figure 9 A top view of the stacked wafer 100 in its current state. Figure 19 This is a diagram illustrating the etching process of the sacrificial layer (InP) 115 and the retaining layer (InGaAsP) 114.
[0100] Figure 7 The etching of the sacrificial layer (InP) 115 and the retaining layer (InGaAsP) 114 as described in (A) to (D) is as follows Figure 5 As shown in (A), the process proceeds from all directions of each of the patterned square stacked bodies 130 toward its center.
[0101] At this point, the etch rate of the retaining layer (InGaAsP) 114 is smaller than that of the sacrificial layer (InP) 115, but the retaining layer (InGaAsP) 114 forms a wedge-shaped opening through top-down etching based on the etching of the sacrificial layer (InP) 115. Figure 19 Region 150). Thus, the etchant is maintained to penetrate inwards, and the sacrificial layer (InP) 115 is completely removed.
[0102] Therefore, as Figure 5 As shown in (A), each layer 130 is patterned into a square. Figure 5 In the etching of (A), such as Figure 16 As shown, the planar shape of the residual retaining layer (InGaAsP) 114 is also roughly square, becoming a shape close to a square pyramid or a truncated square pyramid.
[0103] Figure 17 This is a diagram used to illustrate the etch process in another example. Figure 18 This is a diagram used to illustrate the etching process in yet another example.
[0104] like Figure 17 As shown, when the planar shape of each stack 130 is made into a circular shape, and the sacrificial layer (InP) 115 and the retaining layer (InGaAsP) 114 are etched from all directions, the retaining layer (InGaAsP) 114 remaining in the center becomes a shape similar to a cone or a frustum of a cone.
[0105] In addition, such as Figure 18 As shown, each of the stacked bodies 130 (patterned in a planar shape to form a square) Figure 5In (A), on the two opposite sides of each stacked body 130 ( Figure 18 When the resist for maintaining the structure 122 is formed in the entire area of each of the left and right sides, the etching solution is prevented from penetrating from each side where the resist is formed.
[0106] In this case, only the two sides of the retaining structure 122 (resist) that were never formed ( Figure 18 The top and bottom edges are etched, so that the remaining retaining layer 114 is formed into a generally triangular prism shape extending in the same direction at the center at equal distances from the two edges.
[0107] As described above, according to the structure of the semiconductor laminate of this embodiment, even when the semiconductor layer is exposed to the etching solution, the back side of the semiconductor layer (the lower surface of the cladding layer (n-InP) 117) does not become rough, and the semiconductor layer can be well bonded to the transfer substrate. Furthermore, when removing the sacrificial layer (InP) 115, the underlying retaining layer (InGaAsP) 114 can remain as a tapered shape tapering towards the upper leading edge. Therefore, the sacrificial layer (InP) 115 can be completely removed to the center of the laminate 130, making the peeling of the semiconductor thin film 135 easier.
[0108] Furthermore, while maintaining the lower surface of the upper barrier layer (InGaAs) 116, which is the lowest layer of the semiconductor thin film 135, in a flat state with a roughness of, for example, less than 10 nm, the semiconductor thin film 135 can be stably maintained during the period before peeling by the residual cone-shaped retaining layer (InGaAsP) 114. Moreover, the upper barrier layer (InGaAs) 116 can be etched in the vertical direction after separation (peeling), so the lower surface of the cladding layer (n-InP) 117, which is attached to the transfer substrate 141 by intermolecular forces, can be kept flat.
[0109] Implementation method 2.
[0110] Figure 20 This is a schematic diagram illustrating the stacked structure of a stacked wafer 200 having the structure of the semiconductor stack of the present disclosure according to Embodiment 2.
[0111] exist Figure 20In the stacked wafer 200, the growth substrate 211, which serves as the substrate, is a substrate on which an epitaxial layer is grown, and is an InP layer. On this growth substrate (InP) 211, a buffer layer 212 as an InP layer, a lower barrier layer 213 as an InGaAs layer (the fourth layer), a retaining layer 214 as an InGaAsP layer (the first layer), and a sacrificial layer 215 as an InP layer (the second layer) are sequentially formed by epitaxial growth. The thickness of the retaining layer (InGaAsP) 214 is thicker than the thickness of the sacrificial layer (InP) 215, preferably more than twice as thick.
[0112] Furthermore, on the sacrificial layer (InP) 215, an upper barrier layer 216, which is the third InGaAs layer, a cladding layer 217, which is the n-InP layer, a light-absorbing layer 218, which is the i-InGaAs layer, a cladding layer 219, which is the p-InP layer, and a contact layer 220, which is the p-InGaAs layer, are sequentially formed by epitaxial growth.
[0113] Next, a method for manufacturing the semiconductor device of this embodiment, based on the preparation of the aforementioned stacked wafer 200, will be described. Furthermore, the stacked wafer 200 shown in each figure is configured such that its stacking direction is vertically upward.
[0114] Figure 21 (A)~(C) represent the meaning of "to". Figure 20 The stacked wafer 200 is patterned into a 4×4 defined area. Figure 21 (A) is its top view. Figure 21 (B) is a side view. Additionally, Figure 21 (C) is to Figure 21 (B) is a magnified partial view of a block (P5 surrounded by dashed lines).
[0115] like Figure 21 As shown in (A), in order to separate the interface between the cladding layer (n-InP) 217 and the upper barrier layer (InGaAs) 216 of the stacked wafer 200 into 16 (4×4) stacked bodies 230, etching is performed along the separation region, which is set to a lattice pattern, to form lattice-shaped grooves 230a. Therefore, the upper barrier layers (InGaAs) 216 of the separated regions at this time are as follows: Figure 21 As shown in (B), they remain in a continuous state.
[0116] Figure 22 (A)~(C) represent the meaning of "to". Figure 21 A diagram showing the further patterned state of the stacked wafer 200. Figure 22 (A) is its top view. Figure 22 (B) is a side view. Additionally, Figure 22 (C) is to Figure 22 (B) is a magnified partial view of the multiple blocks shown (P5, enclosed by dashed lines).
[0117] Figure 21 The stacked bodies 230 shown in (A) to (C) are further divided into four sections. That is, as shown in (A) to (C) Figure 22 As shown in (A), along the stack of layers 230 ( Figure 21 The interfaces between the cladding layer (n-InP) 217 and the upper barrier layer (InGaAs) 216, namely the cladding layer (n-InP) 217, the light-absorbing layer (i-InGaAs) 218, the cladding layer (p-InP) 219, and the contact layer (p-InGaAs) 220, are set as cross-shaped separation regions. These four layers are etched to form a cross-shaped groove 232a. Thus, a stack 230 ( Figure 21 The structure is further divided into four segmented stacks 232, and the upper barrier layers (InGaAs) 216 of each segmented region are as follows: Figure 22 As shown in (B), they remain in a continuous state.
[0118] Figure 23 Figures (A) to (C) represent the state in which a protective film 221 is formed in each segmented laminate 232. Figure 23 (A) is its top view. Figure 23 (B) is a side view. Additionally, Figure 23 (C) is to Figure 23 (B) is a magnified partial view of the multiple blocks shown (P5, enclosed by dashed lines).
[0119] like Figure 23 As shown in (A) to (C), the protective film 221 is formed to cover the upper surface of the four functional layers 233 (from the cladding layer (n-InP) 217 to the contact layer (p-InGaAs) 220) and the upper barrier layer (InGaAs) 216 of each segmented laminate 232 after etching. The protective film 221 is made of any of the following materials: Al2O3, SiN, SiO2, etc. This prevents the upper surface and sides of the four functional layers 233 (from the cladding layer (n-InP) 217 to the contact layer (p-InGaAs) 220) of each laminate 232 from being etched.
[0120] Figure 24 (A)~(C) represent in Figure 23 The diagram (A) shows a state in which the protective film 221 of the groove 230a (double-dotted line portion) and the groove 232a (single-dotted line portion) and a portion of the upper barrier layer (InGaAs) 216 are provided with elongated holes 234. Figure 24(A) is its top view. Figure 24 (B) is a side view. Additionally, Figure 24 (C) is to Figure 24 (B) is a magnified partial view of the multiple blocks shown (P5, enclosed by dashed lines).
[0121] like Figure 24 As shown in (A) to (C), in each groove 230a, 232a between each segmented stack 232, an elongated hole 234 is formed by etching along the groove 230a, 232a to reach the sacrificial layer (InP) 215.
[0122] Figure 25 Figures (A) to (D) are diagrams illustrating the etch progress of the sacrificial layer (InP) 215 and the retaining layer (InGaAsP) 214, for example showing... Figure 24 The area of P5 is enclosed by the dashed line of (B). Figure 25 (A) represents the state before etching. Figure 25 (B) and (C) represent the etching process. Figure 25 (D) indicates the state after etching is complete. In addition, for simplicity, the growth substrate 211, buffer layer 212 and functional layer 233 which is above the upper barrier layer 216 are not shown here.
[0123] Hydrochloric acid, a mixture of hydrochloric acid and phosphoric acid, or a mixture of hydrochloric acid and nitric acid are used as the etchant for this etching process. In this etching, the etch rate of the sacrificial layer (InP) 215 is faster and the difference is greater than that of the upper barrier layer (InGaAs) 216. Therefore, the upper barrier layer (InGaAs) 216 is hardly etched.
[0124] In addition, similar to the case of Embodiment 1, here, regarding the etching rate in each layer, the etching rate of the sacrificial layer (InP) 215 is greater than the etching rate of the retaining layer (InGaAsP) 214, and the etching rate of the sacrificial layer (InP) 215 is greater than the etching rate of the upper barrier layer (InGaAs) 216.
[0125] In this etchant, the etch rate of the sacrificial layer (InP) 215 is more than 1000 times that of the upper barrier layer (InGaAs) 216 (i.e., a selectivity of 1000 or more), and the etch rate of the sacrificial layer (InP) 215 is more than 2 times but less than 1000 times that of the retaining layer (InGaAsP) 214 (i.e., a selectivity of 2 or more but less than 1000). Here, the etch rate of the sacrificial layer (InP) 215 is set to be 2 to 4 times that of the retaining layer (InGaAsP) 214 (i.e., a selectivity of 2 to 4). Furthermore, the composition of the retaining layer (InGaAsP) 214 is In(x)Ga(1-x)As(y)P(1-y), where y = 0.4.
[0126] Furthermore, here, the lower barrier layer (InGaAs) 213 is also formed of the same material as the upper barrier layer (InGaAs) 216. Therefore, similarly, the etch rate of the sacrificial layer (InP) 215 is more than 1000 times that of the lower barrier layer (InGaAs) 213. As a result, it is hardly etched during the etching of the upper retaining layer (InGaAsP) 214. In addition, this protects the buffer layer (InP) 212 and the growth substrate (InP) 211, which are located below the lower barrier layer (InGaAs) 213, from being etched.
[0127] That is, when a predetermined etchant is used, the etch selectivity of the sacrificial layer (InP) 215 relative to the upper barrier layer (InGaAs) 216 is greater than the etch selectivity of the sacrificial layer (InP) 215 relative to the retaining layer (InGaAsP) 214. Furthermore, the etch selectivity of the sacrificial layer (InP) 215 relative to the lower barrier layer (InGaAs) 213 is greater than the etch selectivity of the sacrificial layer (InP) 215 relative to the retaining layer (InGaAsP) 214.
[0128] Here, as Figure 24 As described in (A) to (C), elongated holes 234 are formed along the lattice-shaped grooves 230a and 232a, respectively, so that etching is performed from the periphery of each segmented laminate 232 toward its center.
[0129] That is, such as Figure 25As shown in (B) and (C), as the sacrificial layer (InP) 215 is etched, the retaining layer (InGaAsP) 214 is also etched. However, since the sacrificial layer (InP) 215 is etched first, it is etched from its upper surface. However, since the lower barrier layer (InGaAs) 213 is not etched, the retaining layer (InGaAsP) 214 is not etched from its lower surface. As a result, the retaining layer (InGaAsP) 214 is etched in a tapered shape at its two ends.
[0130] When finally removing the sacrificial layer (InP) 215, as Figure 25 As shown in (D), the center of the upper barrier layer (InGaAs) 216 of each segmented stack 232 is supported by a retaining layer (InGaAsP) 214 that remains in the shape of a square pyramid or a frustum of a square pyramid.
[0131] Therefore, in the process of removing the sacrificial layer (InP) 215 by etching, the area of the upper surface of the retaining layer (InGaAsP) 214 that is in contact with the upper barrier layer (InGaAs) 216 is made smaller than the area of the lower surface that is in contact with the lower barrier layer (InGaAs) 213 by etching.
[0132] Figure 26 It is Figure 25 The enlarged partial view of (C) showing the etching process as a cone-shaped retaining layer (InGaAsP) 214 near the end (the portion P6 surrounded by the dashed line).
[0133] about Figure 26 The thickness L7 of the retaining layer (InGaAsP) 214 shown is the ratio of the depth L6 of the tapered portion of the etched end of the retaining layer (InGaAsP) 214 to the angle θ2 at the front end, which is tan(θ2).
[0134] 0 <x<1 (4)
[0135] 0 <y<1 (5)
[0136] The concentrations (composition ratios) of In(x)Ga(1-x)As(y)P(1-y) in the holding layer (InGaAsP) 114 are adjusted within a certain range to increase the concentration of In and P, thereby increasing the ratio. Specifically, (to increase the concentration of In) it is preferable that 0.7 ≤ x, and (to increase the concentration of P) it is preferable that y ≤ 0.5. If it is within this range (x is above 0.7, y is below 0.5), then θ2 of the holding layer (InGaAsP) 214 is greater than 0, that is, the holding layer 214 becomes triangular in shape, and therefore, the semiconductor thin film 235 (described later) can be peelably held with a smaller area (vertical portion). However, in this embodiment, the composition ratio of In and P in the holding layer (InGaAsP) 214 can be infinitely close to 0, and the angle θ2 can be infinitely close to 0.
[0137] In addition, the angle θ2 can be reduced by increasing the thickness of the sacrificial layer (InP) 215, but when the thickness of the retaining layer (InGaAsP) 214 is less than twice the thickness of the sacrificial layer (InP) 215, it may be impossible to retain the required height of the retaining layer (InGaAsP) 214.
[0138] Figure 27 (A)~(C) represent the formation of Figure 24 The diagram shows a state in which the sacrificial layer (InP) 215 is removed by etching in the stacked wafer 200 with elongated aperture 234, and the retaining layer (InGaAsP) 214 is also removed except for the center portion. This is equivalent to... Figure 25 The (D) stage. Figure 27 (A) is its top view. Figure 27 (B) is a side view. Additionally, Figure 27 (C) is to Figure 27 (B) is a magnified partial view of the multiple blocks shown (P5, enclosed by dashed lines). Figure 28 Is with Figure 27 The top view corresponding to (C).
[0139] When the sacrificial layer (InP) 215 is completely removed by etching, as Figure 27 (A)~(C) and Figure 28 As shown, the lower surface of the upper barrier layer (InGaAs) 216 is held in a state where the upper surface of the retaining layer (InGaAsP) 214, which is left in the shape of a square pyramid or frustum of a square pyramid, corresponds to each segmented stack 232. Here, the stacked structure from the upper barrier layer (InGaAs) 216 to the protective film 221 is sometimes referred to as the semiconductor thin film 235.
[0140] At this point, the lower surface of the upper barrier layer (InGaAs) 216 and the upper surfaces of the retaining layer (InGaAsP) 214 that abut against it are coupled with a contact area that is weaker than a covalent bond. Therefore, it can be easily peeled off during the separation of the semiconductor thin film 235, which will be described later. In addition, the lower surface of the retaining layer (InGaAsP) 214 is covalently coupled to the lower barrier layer (InGaAs) 213.
[0141] Here, the etching of the sacrificial layer (InP) 215 and the retaining layer (InGaAsP) 214 proceeds from all directions toward the center of each of the square-shaped segmented laminates 232. At this time, the etching rate of the retaining layer (InGaAsP) 214 is slower than that of the sacrificial layer (InP) 215, but the retaining layer (InGaAsP) 214 forms a wedge-shaped opening (equivalent to...) through top-down etching based on the etching of the sacrificial layer (InP) 215. Figure 19 Region 150). Thus, the etchant is maintained to penetrate inwards, and the sacrificial layer (InP) 215 is completely removed.
[0142] In this embodiment, at this stage, as described above, the upper barrier layer (InGaAs) 216 is etched continuously without being divided according to each segmented stack 232 (except for the elongated via 234). Therefore, the retaining structure 122 required in Embodiment 1 is not necessary.
[0143] Figure 29 It means in Figure 27 (C) shows a diagram of the semiconductor thin film 235 with the imprint head 240 attached thereon. Figure 30 This diagram shows the state in which the semiconductor thin film 235 is peeled off from the retaining layer (InGaAsP) 214 by the imprint head 240. Figure 31 This diagram shows the state after etching the upper barrier layer (InGaAs) 216.
[0144] In order to peel and move the semiconductor thin film 235 from the holding layer (InGaAsP) 214, as Figure 29 As shown, an imprint head 240 is attached to the upper surface of the protective film 221 of the semiconductor thin film 235, such as... Figure 30 As shown, the semiconductor thin film 235 is peeled off from the retaining layer (InGaAsP) 214 by the imprint head 240.
[0145] At this point, the upper barrier layer (InGaAs) 216 is coupled to the upper surface of the retaining layer (InGaAsP) 214 with a force weaker than covalent bonds and a sufficiently small contact area, thus allowing for easy peeling during the separation of the semiconductor thin film 235. Furthermore, the lower surface of the retaining layer (InGaAsP) 214 is covalently coupled to the lower barrier layer (InGaAs) 213.
[0146] Figure 31 It indicates from Figure 30 The diagram shows the state in which the semiconductor thin film 235 held by the imprint head 240 has its upper barrier layer (InGaAs) 216 removed.
[0147] After separation, such as Figure 31 As shown, the upper barrier layer (InGaAs) 216 of the semiconductor thin film 235 is completely removed by etching; however, as referred to in Embodiment 1... Figure 14 As explained in (A) to (C), during etching, the etching is completed from the lower side in the vertical direction before reaching the cladding layer (n-InP) 117 in the horizontal direction. As a result, at least the portion of the upper barrier layer (InGaAs) 216 that is in contact with the lower surface of the cladding layer (n-InP) 217 is removed only by etching from the lower side in the vertical direction, thus enabling uniform removal in that portion.
[0148] Figure 32 This diagram shows the state in which the semiconductor thin film 235, with the upper barrier layer (InGaAs) 216 removed, is adhered to the transfer substrate 241. Figure 33 This diagram shows the state of the first electrode 242 and the second electrode 243 after the protective film 221 is removed.
[0149] like Figure 32 As shown, the semiconductor thin film 235, after the upper barrier layer (InGaAs) 216 is etched, is adhered to the transfer substrate 241, which is a Si substrate different from the growth substrate (InP) 211, by intermolecular forces. Next, as... Figure 33 As shown, the imprint head 240 and protective film 221 are removed, and a stacked body 232 is formed on the transfer substrate (Si) 241 according to each segment (see reference). Figure 22 The functional layers 233 after electrical separation of (A) to (C) are semiconductor layers. Each functional layer 233 has a cladding layer (n-InP) 217, a light absorption layer (i-InGaAs) 218, a cladding layer (p-InP) 219, and a contact layer (p-InGaAs) 220.
[0150] Then, as Figure 33As shown, a first electrode 242 is formed on the contact layer (p-InGaAs) 220 of the functional layer 233, and a second electrode 243 is formed in connection with the cladding layer (n-InP) 217. Thus, a semiconductor device having a transfer substrate 241, a functional layer 233, a first electrode 242, and a second electrode 243 is formed.
[0151] The semiconductor devices mentioned here are, for example, photodiodes or LEDs. These semiconductor devices are used in, for example, image sensors, LED printheads, LED displays, etc.
[0152] As described above, according to the structure of the semiconductor stack of this embodiment, when removing the sacrificial layer (InP) 215, the underlying retaining layer (InGaAsP) 214 can remain as a tapered shape that tapers towards the upper front end. Therefore, the sacrificial layer (InP) 215 can be completely removed to the center of each segmented stack 232, making the peeling of the semiconductor thin film 235 easier.
[0153] Furthermore, while maintaining the lower surface of the upper barrier layer (InGaAs) 216, which is the lowest layer of the semiconductor thin film 235, in a flat state with a roughness of, for example, less than 10 nm, the semiconductor thin film 235 can be stably maintained during the period before peeling by the residual cone-shaped retaining layer (InGaAsP) 214. Moreover, the upper barrier layer (InGaAs) 216 can be etched in the vertical direction after peeling, so the lower surface of the cladding layer (n-InP) 217, which is attached to the transfer substrate 241 by intermolecular forces, can be kept flat.
[0154] Furthermore, in this embodiment, the upper barrier layer (InGaAs) 216 is continuously formed without being divided (except for the elongated hole 234) by multiple retaining layers (InGaAsP) 214. Therefore, when removing the sacrificial layer (InP) 215, it is not necessary to form a resist (equivalent to the retaining structure 122 in embodiment 1).
[0155] In addition, the terms "upper," "lower," "left," and "right" are used in the claims and description of the embodiments, but these are for convenience and do not limit the absolute positional relationship of the semiconductor stack.
[0156] Label Explanation
[0157] 100: Stacked wafer; 111: Growth substrate (substrate); 112: Buffer layer; 113: Lower barrier layer (fourth layer); 114: Holding layer (first layer); 115: Sacrificial layer (second layer); 116: Upper barrier layer (third layer); 116a: Stepped section; 117: Clad layer; 118: Light-absorbing layer; 119: Clad layer; 120: Contact layer; 121: Protective film; 122: Holding structure; 130: Stacked body; 131a: Groove section; 131b: Groove section; 133: Functional layer (semiconductor layer); 135: Semiconductor thin film; 140: Imprint head; 141: Transfer substrate; 142: First electrode; 143: Second electrode; 15 0: Region; 200: Stacked wafer; 211: Growth substrate (substrate); 212: Buffer layer; 213: Lower barrier layer (fourth layer); 214: Holding layer (first layer); 215: Sacrificial layer (second layer); 216: Upper barrier layer (third layer); 217: Covering layer; 218: Light absorption layer; 219: Covering layer; 220: Contact layer; 221: Protective film; 230: Stack; 230a: Groove; 232: Segmented stack; 232a: Groove; 233: Functional layer (semiconductor layer); 234: Elongated hole; 235: Semiconductor thin film; 240: Imprint head; 241: Transfer substrate; 242: First electrode; 243: Second electrode.
Claims
1. A semiconductor laminate, characterized in that, The semiconductor stack has: Substrate; The first layer is stacked on top of the substrate; The second layer is stacked on top of the first layer; The third layer is stacked on top of the second layer; as well as A semiconductor layer, stacked on the third layer, wherein at least the layer in contact with the third layer is made of the same material as the second layer. When the specified etchant is used, the etch selectivity of the second layer relative to the third layer is greater than that of the second layer relative to the first layer.
2. The semiconductor laminate according to claim 1, characterized in that, The semiconductor stack also has a fourth layer, which is stacked on top of the substrate and is made of the same material as the third layer. The first layer is stacked on top of the fourth layer.
3. The semiconductor laminate according to claim 2, characterized in that, The substrate, the semiconductor layer in contact with the third layer, and the second layer are all made of indium phosphide. The first layer is composed of indium gallium arsenide phosphide. The third and fourth layers are composed of indium gallium arsenide.
4. The semiconductor laminate according to any one of claims 1 to 3, characterized in that, The first layer is thicker than the second layer.
5. The semiconductor laminate according to any one of claims 1 to 4, characterized in that, The semiconductor layer is formed smaller than the third layer in a first direction parallel to the upper surface of the substrate. The thickness of the third layer in a second direction perpendicular to the upper surface of the substrate is smaller than the length of the portion of the third layer protruding from the outer periphery of the semiconductor layer in the first direction.
6. The semiconductor laminate according to any one of claims 1 to 5, characterized in that, The semiconductor stack also has a protective film formed in a manner that covers the surface of the semiconductor layer that is in contact with the third layer.
7. A method for manufacturing a semiconductor device, the method comprising: The second layer of the semiconductor laminate is removed using a specified etchant. The semiconductor stack has a first layer stacked above a substrate, a second layer stacked on the first layer, a third layer stacked on the second layer, and a semiconductor layer stacked on and at least in contact with the third layer, which is made of the same material as the second layer. Separate the semiconductor layer and the third layer from the substrate; Remove the third layer; as well as The semiconductor layer is transferred to a transfer substrate that is different from the substrate.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, When removing the second layer, the second surface of the third layer side of the first layer is made smaller than the first surface of the substrate side of the first layer and parallel to the upper surface of the substrate, and the third layer is bonded to the second surface.
9. The method for manufacturing a semiconductor device according to claim 7 or 8, characterized in that, Before removing the second layer, a protective film is formed in a manner that covers the surface of the semiconductor layer that is in contact with the third layer.