Silicon carbide-based semiconductor structure for power applications and related manufacturing method

Abstract

This invention relates to a silicon carbide-based semiconductor structure, comprising: - an active layer made of single-crystal silicon carbide having a first dopant concentration uniform across its thickness; - a carrier substrate made of polycrystalline silicon carbide having a second dopant concentration uniform across its thickness and a resistivity less than or equal to 10 molhm·cm, the second concentration being related to the first concentration by the following relationship: C2 > N2 x exp(-C1 / N1), where C1 is the first concentration, C2 is the second concentration, and N1 = 2.85.10 18 cm ‑3 N² = 5.40.10 20 cm ‑3 The interface region between the carrier substrate and the working layer includes nodules and direct contact areas between the working layer and the carrier substrate. The nodules contain metal or semiconductor materials other than silicon carbide. The interface region has a width of less than or equal to 0.01 mol / cm². 2 The average resistivity, along the thickness of the semiconductor structure, exhibits a dopant concentration distribution that: - is stepped, and - has no doping peaks in the interface region, or - exhibits doping peaks in the interface region, the extreme values ​​of which correspond to a third dopant concentration equal to the second dopant concentration, with a deviation within ±10%. The invention also relates to a method for manufacturing such a semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of microelectronics, and more particularly to the field of power electronics. Specifically, this invention relates to a structure comprising a semiconductor layer made of high-quality single-crystal silicon carbide and a carrier substrate made of polycrystalline silicon carbide, the semiconductor layer and the carrier substrate being assembled at a conductive interface region. This invention also relates to a method for manufacturing such a structure. Background Technology

[0002] Semiconductor structures are typically formed by transferring a thin-film transfer layer with high crystallinity onto a semiconductor carrier substrate with lower crystallinity. A well-known thin-film transfer method is Smart Cut. ™ The process is based on the following operations: implanting light ions into a donor substrate and performing direct bonding assembly at the bonding interface between the donor and carrier substrates; separating along a buried vulnerable plane defined by the implantation, thereby transferring the working layer from the donor substrate to the carrier substrate. In addition to the economic advantages associated with the streamlining of the high-quality material of the working layer, the semiconductor structure also provides advantageous properties, such as those related to the thermal conductivity, electrical conductivity, or mechanical compatibility of the carrier substrate.

[0003] For example, in the field of power electronics, it is advantageous to establish electrical conduction between the active layer and the carrier substrate to form vertical components. For instance, in structures comprising an active layer made of single-crystal silicon carbide (SiC) and a carrier substrate made of low-quality silicon carbide (SiC) (single-crystal or polycrystalline), the bonding interface must have the lowest possible resistivity, less than 0.1 mol / cm². 2 Or even more preferably less than 0.01 mohm.cm 2 .

[0004] Some existing solutions propose achieving direct semiconductor-on-semiconductor bonding between the working layer and the carrier substrate to establish vertical electrical conduction. However, achieving good interface quality using this type of bonding is difficult.

[0005] F. Mu et al. (ECS Transactions, 86(5) 3-21, 2018) achieved direct bonding (SAB, "surface-activated bonding") after activating the surface to be assembled by argon bombardment: this treatment prior to bonding generates a very high density of dangling bonds, which promotes the formation of covalent bonds at the assembly interface and thus generates high bonding energy. However, this method has the disadvantage of generating an amorphous layer at the assembly surface, which adversely affects the vertical electrical conduction between the thin layer and the carrier substrate. To overcome this problem, a method of heavy doping of the surface by shallow implantation was specifically proposed in EP3168862. In addition to the fact that the shallow implantation dose cannot be increased indefinitely, the high introduction of dopant atoms tends to damage the crystal quality of the working layer and / or reduce the binding energy of the structure.

[0006] Other solutions in the prior art propose using conductive bonding with different types of layers deposited on the surface to be assembled in order to avoid large-scale dopant injection before assembly.

[0007] Reference WO2022 / 008809 proposes forming the interface region in a SiC / SiC semiconductor structure using a very thin layer of metal material (such as tungsten). Considering the working layer and carrier substrate made of single-crystal SiC with a resistivity of 20 molhm·cm, and the 1 nm to 3 nm tungsten layer (W) sandwiched between the working layer and the carrier substrate, after applying appropriate heat treatment and forming very fine junctions mainly composed of metal (W), a resistivity of less than or equal to 0.1 molhm·cm can be achieved. 2 The resistivity of the interface region enables good vertical conduction in the interface region.

[0008] Document WO2022 / 129726 proposes forming an interface region in a SiC / SiC semiconductor structure. This interface region includes a direct contact region between the active layer and the carrier substrate, and an aggregate comprising a semiconductor material different from both the active layer and the carrier substrate, and having a thickness of less than or equal to 250 nm. The semiconductor material is chosen due to its specific affinity for oxygen. Therefore, the aggregate can effectively trap oxygen that may be present at the bonding interface; the direct contact region between the active layer and the carrier substrate (specifically, without native oxide residue) allows for efficient and high-quality electrical conduction and / or vertical semiconductor / semiconductor contacts. Considering the active layer with a resistivity of 20 molhm·cm, the carrier substrate with a resistivity of 20 molhm·cm, and the silicon semiconductor material, a thickness of less than or equal to 0.1 molhm·cm can be obtained. 2 The resistivity of the interface region, for example, 0.032 mohm·cm. 2 (After annealing the structure at 1370℃) or 0.0076 mohm.cm 2(After annealing at a very high temperature (i.e., 1900°C)).

[0009] Purpose of the invention

[0010] This invention provides a solution that satisfies the requirement of very low resistivity (less than or equal to 0.01 mol / cm²) in the interface region of a silicon carbide-based semiconductor structure. 2 This invention addresses the need for semiconductor structures and simplifies their fabrication. The present invention relates to a semiconductor structure and a method for manufacturing such a structure. Summary of the Invention

[0011] This invention relates to a silicon carbide-based semiconductor structure, the semiconductor structure comprising: - A working layer made of single-crystal silicon carbide, having a uniform first dopant concentration across its thickness. - A carrier substrate made of polycrystalline silicon carbide, the carrier substrate having a second dopant concentration uniformly distributed over its thickness, the second concentration being related to the first concentration by the following relationship: C2>N2 x exp(-C1 / N1), where C1 is the first concentration, C2 is the second concentration, and N1 = 2.85.10. 18 cm -3 And N2 = 5.40.10 20 cm -3 , - An interface region located between the carrier substrate and the working layer, comprising nodules and direct contact areas between the working layer and the carrier substrate, wherein the nodules comprise a metal or semiconductor material other than silicon carbide, and the interface region has a size less than or equal to 0.01 mol / cm². 2 The average resistivity.

[0012] Dopant concentration distribution along the thickness of the semiconductor structure: - It takes the form of steps, and - There are no doped peaks in this interface region, or - A doping peak is exhibited in this interface region. The extreme value of the doping peak corresponds to the concentration of the third dopant, which is equal to the concentration of the second dopant, with a deviation within ±10%.

[0013] Advantageous features according to the invention (alone or in any feasible combination): The resistivity of the carrier substrate is less than or equal to 10 mohm.cm, 5 mohm.cm, or even 3 mohm.cm or even 2 mohm.cm; The interface region has a thickness of less than or equal to 200 nm; The metallic material of the nodule is selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper, or the semiconductor material of the nodule is selected from silicon, germanium, carbon, III-V compounds such as gallium nitride, or other compounds formed from these materials.

[0014] The present invention also relates to a method for manufacturing a silicon carbide-based semiconductor structure, the method comprising the following steps: a) Provide a working layer made of single-crystal silicon carbide, the working layer having free surfaces to be assembled and a first dopant concentration uniform across its thickness. b) Provide a carrier substrate made of polycrystalline silicon carbide, the carrier substrate having a free surface to be assembled and a second dopant concentration uniform across its thickness, the second concentration being related to the first concentration by the following relationship: C2>N2 x exp(-C1 / N1), where C1 is the first concentration, C2 is the second concentration, and N1 = 2.85.10. 18 cm -3 And N2 = 5.40.10 20 cm -3 , c) Deposit a film of a metal or semiconductor material other than silicon carbide with a thickness of less than or equal to 20 nm on the free surface to be assembled on the working layer and / or on the free surface to be assembled on the carrier substrate. d) Forming an intermediate structure comprising free surfaces to be assembled, respectively directly assembling the working layer and the carrier substrate, the intermediate structure comprising an encapsulated film derived from one or more films deposited during step c). e) Anneal the intermediate structure at a temperature between 1200°C and 2000°C to form the semiconductor structure including an interface region comprising a direct contact area between the thin layer and the carrier substrate and nodules formed by the segmentation of the encapsulated film.

[0015] This interface area has a value less than or equal to 0.01 mohm.cm. 2 The average resistivity; the dopant concentration distribution along a thickness of the semiconductor structure is in the form of steps, and there is no doping peak in the interface region or a doping peak is exhibited in the interface region, the extreme value of which corresponds to the third dopant concentration, which is equal to the second dopant concentration, with a deviation within ±10%.

[0016] Advantageous features according to the invention (alone or in any feasible combination): Step a) includes implanting a light material into a donor substrate of single-crystal silicon carbide to form a buried vulnerable plane, which together with the front side of the donor substrate defines the working layer. Step d) includes, after generating a direct assembly of the bonding assembly including the donor substrate and the carrier substrate, separating at the buried vulnerable plane to form, on the one hand, the intermediate structure including the working layer, the encapsulated film and the carrier substrate, and on the other hand, the remaining portion of the donor substrate. Prior to step c), the free surface of the film to be assembled has a single-crystal surface that has no regions that are activated by doping or bombardment but are not crystallized or damaged, and the free surface of the carrier substrate to be assembled has a polycrystalline surface that has no regions that are activated by doping or bombardment but are not crystallized or modified. The method includes the step of epitaxially growing an additional layer of single-crystal silicon carbide on the working layer of the semiconductor structure. Attached Figure Description

[0017] Other features and advantages of the invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings, in which: [ Figure 1 ] Figure 1 A semiconductor structure according to the present invention is shown; [ Figure 2a ] [ Figure 2b ] [ Figure 2c ] [ Figure 2d ] [ Figure 2e ] Figures 2a to 2e The steps of the manufacturing method according to the present invention are shown; [ Figure 3a ] [ Figure 3b ] [ Figure 3c ] [ Figure 3d ] Figures 3a to 3d The steps of the manufacturing method according to the present invention are shown; [ Figure 4 ] Figure 4 The dopant concentration distribution (A) of the semiconductor structure according to the invention along the thickness is shown in comparison with other dopant concentration distributions (B, C, D) of prior art structures. [ Figure 5 ] Figure 5A curve showing the relationship between the second concentration C2 and the first concentration C1 is shown to obtain a value less than or equal to 0.01 molhm.cm. 2 The average resistivity of the interface region (represented as ρ in the figure) int The first concentration C1 and the second concentration C2 are the dopant concentrations of the working layer made of single-crystal silicon carbide and the dopant concentrations of the carrier substrate in the semiconductor structure according to the present invention, respectively.

[0018] Some of the accompanying figures are schematic diagrams and are not drawn to scale for clarity. Specifically, the thickness of the layer along the z-axis is not proportional to the lateral dimensions along the x- and y-axis. The same reference numerals in the figures can be used for the same type of element. Detailed Implementation

[0019] This invention relates to a semiconductor structure 100, which includes a working layer 10 made of single-crystal silicon carbide (typically polytype 4H), a carrier substrate 30 made of polycrystalline silicon carbide (typically polytype 3C), and an interface region 20 located between the working layer 10 and the carrier substrate 30. Figure 1 Like working layer 10, interface area 20 extends parallel to the main plane (x,y).

[0020] Advantageously, and as is common in the field of microelectronics, the semiconductor structure 100 is in the form of a circular wafer with a diameter between 100 mm and 450 mm. It should be understood that, in this case, the carrier substrate 30 and the working layer 10 also have this circular shape. The front side 100a and the back side 100b (circular) of the wafer extend parallel to the main plane (x,y).

[0021] The semiconductor structure 100 has a total thickness typically between 300 micrometers and 1000 micrometers. The thickness of the carrier substrate 30 forms the majority of this total thickness, wherein the working layer 10 typically has a thickness of less than a few micrometers or even less than 1 μm.

[0022] According to the present invention, the carrier substrate 30 has a uniform dopant concentration (hereinafter referred to as the second concentration C2) over its thickness. Uniformity means a constant dopant concentration over the thickness within + / - 10%. For N-type doping, nitrogen, phosphorus, or arsenic atoms will be present in the polycrystalline matrix of the carrier substrate 30, while for P-type doping, boron or aluminum atoms will be present.

[0023] Advantageously, the resistivity of the carrier substrate 30 is less than or equal to 10 mol / cm (i.e., the dopant concentration is typically greater than or equal to 1.10). 20 cm -3 ), 5 mohm.cm (i.e., the dopant concentration is typically greater than or equal to 2.10). 20 cm -3), or even 3 mohm.cm, or even 2 mohm.cm (i.e., dopant concentration greater than or equal to 4.10). 20 cm -3 ).

[0024] The working layer 10 also has a uniform dopant concentration (referred to as the first concentration C1) across its thickness (within + / - 10%). The doping type of the working layer 10 is typically the same as that of the carrier substrate 30.

[0025] Furthermore, the second concentration C2 is related to the first concentration C1 by the following relationship: C2 > N2 x exp(-C1 / N1), where N1 = 2.85.10 18 cm -3 And N2 = 5.40.10 20 cm -3 ,like[ Figure 5 As shown in the figure. It should be noted that this curve is defined for the N-type doped single-crystal 4H-SiC working layer 10 and the N-type doped polycrystalline 3C-SiC carrier substrate 30.

[0026] Therefore, according to the present invention, the range of the first concentration C1 and the second concentration C2 is located within... Figure 5 The curve reflects the average resistivity ρ of the interface region 20. int Equal to 0.01 mohm.cm 2 And it is less than this value when moving above the curve.

[0027] Therefore, in the semiconductor structure 100 according to the invention, a wide range of resistivity can be used for the working layer 10: for example, a resistivity between a few ohms and 10 mohm·cm can be used (i.e., the first concentration C1 of the dopant is typically 1.10). 17 cm -3 The magnitude is similar to 1.10 19 cm -3 Between orders of magnitude). By limiting the range (in ρ) int (Above the curve) Selecting a second concentration of C2 for the carrier substrate 30 will achieve excellent electrical conduction between the working layer 10 and the carrier substrate 30 via the interface region 20.

[0028] Interface region 20 includes a nodule 21 and a direct contact region 22 located between working layer 10 and carrier substrate 30. Nodule 21 is made of a metal or semiconductor material other than silicon carbide. The metal material of nodule 21 may be selected from, but is not limited to, tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper; the semiconductor material of nodule 21 may be selected from, but is not limited to, silicon, germanium, carbon, III-V compounds such as gallium nitride, or other compounds formed from these materials (SiGe, SiGeC, etc.).

[0029] Interface region 20 has a thickness typically less than or equal to 200 nm or even less than or equal to 100 nm along the z-axis orthogonal to the principal plane (x, y). Specifically, its maximum thickness is defined by the maximum thickness of the nodules 21. The nodules 21 distributed on interface region 20 are either unconnected or adjacent to each other; most of the unconnected nodules are separated from each other by direct contact region 22, in which the working layer 10 is in direct contact with the carrier substrate 30, in other words, there is a direct bond between the single-crystal silicon carbide of the working layer 10 and the polycrystalline silicon carbide of the carrier substrate 30.

[0030] On the central plane P of the interface area 20, the coverage of the direct contact area 22 is typically between 30% and 80%.

[0031] In some cases of the semiconductor structure 100, nanometer-thick cavities may optionally exist in these direct contact regions 22, but the cavities typically occupy less than 10% or even less than 5% of the surface area along the principal (x,y) plane occupied by the direct contact regions 22. Their thickness is also less than the thickness of the nodules 21.

[0032] According to the present invention, the interface region 20 has a size of less than or equal to 0.01 mohm·cm. 2 The resistivity of the interface region is discussed in this paper due to the very low thickness of the interface region 20. 2 The resistivity is expressed in units of "surface" resistivity. Average resistivity refers to the resistivity of interface region 20 as a whole, including its individual regions: direct contact region 22, nodules 21, and cavities (if present). In practice, the resistivity of interface region 20 is obtained from measurements of I(V) (current as a function of voltage) taken at the two electrodes formed on structure 100, through which a current path flows between the two electrodes across interface region 20 due to the trench 40 between the electrodes. Naturally, the resistivity contributions of other layers and interfaces involved in the current path are taken into account.

[0033] like[ Figure 4 As shown, the dopant concentration distribution A along the thickness of the semiconductor structure 100 forms a stepped pattern between the working layer 10 and the carrier substrate 30. In other words, starting from the free surface of the working layer 10, passing through the interface region 20 and penetrating the carrier substrate 30 to a depth greater than 1 μm (parallel to the z-axis), the dopant concentration distribution defines a clear step between the thinner layer 10, which is less doped than the carrier substrate 30, and the carrier substrate, which has a higher doping level (particularly, in...). Figure 4 In the example, the first concentration C1 is approximately 5.10. 18 cm -3 And for the second concentration, C2 is approximately 5.10. 20cm -3 No dopant diffusion distribution is used to increase or change the uniform doping level of the thin film 10 near the interface region 20.

[0034] Furthermore, the interface region 20 has an average doping level that is the same as or very close to the average doping level of the carrier substrate 30. The interface region 20 has no doping peaks associated with the exogenous introduction (e.g., by implantation) of dopant on one side of the working layer 10 or the carrier substrate 30; the interface region 20 has the same dopant concentration within ±10% of the second concentration.

[0035] Optionally, the interface region 20 may exhibit a doping peak, but the extreme value of the doping peak corresponds to a dopant concentration slightly greater than or less than the second concentration (the so-called third concentration): the third dopant concentration is equal to the second dopant concentration C2, with a deviation within ±10%. Therefore, this doping peak is also much lower than the peak associated with the exogenous introduction of the dopant, as can be obtained from structures in the prior art. Figure 4 The distributions seen in B, C, and D in the diagram.

[0036] The semiconductor structure 100 thus ensures good conductivity between the working layer 10 and the carrier substrate 30 via its interface region 20. Specifically, the direct contact region 22 benefits from a high concentration of dopant, similar to that of the carrier substrate 30, due to the diffusion and trapping of dopant from the carrier substrate 30 at the interface between the working layer 10 and the carrier substrate 30. The nodule 21 can also participate in vertical electrical conduction; the presence of a large amount of dopant at the interface between the nodule 21 and the highly doped carrier substrate 30 contributes to this conduction.

[0037] Resistivity less than or equal to 0.01 molhm·cm 2 The interface region 20 can be considered "transparent" in the semiconductor structure 100, thus not providing a parasitic increase in resistance in vertical electrical conduction.

[0038] In addition to its excellent electrical conductivity, the interface region 20 ensures physical continuity between the working layer 10 and the carrier substrate 30 and provides excellent mechanical strength to the semiconductor structure 100. Therefore, the quality of the working layer 10 is not affected by any holes or interface defects; it should be noted that the aforementioned cavities (when present) have dimensions and density that do not adversely affect the quality and mechanical resistance of the working layer 10.

[0039] Power devices can be fabricated on and / or in the active layer 10 of the semiconductor structure 100 according to the invention. It is not necessary to thin the carrier substrate 30 to a thickness of less than 200 μm or even less than 150 μm because the high doping of the carrier substrate 30 ensures excellent vertical conductivity. Typically, the active layer 10 needs to be thickened, for example, by epitaxial formation of additional layers, to fabricate power devices.

[0040] These components may specifically include at least one electrical contact in and / or on the carrier substrate 30 in a region of the back side 100b of the semiconductor structure 100. As a non-limiting example, these power components may include transistors, diodes, thyristors, or passive components (capacitors, inductors, etc.).

[0041] The present invention also relates to a method for manufacturing the semiconductor structure 100 as described above.

[0042] The production method first includes step a): providing a working layer 10 made of single-crystal silicon carbide. Figure 2a In step a), the working layer 10 has a free face 10a, which is intended to be assembled during subsequent steps of the method; this free face is also referred to as the front face 10a. The working layer also has a back face 10b opposite to its front face 10a. The thin film 10 has a uniform dopant concentration (first concentration C1) across its thickness. As mentioned earlier, a resistivity, for example, between a few ohms and 10 mohm·cm (i.e., between 1.10) can be used. 17 cm -3 The order of magnitude reached 1.10 19 cm -3 The first dopant concentration C1 is between orders of magnitude.

[0043] According to an advantageous embodiment, the working layer 10 originates from a transfer of material from the surface layer of the donor substrate 1, particularly based on Smart Cut. ™ Method layer transfer.

[0044] Therefore, step a) may include injecting a light material (e.g., hydrogen, helium, or a combination of both) into the donor substrate 1 (typically 4H-SiC) to form a buried vulnerable plane 11, which, together with the front side 10a of the donor substrate 1, defines the working layer 10. Figure 3a ]).

[0045] According to a variation of this embodiment, step a) includes forming a donor substrate 1 by epitaxially extending a donor layer 1' on an initial substrate before implanting the light material. Figure 3b This variation allows for the formation of a donor layer 1' with the structural and electrical properties required for the intended application. Specifically, excellent crystal quality can be obtained through epitaxy, and the in-situ doping of the donor layer 1' can be precisely controlled. Light material is then implanted into the donor layer 1' to form a buried vulnerable plane 11.

[0046] Alternatively, the working layer 10 provided in step a) can of course be formed by other known thin film transfer techniques.

[0047] The manufacturing method according to the invention then includes step b): providing a carrier substrate 30 made of polycrystalline silicon carbide ([ Figure 2b The carrier substrate 30 has a free surface 30a, which is intended to be assembled during subsequent steps of the method, and is also referred to as the front side 30a; the carrier substrate also has a back side 30b.

[0048] According to the present invention, the dopant concentration (second concentration C2) of the carrier substrate 30 is uniform across its thickness and is related to the first concentration C1 by the following relationship: C2 > N2 x exp(-C1 / N1), where N1 = 2.85.10 18 cm -3 And N2 = 5.40.10 20 cm -3 This is especially true when the working layer 10 and the carrier substrate 30 are N-type doped.

[0049] Advantageously, the resistivity of the carrier substrate 30 is less than or equal to 10 mohm.cm, or even 5 mohm.cm, 3 mohm.cm or 2 mohm.cm.

[0050] Then, the manufacturing method includes step c): on the free surface 10a to be assembled on the working layer 10 or on the free surface 30a to be assembled on the carrier substrate 30, or as [ Figure 2c As shown, a film 2 made of a metal or semiconductor material other than silicon carbide is deposited on two free surfaces 10a and 30a to be assembled.

[0051] It should be noted that the free surface 10a of the working layer 10 has a completely single-crystal surface; neither implantation doping nor bombardment activation has damaged or amorphized its crystal quality. Similarly, the free surface 30a of the carrier substrate 30 has a polycrystalline surface, which has not been modified or amorphized by any implantation doping or atomic bombardment activation.

[0052] Metallic materials may be selected from the following non-limiting list of materials: tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, and copper; semiconductor materials may be selected from the following non-limiting list of materials: silicon, germanium, carbon, III-V compounds such as gallium nitride, or other compounds formed from these materials (SiGe, SiGeC, etc.).

[0053] The film 2 has a thickness of less than or equal to 20 nm, preferably less than or equal to 10 nm, or even less than or equal to 5 nm. For example, the deposited film 2 may have a thickness of approximately 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 10 nm, or 15 nm.

[0054] It should be noted that when film 2 is deposited on two free surfaces 10a and 30a, the total deposition thickness (i.e., the sum of the thicknesses of film 2 deposited on one free surface 10a and the other free surface 30a) is preferably less than or equal to 20 nm, or even less than or equal to 10 nm. The total thickness of the deposited film 2 is always kept low so as to allow for segmentation of the film in the form of nodules 21 in subsequent steps of the method.

[0055] Membrane 2 is deposited in a non-oxidizing controlled atmosphere. It is extremely important that membrane 2 is not subjected to oxidation or deterioration from contamination from the surrounding atmosphere. Typically, the deposition in step c) takes place over approximately 10... -6 The procedure is performed under a high vacuum of Pa or less.

[0056] Depending on the nature of the deposited film 2, step c) is carried out at room temperature or low temperature, advantageously by sputter deposition, which uses neutral elements or elements (Ar, Si, N, etc.) that are not problematic as residual elements in the deposited metal to bombard the metal target.

[0057] According to a specific embodiment, the manufacturing method according to the invention includes a deoxidation step c') of the free surface 10a of the working layer 10 to be assembled and / or the free surface 30a of the carrier substrate 30 to be assembled, prior to the deposition step c). This step removes potential native oxides present on the surfaces of the working layer 10 and / or the carrier substrate 30. Deoxidation can be performed by wet chemical processing (e.g., HF etching) or dry processing (dry etching or annealing in a reducing atmosphere).

[0058] The manufacturing method then includes step d): forming an intermediate structure 150, said step including directly assembling the free surfaces 10a and 30a of the working layer 10 and the carrier substrate 30 to be assembled at the assembly interface 15, respectively. Figure 2d ]).

[0059] The direct assembly is preferably performed via molecular adhesion bonding, which involves bringing the surfaces 10a and 30a to be assembled into contact under a non-oxidizing controlled atmosphere. When the film is deposited only on the carrier substrate 30, it can be a direct bond between the working layer 10 and the film 2; or when the film is deposited only on the working layer 10, it can be a direct bond between the carrier substrate 30 and the film 2; or when the film is deposited on both the working layer 10 and the carrier substrate 30, it can even be a direct bond between the two films 2.

[0060] Direct bonding is preferably at about 10 -6 The procedure is performed under a high vacuum of Pa or less.

[0061] Advantageously, the deposition in step c) and the direct bonding in step d) can be linked in situ or in a multi-chamber apparatus without disrupting the vacuum. For example, the Atomic Diffusion Bonding BV7000 from Canon will be mentioned, in which the deposition and direct bonding of membrane 2' can be carried out continuously by maintaining a controlled atmosphere.

[0062] refer to Figures 3a to 3d In the advantageous embodiment shown, step d) includes directly assembling the free surface 10a of the working layer 10 to be assembled onto the free surface 30a of the carrier substrate 30 to be assembled, thereby producing a bonding assembly 200 including the donor substrate 1, the carrier substrate 30, and the assembly interface 15. Figure 3c Step d) further includes separation at the buried vulnerable plane 11 to form, on the one hand, an intermediate structure 150 comprising the working layer 10, the film 2, and the carrier substrate 30, and on the other hand, the remaining portion 1'' of the donor substrate. Figure 3d This separation can be performed during heat treatment, which allows cavities and microcracks induced by the injected material to grow in the embedded weak plane 11. See Smart Cut. ™ As is well known, separation can also be achieved by applying mechanical stress or by a combination of thermal and mechanical stress.

[0063] A sequence of cleaning, smoothing, polishing, or etching of the separation surface 10b of the working layer 10 and / or the separation surface 1''a of the remaining portion 1'' of the donor substrate can be performed to restore good surface quality, specifically in terms of roughness, defect rate, and other contamination.

[0064] Regardless of the implementation of this method, at the end of step d), the intermediate structure 150 has a front side 10b on one side of the working layer 10, a back side 30b on one side of the carrier substrate 30, and an encapsulated film 2' between the working layer 10 and the carrier substrate 30. It should be noted that when the film is deposited on only one of the free surfaces 10a and 30a to be assembled, the encapsulated film 2' corresponds to film 2, or to two films 2 respectively deposited on the working layer 10 and the carrier substrate 30.

[0065] The manufacturing method according to the invention then includes step e): annealing the intermediate structure 150 at a temperature between 1200°C and 2000°C (preferably at about 1700°C) to cause segmentation of the encapsulated film 2' in the form of nodules 21, and to cause dopant to diffuse from the carrier substrate 30 (doped in a very heavy manner) into the direct contact region 22 and optionally into the nodules 21. Step e) results in the formation of a semiconductor structure 100, the interface region 20 of which is located between the carrier substrate 30 and the working layer 10, the interface region 20 including the nodules 21 and the direct contact region 22 ([ Figure 2e ]).

[0066] The annealing temperature in step e) is selected such that the system, comprising the encapsulated film 2' and the semiconductor surfaces of the carrier substrate 30 and the working layer 10 in contact with said film 2', optimizes its surface energy in such a way that the encapsulated film 2' agglomerates into nodules 21 and creates direct contact regions 22 between the respective semiconductor surfaces of the working layer 10 and the carrier substrate 30. This temperature is also set such that the closure of the bonding interface in the direct contact region 22 between the single-crystal silicon carbide of the working layer 10 and the polycrystalline silicon carbide of the carrier substrate 30 is possible. Furthermore, the annealing temperature allows dopants to diffuse from the carrier substrate 30 into the direct contact region 22 and potentially into the nodules 21 (especially when these nodules are made of semiconductor material).

[0067] Considering the steep gradient of dopant concentration between the working layer 10 and the carrier substrate 30 (which is generated by the relationship between the first concentration C1 and the second concentration C2, as shown in […] Figure 5 As shown by the curves in [ ], the dopant diffuses very efficiently toward the working layer 10 and segregates at the interfaces present in the interface region 20 (i.e., the interface between single-crystal SiC and polycrystalline SiC), at each direct contact region 22, and at the interface between the material of nodule 21 and polycrystalline SiC. The amount of dopant that can segregate at these interfaces is much greater than the amount of dopant that can diffuse into the working layer (related to the solubility of dopant in single-crystal SiC). Notably, the interface between single-crystal SiC and polycrystalline SiC in the direct contact region 22 can be considered a very extensive grain boundary, where the dopant concentrates, preferably in the SiC bulk phase. Due to the roughness of this interface (particularly related to the presence of polycrystalline SiC grains), the dopant is distributed on both sides of the single-crystal SiC / polycrystalline SiC interface at a thickness of up to 5 nm.

[0068] The material constituting nodule 21 may also have a higher dopant solubility than in SiC; for example, this is the case at temperatures above the melting point when the material is silicon.

[0069] Known techniques, such as SIMS (secondary ion mass spectrometry), can be used to measure the dopant concentration distribution along the thickness of the semiconductor structure 100. The measurement points in the plane of the interface region 20 are large enough to integrate and average the distribution measurements over the individual elements constituting the interface region 20, i.e., primarily the nodules 21 and the direct contact region 22.

[0070] The dopant concentration distribution of semiconductor structure 100 takes the form of a steep step, with its transition consistent with interface region 20. This steepness reflects the fact that no dopant significantly diffuses from the carrier substrate 30 into the working layer 10, which is highly advantageous in terms of the properties and stability of said layer 10. This distribution also exhibits no doping peaks in interface region 20, or shows doping peaks in interface region 20 whose extreme values ​​correspond to a third dopant concentration equal to the second dopant concentration, with a deviation within ±10%.

[0071] The direct contact region 22 is doped to a level similar to that of the carrier substrate 30, and has a doping density of less than or equal to 0.01 mol·cm⁻¹. 2 The resistivity of the interface region is such that it gives the overall average resistivity similar to that of the interface region.

[0072] Therefore, the described manufacturing method produces a semiconductor structure 100 that provides excellent vertical electrical conduction between the working layer 10 and the carrier substrate 30 via an interface region 20, which is mainly composed of junctions 21 and direct contact regions 22. The diffusion of dopants from the carrier substrate 30 (due to the strong dopant concentration gradient between the working layer 10 and the carrier substrate 30) and their segregation at the various interfaces of the interface region 20 impart very low resistivity to the interface region.

[0073] Example implementation plan: Donor substrate 1 is made of high-quality single-crystal 4H SiC with a diameter of 150 mm. Donor substrate 1 is N-doped and has a resistivity of approximately 20 mol / L (first dopant concentration C1: 4.10). 18 cm -3 ). Through its front 1a (“C” shaped face) at 5.10 16 cm -2 Hydrogen ions are injected into it at a dose of 95 keV and an energy of 95 keV. This defines a buried vulnerable plane 11 near the injection depth, which together with the front side 10a of the donor substrate 1 defines the working layer 10.

[0074] The support substrate 30 is made of polycrystalline 3C SiC with the same diameter as the donor substrate 1. It is N-doped and has a resistivity of approximately 3 mol / cm (i.e., 5.10). 20 cm -3The second dopant concentration (C2).

[0075] Both substrates 1 and 30 undergo a cleaning sequence to remove particles and other surface contaminants. The sequence is preferably selected such that the surfaces of substrates 1 and 30 do not undergo oxidation (no native oxides are present).

[0076] Substrates 1 and 30 are introduced into the first deposition chamber and integrated into the direct bonding device. In 10 -6 Under vacuum and room temperature, a silicon film 2 with a thickness of 10 nm is deposited by sputtering onto each of the front surfaces 10a and 30a (free surfaces to be assembled) of substrates 1 and 30. Substrates 1 and 30 are then introduced into a second bonding chamber so that they can be assembled at their front surfaces 10a and 30a by bringing the films 2 deposited on the donor substrate 1 and the carrier substrate 30 into direct contact. The atmosphere in the bonding chamber is the same as that in the deposition chamber, which avoids any oxidation or passivation of the surface of the film 2.

[0077] After assembly, the bonding assembly 200 includes a donor substrate 1 connected to a carrier substrate 30 via a bonding interface 15, and an encapsulated film 2' formed by two films 2 deposited and embedded between the two substrates 1 and 30. The encapsulated film 2' has a thickness of approximately 20 nm.

[0078] The bonding component 200 is heat-treated at a temperature between 800°C and 1000°C for several minutes to several hours to induce separation at the buried vulnerable plane 11. An intermediate structure 150 is then obtained, comprising a working layer 10 with a thickness of 500 nm disposed on an encapsulated film 2', which itself is disposed on a carrier substrate 30. A cleaning and polishing sequence is applied to restore the surface 10b of the working layer 10 to the correct level of defects and roughness.

[0079] Finally, an annealing process at 1700°C for 30 minutes is applied to the intermediate structure 150, which previously had a protective layer on its front side 10b (also the free surface 10b of the working layer 10 in the intermediate structure 150). At the end of this annealing, the structure 100 according to the invention is obtained: due to the segregation of dopants from the carrier substrate 30 at the various interfaces of the interface region 20, the interface region 20 formed by the silicon junction 21 and the direct contact region 22 between the working layer 10 and the carrier substrate 30 imparts excellent vertical conductivity to the structure 100 (the average resistivity of the interface region is approximately 0.01 mohmcm). 2 ).

[0080] The nodules 21 in the structure 100 have a thickness of approximately 200 nm and an average diameter of approximately 100 nm to 1 μm. The coverage of the direct contact region 22 in the middle plane of the interface region 20 is approximately 80%. The dopant concentration distribution according to the thickness of the semiconductor structure 100 takes the form of a steep step, and the uniform concentration distribution of the working layer 10 does not change significantly.

[0081] Of course, the present invention is not limited to the described embodiments, and alternative embodiments can be added thereto without departing from the scope of the invention as defined by the claims.

Claims

1. A silicon carbide-based semiconductor structure (100), said semiconductor structure comprising: - A working layer (10) made of single-crystal silicon carbide, the working layer having a first dopant concentration (C1) uniform across the thickness of the working layer. - A carrier substrate (30) made of polycrystalline silicon carbide, the carrier substrate having a second dopant concentration (C2) uniform across its thickness, the second concentration (C2) being related to the first concentration (C1) by the following relationship: C2 > N2 x exp(-C1 / N1), where N1 = 2.85.10 18 cm -3 And N2 = 5.40.10 20 cm -3 , - Interface region (20), the interface region being located between the carrier substrate (30) and the working layer (10), the interface region comprising a nodule (21) and a direct contact region (22) located between the working layer (10) and the carrier substrate (30), the nodule (21) comprising a metal or semiconductor material other than silicon carbide, the interface region (20) having a density less than or equal to 0.01 molhm.cm 2 average resistivity, Dopant concentration distribution along the thickness of the semiconductor structure (100): -It takes the form of steps, and -No doping peaks are present in the interface region (20), or - A doping peak is exhibited in the interface region (20), the extreme value of which corresponds to the concentration of the third dopant, which is equal to the concentration of the second dopant, with a deviation within ±10%.

2. The semiconductor structure (100) according to any one of the preceding claims, wherein the resistivity of the carrier substrate is less than or equal to 10 molhm.cm, 5 molhm.cm, even 3 molhm.cm or even 2 molhm.cm.

3. The semiconductor structure (100) according to any one of the preceding claims, wherein the interface region has a thickness of less than or equal to 200 nm.

4. The semiconductor structure (100) according to any one of the preceding claims, wherein: - The metallic material of the nodules (21) is selected from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper, or The semiconductor material of the nodule (21) is selected from silicon, germanium, carbon, III-V compounds such as gallium nitride, or other compounds formed from these materials.

5. A method for manufacturing a silicon carbide-based semiconductor structure (100), the method comprising the following steps: a) Provide a working layer (10) made of single-crystal silicon carbide, the working layer having a free surface to be assembled and a first dopant concentration (C1) uniform across the thickness of the working layer. b) Provide a carrier substrate (30) made of polycrystalline silicon carbide, the carrier substrate having a free surface to be assembled and a second dopant concentration (C2) uniform across the thickness of the carrier substrate, the second concentration (C2) being related to the first concentration (C1) by the following relationship: C2 > N2 x exp(-C1 / N1), where N1 = 2.85.10 18 cm -3 And N2 = 5.40.10 20 cm -3 , c) Deposit a film (2) of a metal or semiconductor material other than silicon carbide with a thickness of 20 nm or less on the free surface to be assembled on the working layer (10) and / or on the free surface to be assembled on the carrier substrate (30). d) Forming an intermediate structure (150), the step of forming the intermediate structure comprising directly assembling the free surface to be assembled of the working layer (10) and the free surface to be assembled of the carrier substrate (30), the intermediate structure (150) comprising an encapsulated film (2') derived from one or more films (2) deposited during step c). e) The intermediate structure (150) is annealed at a temperature between 1200°C and 2000°C to form the semiconductor structure (100) including an interface region (20) comprising a direct contact region (22) between the thin layer (10) and the carrier substrate (30) and nodules (21) formed by the segmentation of the encapsulated film (2'). - The interface region (20) has a size less than or equal to 0.01 mohm.cm. 2 average resistivity, - The dopant concentration distribution along the thickness of the semiconductor structure (100) is in the form of steps, and there is no doping peak in the interface region (20); or a doping peak is exhibited in the interface region (20), the extreme value of which corresponds to a third dopant concentration equal to the second dopant concentration (C2), with a deviation within ±10%.

6. The manufacturing method according to claim 5, wherein step a) includes implanting a light material into a donor substrate (1) made of single-crystal silicon carbide to form a buried vulnerable plane (11), the buried vulnerable plane defining the working layer (10) together with the front side of the donor substrate (1).

7. The manufacturing method according to any one of claims 5 and 6, wherein step d) comprises, after the direct assembly of the bonding assembly (200) comprising the donor substrate (1) and the carrier substrate (30), separation at the buried vulnerable plane (11) to form, on the one hand, the intermediate structure (150) comprising the working layer (10), the encapsulated film (2') and the carrier substrate (30), and on the other hand, the remaining portion (1'') of the donor substrate.

8. The manufacturing method according to any one of claims 5 to 7, wherein prior to step c), the free surface of the thin film (10) to be assembled has a single crystal surface, the single crystal surface having no regions that are activated by doping or bombardment and are non-crystallized or damaged, and the free surface of the carrier substrate (30) to be assembled has a polycrystalline surface, the polycrystalline surface having no regions that are activated by doping or bombardment and are non-crystallized or modified.

9. The manufacturing method according to any one of claims 5 to 8, the manufacturing method comprising the step of epitaxially growing an additional layer of single-crystal silicon carbide on the working layer (10) of the semiconductor structure (100).

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