A detection circuit for a power board
By designing a power board detection circuit and using voltage divider and comparator units to determine the state of bridge arm transistors, the reliability problem of fault detection at the single-board stage is solved, and the safety of detection and product quality are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG TOPSTAR TECH
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-09
Smart Images
Figure CN122171981A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of fault detection technology, and in particular to a detection circuit for a power board. Background Technology
[0002] In the production process of servo drives, the power boards, which are the core components, are generally tested during the production phase. These power boards are typically tested in batches using specialized testing tools developed by the R&D team; these tools are also known as testing fixtures. Usually, once a product enters the mass production stage, the design's rationality has already been verified. The main purpose of mass production fixture testing is to eliminate the risk of faults such as poor soldering or component damage, preventing defective products from entering the market and causing greater losses.
[0003] However, the existing technology does not provide a complete and reliable solution for completing power board testing at the single-board stage. Summary of the Invention
[0004] This invention provides a detection circuit for a power board, which reliably performs fault detection on the power board at the single-board stage.
[0005] According to one aspect of the present invention, a detection circuit for a power board is provided, the power board including a bridge arm, the bridge arm including a first transistor and a second transistor; the detection circuit for the power board includes: a main control module and a detection module, the detection module including: a voltage divider unit and a comparison unit; The first terminal of the first transistor and the first terminal of the voltage divider unit are both connected to a first power supply voltage. The second terminal of the first transistor is connected to the voltage divider terminal of the voltage divider unit and the first terminal of the second transistor. The second terminal of the second transistor and the second terminal of the voltage divider unit are both connected to a second power supply voltage. When the voltage divider unit is not connected to the bridge arm, the voltage divider terminal has the first voltage. The comparison unit is connected to the voltage divider terminal of the voltage divider unit and is connected to a first reference voltage and a second reference voltage. The comparison unit is used to generate an output signal based on the relationship between the voltage at the voltage divider terminal and the first reference voltage, and the relationship between the voltage at the voltage divider terminal and the second reference voltage. The first reference voltage is less than the first power supply voltage and greater than the first voltage, and the second reference voltage is less than the first voltage and greater than the second power supply voltage. The bridge arm is used to control the on / off state of the first transistor and the second transistor in response to a test signal; each test signal corresponds to a target output signal; The main control module is connected to the comparison unit, and the main control module is used to determine whether the bridge arm has failed based on whether the output signal and the target output signal are consistent.
[0006] Optionally, the comparison unit includes a first comparator and a second comparator; The first input terminal of the first comparator is connected to the voltage divider terminal, the second input terminal of the first comparator is connected to the first reference voltage, and the output terminal of the first comparator is connected to the main control module. The first input terminal of the second comparator is connected to the second reference voltage, the second phase input terminal of the second comparator is connected to the voltage divider terminal, and the output terminal of the second comparator is connected to the main control module.
[0007] Optionally, the detection module further includes a first digital input unit and a second digital input unit; The input terminal of the first digital input unit is connected to the output terminal of the first comparator, and the output terminal of the first digital input unit is connected to the main control module. The first digital input unit is used to electrically isolate and level-convert the signal output from the output terminal of the first comparator and then input it to the main control module. The input terminal of the second digital input unit is connected to the output terminal of the second comparator, and the output terminal of the second digital input unit is connected to the main control module. The second digital input unit is used to electrically isolate and level-convert the signal output from the output terminal of the second comparator and then input it to the main control module.
[0008] Optionally, the detection module further includes a third resistor, a fourth resistor, and a fifth resistor connected in series between the third power supply terminal and the fourth power supply terminal. The common terminal connecting the third resistor and the fourth resistor is connected to the second input terminal of the first comparator, and is used to output the first reference voltage. The common terminal of the fourth resistor and the fifth resistor is connected to the first input terminal of the second comparator, and is used to output the second reference voltage; The voltage divider unit includes a first resistor and a second resistor; The first end of the first resistor is connected to the first power supply voltage, the second end of the first resistor is connected to the first end of the second resistor, the second terminal of the first transistor and the comparator unit, and the second end of the second resistor is connected to the second power supply voltage.
[0009] Optionally, the test signal includes a first control signal and a second control signal, wherein the first control signal is configured to control the on / off state of the first transistor in three stages, and the second control signal is configured to control the on / off state of the second transistor in three stages, wherein the three stages include a first stage, a second stage, and a third stage. In the first stage, the first control signal has a first turn-off potential, and the second control signal has a second turn-off potential; the first turn-off potential is a potential for controlling the first transistor to turn off, and the second turn-off potential is a potential for controlling the second transistor to turn off. In the second stage, the first control signal has a first turn-on potential and the second control signal has a second turn-off potential; the first turn-on potential is the potential that controls the first transistor to turn on; In the third stage, the first control signal has the first turn-off potential and the second control signal has the second turn-on potential; the second turn-on potential is the potential that controls the second transistor to turn on.
[0010] Optionally, the pulse frequency of the first control signal is equal to the pulse frequency of the second control signal; The power board is used to transmit a first working signal to the control terminal of the first transistor and a second working signal to the control terminal of the second transistor when driving the load to work. The pulse frequency of the first working signal is equal to the pulse frequency of the second working signal, and the pulse frequency of the first control signal is less than the pulse frequency of the first working signal.
[0011] Optionally, the power board further includes a slave control module, the master control module is connected to the slave control module, and the master control module is used to transmit detection trigger signals to the slave control module; The slave control module is used to send a test signal to the bridge arm after receiving the detection trigger signal.
[0012] Optionally, the power board includes at least one bridge arm, and the detection module is configured in a one-to-one correspondence with the bridge arm.
[0013] Optionally, the detection circuit of the power board further includes a short-circuit detection module corresponding to the bridge arm. The short-circuit detection module is connected to the bridge arm and is used to generate a short-circuit detection signal according to the short-circuit state of the bridge arm. The short-circuit state includes a short-circuit state and a short-circuit state. The main control module is connected to the short circuit detection module. The main control module is used to control the generation of the test signal when it is determined that no short circuit has occurred in the bridge arm based on the short circuit detection signal.
[0014] Optionally, the short-circuit detection module includes: a shunt and a third comparator; The first end of the current shunt is connected to the second terminal of the second transistor, and the second end of the current shunt is connected to the second end of the voltage divider unit; The first input terminal of the third comparator is connected to the first terminal of the shunt, the second input terminal of the third comparator is connected to the third reference voltage, and the output terminal of the third comparator is connected to the main control module.
[0015] In this embodiment, the detection circuit sends test signals to the bridge arms before the power board is installed in the complete system, i.e., at the single-board stage, to determine whether the bridge arms of the power board are faulty. After receiving the test signal, the bridge arm controls the corresponding first and second transistors to operate, causing the voltage divider to output a voltage. The voltage output from the voltage divider is then compared with two reference voltages by a comparison unit to generate an output signal. When the output signal matches the target output signal corresponding to the test signal, it indicates that both transistors have performed the on or off action according to the signal in the test signal, confirming that both transistors in the bridge arm are normal. Furthermore, the voltage at the voltage divider must be compared with the first and second reference voltages separately before generating an output signal, avoiding the problem of low reliability when comparing the voltage at the voltage divider with a single reference voltage, thus improving the reliability of the detection.
[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the detection circuit of a power board provided in an embodiment of the present invention; Figure 2 A schematic diagram of the detection circuit of another power board provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a first digital input unit provided for the implementation of the present invention. Detailed Implementation
[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0021] The power board includes bridge arms, each including a first transistor and a second transistor. The power board may include at least one bridge arm, each including an upper bridge arm and a lower bridge arm. The upper bridge arm includes a transistor (the first transistor), and the lower bridge arm includes a transistor (the second transistor). In this embodiment, the power board can be a power board for driving a servo motor. In practical applications, it is connected to the servo motor to drive its operation.
[0022] Figure 1 This is a schematic diagram of the detection circuit of a power board provided in an embodiment of the present invention, with reference to... Figure 1 The detection circuit 1 includes a main control module 10 and a detection module 11. The detection module 11 includes a voltage divider unit and a comparison unit 112. The power board 2 includes at least one bridge arm, such as one bridge arm or three bridge arms. The detection module 11 is configured to correspond one-to-one with each bridge arm. When the power board 2 includes three bridge arms, the three bridge arms can simultaneously receive test signals to perform the following fault detection, or the three bridge arms can receive test signals sequentially to perform fault detection. The test signals received by the three bridge arms can be the same or different, and there is no specific limitation on this.
[0023] The first terminal of the first transistor T1 and the first terminal of the voltage divider unit 111 are both connected to the first power supply voltage VCC1. The second terminal of the first transistor T1 is connected to the voltage divider terminal U0 of the voltage divider unit 111 and the first terminal of the second transistor T2. The second terminal of the second transistor T2 and the second terminal of the voltage divider unit 111 are both connected to the second power supply voltage. When the voltage divider unit 111 is not connected to the bridge arm, the voltage divider terminal U0 has a first voltage. The first voltage is obtained by dividing the difference between the first power supply voltage VCC1 and the second power supply voltage by the impedance between the first terminal and the voltage divider terminal of the voltage divider unit 111 and the impedance between the second terminal and the voltage divider terminal of the voltage divider unit 111. The test signal may include two control signals, one for controlling the first transistor to turn on or off, and the other for controlling the second transistor T2 to turn on or off. The voltage divider terminal has different voltages when the bridge arm is in different on / off states. Specifically, when the on / off state is that the first transistor T1 is on and the second transistor T2 is off, the voltage at the voltage divider terminal U0 is the first power supply voltage VCC1; when the on / off state is that the first transistor T1 is off and the second transistor T2 is off, the voltage at the voltage divider terminal U0 is the first voltage; and when the on / off state is that the first transistor T1 is off and the second transistor T2 is on, the voltage at the voltage divider terminal U0 is the second power supply voltage.
[0024] The first transistor T1 can be a MOS transistor or an IGBT transistor. In this embodiment, both the first transistor T1 and the second transistor T2 are NMOS transistors. The first terminal of the first transistor T1 can be the source, the second terminal can be the drain, and the control terminal for receiving the test signal is the gate. The first terminal of the second transistor T2 can be the source, the second terminal can be the drain, and the control terminal for receiving the test signal is the gate. The test signal includes a first control signal G1 and a second control signal G2. The first control signal G1 is configured to be transmitted to the gate of the first transistor T1 to cause the first transistor T1 to turn on or off in response to the first control signal. The second control signal G2 is configured to be transmitted to the gate of the second transistor T2 to cause the second transistor T2 to turn on or off in response to the second control signal G2. The first power supply voltage VCC1 is less than a preset voltage and greater than the second power supply voltage. The second power supply voltage can be the first ground potential, that is, the second terminal of the voltage divider unit 111 and the second terminal of the second transistor T2 are both connected to the first ground potential GND1. Optionally, the first power supply voltage VCC1 is greater than 0V and less than 50V. Preferably, the first power supply voltage VCC1 is equal to 24V. In existing technologies, fault detection of the power board 2 is generally performed when the power board 2 drives the load. Under normal operating conditions, a 300V DC current is connected between the first electrode of the first transistor T1 and the second electrode of the second transistor T2. However, in this embodiment, during the detection phase, the differential voltage between the first transistor T1 and the second transistor T2 is a 24V DC current, which eliminates the safety risks of high-voltage electric shock to operators and high-voltage damage to devices, and greatly improves the safety of the detection.
[0025] The comparison unit 112 is connected to the voltage divider terminal U0 of the voltage divider unit 111. The comparison unit 112 is also connected to the first reference voltage VF1 and the second reference voltage VF2. The comparison unit 112 is used to generate an output signal based on the relationship between the voltage of the voltage divider terminal U0 and the first reference voltage VF1, and the relationship between the voltage of the voltage divider terminal U0 and the second reference voltage VF2. The first reference voltage VF1 is less than the first power supply voltage VCC1 and greater than the first voltage, and the second reference voltage VF1 is less than the first voltage and greater than the second power supply voltage.
[0026] The comparator unit 112 has two output terminals, referred to as the first output terminal and the second output terminal, respectively. In an optional embodiment, the comparator unit 112 is configured to output a high potential through the first output terminal when the voltage at the voltage divider terminal U0 is greater than the first reference voltage VF1, and output a low potential through the first output terminal when the voltage at the voltage divider terminal U0 is less than the first reference voltage VF1; or, output a low potential through the first output terminal when the voltage at the voltage divider terminal U0 is greater than the first reference voltage VF1, and output a high potential through the first output terminal when the voltage at the voltage divider terminal U0 is less than the first reference voltage VF1. The comparator unit 112 is further configured to output a high potential through the second output terminal when the second reference voltage VF2 is greater than the voltage at the voltage divider terminal U0, and output a low potential through the second output terminal when the second reference voltage VF2 is less than the voltage at the voltage divider terminal U0; or, output a low potential through the second output terminal when the second reference voltage VF2 is greater than the voltage at the voltage divider terminal U0, and output a high potential through the second output terminal.
[0027] The bridge arm is used to control the on / off state of the first transistor T1 and the second transistor T2 in response to test signals; each test signal corresponds to a target output signal.
[0028] The main control module 10 is connected to the comparison unit 112. The main control module 10 is used to determine whether a bridge arm has failed based on whether the output signal and the target output signal are consistent. Optionally, the main control module 10 is used to determine whether the first transistor T1 and / or the second transistor T2 has failed based on whether the output signal and the target output signal are consistent. When the output signal and the target output signal are consistent, it is determined that the bridge arm has not failed; when the output signal and the target output signal are inconsistent, it is determined that the bridge arm has failed, so that the two transistors in the bridge arm can be replaced subsequently.
[0029] The test signal is used to characterize the target on / off state of the bridge arm. When the bridge arm is in a certain target on / off state, the corresponding voltage divider terminal U0 outputs the target voltage. The output signal generated by the comparison unit 112 based on the relationship between the target voltage and the first reference voltage VF1, and the relationship between the target voltage and the second reference voltage VF2, is the target output signal corresponding to the test signal.
[0030] For example, in the first stage, the first control signal in the test signal is at a high potential and the second control signal is at a low potential. Therefore, the target on / off state is that the first transistor T1 is on and the second transistor T2 is off. The target voltage corresponding to the voltage divider terminal U0 is the first power supply voltage VCC1. Taking the comparison unit 112 as an example, when the voltage at the voltage divider terminal U0 is greater than the first reference voltage VF1, it outputs a high potential through the first output terminal; when the voltage at the voltage divider terminal is less than the first reference voltage VF1, it outputs a low potential through the first output terminal; when the second reference voltage VF2 is greater than the voltage at the voltage divider terminal U0, it outputs a high potential through the second output terminal; and when the second reference voltage VF2 is less than the voltage at the voltage divider terminal U0, it outputs a low potential through the second output terminal. When the target voltage is the first power supply voltage VCC1, the comparison unit 112 outputs a high potential from the first output terminal and a low potential from the second output terminal. That is, the target output signal includes a sequence composed of the high potential from the first output terminal and the low potential from the second output terminal, such as "10".
[0031] When the first transistor T1 is able to turn on in response to the high potential of the first control signal G1 and the second transistor T2 is able to turn off in response to the low potential of the second control signal G2, the output signal of the comparison unit 112 is also "10", then the target output signal matches the output signal, and neither the first transistor T1 nor the second transistor T2 has failed. If the first transistor T1 fails to turn on in response to the high potential of the first control signal G1 in the test signal, then the first transistor T1 is actually in the off state. When the second transistor T2 is able to turn off in response to the low potential of the second control signal G2 in the test signal, the voltage output by the voltage divider terminal U0, i.e., the target voltage, is the first voltage. At this time, the first output terminal of the comparison unit 112 outputs a low potential and the second output terminal outputs a low potential, that is, the output signal of the comparison unit 112 is "00", the output signal is inconsistent with the target output signal, and the first transistor T1 is determined to have failed based on the target output signal and the output signal corresponding to the test signal in the first stage. In the second stage, the first control signal G1 is at a low potential and the second control signal G2 is at a high potential in the test signal, so the corresponding target output signal is "01". If at this time, the first transistor T1 is normally turned off according to the first control signal G1 and the second transistor T2 is not turned on according to the corresponding potential of the second control signal G2, that is, the second transistor T2 is actually in the off state, then the output signal is "00". The output signal and the target output signal do not match, and according to the target output signal and the output signal corresponding to the test signal in the second stage, it is determined that the second transistor T2 has failed.
[0032] In this embodiment, the detection circuit sends test signals to the bridge arms to determine if any bridge arms of the power board are faulty, before the power board is integrated into the complete system. Upon receiving the test signal, the bridge arm controls the corresponding first and second transistors to operate, causing the voltage divider to output a voltage. This voltage is then compared with two reference voltages by a comparison unit to generate an output signal. When the output signal matches the target output signal corresponding to the test signal, it indicates that both transistors have performed the on / off action according to the test signal, confirming that both transistors in the bridge arm are functioning normally. Furthermore, the voltage at the voltage divider must be compared with both the first and second reference voltages separately before generating an output signal, avoiding the low reliability of comparing the voltage at the voltage divider with a single reference voltage and improving the reliability of the detection.
[0033] In one optional implementation, the main control module generates test signals and transmits them to the bridge arm. Alternatively, in other embodiments, the main control module communicates with a control module integrated into the power board to enable the control module in the power board to generate test signals. Specifically, Figure 2 This is a schematic diagram of the detection circuit of another power board provided in an embodiment of the present invention, with reference to... Figure 2 The power board 2 also includes a slave control module 21, and the master control module 10 is connected to the slave control module 21. The master control module 10 is used to transmit detection trigger signals to the slave control module 21. The slave control module 21 is used to send a test signal to the bridge arm after receiving the detection trigger signal.
[0034] The control module built into the power board 2 is used as the slave control module 21. The master control module 10 and the slave control module 21 establish communication through a communication bus. When the master control module 10 determines that the power board needs to be tested, it sends a detection trigger signal to the slave control module 21, so that the slave control module 21 responds to the detection trigger signal and sends a test signal to the bridge arm. Optionally, the power board 2 also includes an isolation module 22, and the test signal is output to the bridge arm after passing through the isolation module 22. When the slave control module 21 generates the test signal based on the detection trigger signal, the detection trigger signal can be a signal indicating that the test signal has a specific potential at different stages. The master control module 10 stores the target output signal corresponding to the test signal generated based on the detection trigger signal. Then, the master control module 10 determines whether the transistor in the bridge arm has failed based on whether the actual output signal of the comparison unit 112, i.e., the output signal, is consistent with the target output signal.
[0035] Continue to refer to Figure 1 Optionally, the test signal includes a first control signal and a second control signal. The first control signal is configured to control the on / off state of the first transistor T1 in three stages, and the second control signal is configured to control the on / off state of the second transistor T2 in three stages, including a first stage, a second stage, and a third stage. In the first stage, the first control signal G1 has a first turn-off potential, and the second control signal G2 has a second turn-off potential; the first turn-off potential is the potential for controlling the first transistor T1 to turn off, and the second turn-off potential is the potential for controlling the second transistor T2 to turn off. In the second stage, the first control signal G1 has a first turn-on potential and the second control signal G2 has a second turn-off potential; the first turn-on potential is the potential that controls the first transistor T1 to turn on; In the third stage, the first control signal G1 has a first turn-off potential and the second control signal G2 has a second turn-on potential; the second turn-on potential is the potential that controls the second transistor T2 to turn on.
[0036] Taking the first transistor T1 and the second transistor T2 as examples where both are NMOS transistors, the first turn-on potential and the second turn-on potential are both high potentials, which can be denoted as "1", and the second turn-off potential and the first turn-off potential are both low potentials, which can be denoted as "0".
[0037] The first, second, and third phases can form a continuous time period, and the order of the three phases is not specifically limited. The order of the three phases can be the first, second, and third phases, or the first, third, and second phases, or any other order.
[0038] When the test signal in each of the three stages is consistent with the target output signal in that stage, it is determined that the first and second transistors in the bridge arm are normal and can be turned on or off according to the signals connected to their respective gates. If the output signal in any stage is inconsistent with the target output signal in that stage, it is determined that at least one transistor in the bridge arm is faulty.
[0039] Continue to refer to Figure 2 Optionally, the pulse frequency of the first control signal G1 is equal to the pulse frequency of the second control signal G2. The power board is used to transmit a first working signal to the control terminal of the first transistor T1 and a second working signal to the control terminal of the second transistor T2 when the drive load is working. The pulse frequency of the first working signal is equal to the pulse frequency of the second working signal, and the pulse frequency of the first control signal G1 is less than the pulse frequency of the first working signal.
[0040] When detecting whether the transistors in the bridge arm of the power board 2 can be turned on or off according to the signal input to the control terminal, the first control signal G1 input to the control terminal of the first transistor T1 and the second control signal G2 input to the control terminal of the second transistor T2 are both PWM signals. When the power board is put into use and drives the load, the first working signal input to the control terminal of the first transistor T1 and the second working signal input to the control terminal of the second transistor T2 are both PWM signals. However, both the first working signal and the second working signal are high-frequency signals with a pulse frequency greater than a preset frequency value. If the first control signal G1 and the second control signal G2 sent to the bridge arm are also high-frequency signals when detecting the power board 2, the detection circuit 1 is required to have a fast response capability. Otherwise, the output signal of the comparison unit 112 received by the main control module 10 may not be able to follow the changes in the test signal, resulting in a deviation in the detection result. Therefore, in this embodiment, the pulse frequencies of the first control signal G1 and the second control signal G2 are set to be lower than the pulse frequencies of the first working signal or the second working signal to reduce the requirement for the response speed of the detection circuit 1, ensure that the output signal of the comparison unit 112 can follow the changes in the test signal, and improve the detection reliability.
[0041] Continue to refer to Figure 2 Optionally, the comparison unit 112 includes a first comparator 1121 and a second comparator 1122; The first input terminal of the first comparator 1121 is connected to the voltage divider terminal U0, the second input terminal of the first comparator 1121 is connected to the first reference voltage VF1, and the output terminal U+ of the first comparator 1121 is connected to the main control module 10.
[0042] The first input terminal of the second comparator 1122 is connected to the second reference voltage VF2, the second input terminal of the second comparator 1122 is connected to the voltage divider terminal U0, and the output terminal U- of the second comparator 1122 is connected to the main control module 10.
[0043] The first input terminal of the first comparator 1121 is a non-inverting input terminal and the second input terminal is an inverting input terminal, or the first input terminal of the first comparator 1121 is an inverting input terminal and the second input terminal is a non-inverting input terminal. The first input terminal of the second comparator 1122 is a non-inverting input terminal and the second input terminal is an inverting input terminal, or the first input terminal of the second comparator 1122 is an inverting input terminal and the second input terminal is a non-inverting input terminal. In this embodiment, taking the example that the first input terminals of the first comparator 1121 and the first input terminals of the second comparator 1122 are both non-inverting input terminals and the second input terminals of the first comparator 1121 and the second input terminals of the second comparator 1122 are both inverting input terminals, the test signal is configured with potential in three stages to complete the fault detection of the bridge arm.
[0044] This embodiment provides a truth table for detection, as shown in Table 1.
[0045] Table 1 Truth Table for Testing In the first stage, when the first control signal G1 is at a low potential "0" and the second control signal G2 is at a low potential "0", if both the first transistor T1 and the second transistor T2 can respond normally to their respective control signals, the potential of the voltage divider terminal U0 is the first voltage, which is less than the first reference voltage VF1. The first comparator 1121 outputs a low potential 0, and the first voltage is greater than the second reference voltage VF2. The second comparator 1122 outputs a low potential 0. In the second stage, when the first control signal G1 is at a high potential "1" and the second control signal G2 is at a low potential "0", if both the first transistor T1 and the second transistor T2 can respond normally to their respective control signals, the potential of the voltage divider terminal U0 is the first power supply voltage VCC1, which is greater than the first reference voltage VF1. The first comparator 1121 outputs a high potential 1, and the first power supply voltage is greater than the second reference voltage VF2. The second comparator 1122 outputs a low potential 0. In the third stage, when the first control signal G1 is at a low potential "0" and the second control signal G2 is at a high potential "1", if both the first transistor T1 and the second transistor T2 can respond normally to their respective control signals, the potential of the voltage divider terminal U0 is the second power supply voltage. Since the second power supply voltage is less than the first reference voltage VF1, the first comparator 1121 outputs a low potential 0. Since the second power supply voltage is less than the second reference voltage VF2, the second comparator 1122 outputs a high potential 1. The target output signal for the first stage is "00", the target output signal for the second stage is "10", and the target output signal for the third stage is "01". Therefore, in the first stage, the output signal is "00", in the second stage, the output signal is "10", and in the third stage, the output signal is "01". The target output signal for each stage is consistent with the output signal, completing the three-state detection of the bridge arm and confirming that the bridge arm is normal. Simultaneously, the faulty transistor can be identified by combining the target output signals and the output signals corresponding to the three stages. If the output signal is "10" in the first stage, it indicates that the first transistor T1 has failed to respond to the control terminal signal and is turned off, meaning the first transistor T1 has failed. If the output signal is "01", it indicates that the second transistor T1 has failed to respond to the control terminal signal and is turned off, meaning the first transistor T1 has failed. And / or, in the second stage, if the output signal is "00", it indicates that the first transistor T1 has failed to respond to the control terminal signal and is turned on, meaning the first transistor T1 has failed. If the output signal is "01", it indicates that both the first transistor T1 and the second transistor T2 have failed.And / or, in the third stage, if the output signal is "00", it is determined that the second transistor T2 is not turned on in response to the control terminal signal, and the second transistor T1 has failed. If the output signal is "10", it is determined that the first transistor T1 is turned off in response to the control terminal signal and the second transistor T1 is turned on in response to the control terminal signal, and both the first transistor T1 and the second transistor T2 have failed.
[0046] Continue to refer to Figure 2 Optionally, the detection module 11 also includes a first digital input unit 113 and a second digital input unit 114; The input terminal IN1 of the first digital input unit 113 is connected to the output terminal U+ of the first comparator 1121, and the output terminal of the first digital input unit 113 is connected to the main control module 10. The first digital input unit 113 is used to electrically isolate and level-convert the signal output from the output terminal U+ of the first comparator 1121 and then input it to the main control module 10. The input terminal of the second digital input unit 114 is connected to the output terminal U- of the second comparator 1122, and the output terminal U- of the second digital input unit 114 is connected to the main control module 10. The second digital input unit 114 is used to electrically isolate and level-convert the signal output from the output terminal of the second comparator 1122 and then input it to the main control module 10.
[0047] The high and low potentials output by the first comparator 1121 and the second comparator 1122 may not be within the voltage range that the main control module 10 can recognize. Therefore, they need to be electrically isolated and converted to high and low potentials that the main control module 10 can recognize through two digital input units. For example, the high potential output by the first comparator 1121 is converted to a high potential that the main control module 10 can recognize through the first digital input unit 113, and the low potential output by the first comparator 1121 is converted to a low potential that the main control module 10 can recognize through the first digital input unit 113. Similarly, the high potential output by the second comparator 1122 is converted to a high potential that the main control module 10 can recognize through the second digital input unit 114, and the low potential output by the second comparator 1122 is converted to a low potential that the main control module 10 can recognize through the second digital input unit 114. The high potential relative to the first comparator 1121 is different from the high potential relative to the main control module 10, and the same applies to the low potential, so level conversion is required.
[0048] Figure 3 A schematic diagram of the structure of a first digital input unit provided for implementation of the present invention is shown below. Figure 2 and Figure 3Optionally, both the first digital input unit 113 and the second digital input unit 114 include an opto-isolator. The opto-isolator includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second capacitor C2, and an optocoupler 1131. Figure 3 Taking the structure of the first digital input unit as an example, the first end of the seventh resistor R7 serves as the input terminal IN1 of the first digital input unit 113. The second end of the seventh resistor R7 is connected to the first end of the second capacitor C2, the first end of the eighth resistor R8, and the first input terminal of the optocoupler 1131. The second ends of the second capacitor C2, the eighth resistor R8, and the second input terminal of the optocoupler 1131 are all connected to the first ground potential GND1. The first output terminal of the optocoupler 1131 is connected to the third power supply voltage VCC3, such as 3.3V. The second output terminal of the optocoupler 1131 is connected to the first ends of the ninth resistor R9 and the tenth resistor R10. The second end of the ninth resistor R9 is connected to the second ground potential GND2, and the second end of the tenth resistor R10 is connected to the main control module 10. The first ground potential GND1 is different from the second ground potential GND2. When the first comparator 1121 outputs a high potential relative to itself, this high potential controls the diode in the optocoupler 1131 to emit light, thereby turning on the transistor K1 in the optocoupler 1131. The first digital input unit 113 outputs the third power supply voltage VCC3 to the main control module 10. The third power supply voltage VCC3 is a voltage that the main control module 10 can recognize and is a recognizable high potential, thereby converting the high potential relative to the first comparator 1121 into a high potential that the main control module 10 can recognize. When the first comparator 1121 outputs a low potential relative to itself, this low potential controls the diode in the optocoupler 1131 to not emit light, thereby turning off the transistor K1 in the optocoupler 1131. The first digital input unit 113 outputs the second ground potential GND2 to the main control module 10. The second ground potential GND2 is a voltage that the main control module 10 can recognize and is a recognizable low potential, thus converting the low potential relative to the first comparator 1121 into a low potential that the main control module 10 can recognize. The structure and working principle of the second digital input unit 114 are the same as those of the first digital input unit 113, and will not be described again here.
[0049] Continue to refer to Figure 2 Optionally, the power board's detection circuit also includes a short-circuit detection module 12, which is connected to the bridge arm. The short-circuit detection module 12 is used to generate a short-circuit detection signal based on the short-circuit state of the bridge arm. The short-circuit state includes a short-circuit state and a short-circuit state. The main control module 10 is connected to the short circuit detection module 12. The main control module 10 is used to control the generation of test signals when it is determined that no short circuit has occurred in the bridge arm based on the short circuit detection signal.
[0050] The short-circuit detection module 12 can be configured one-to-one with each bridge arm. The short-circuit detection module 12 can be a current sensor used to detect the current in the branch where the bridge arm is located. The short-circuit detection signal includes a first signal and a second signal. In an optional embodiment, if the current of the bridge arm is greater than a preset threshold, it is determined that both the first transistor T1 and the second transistor T2 in the bridge arm are conducting, and the bridge arm is in a short-circuit state. The short-circuit detection module 12 generates a first signal. When the main control module 10 receives the first signal, it determines that the bridge arm is conducting, generates an alarm signal, and triggers short-circuit protection. If the current of the bridge arm is less than the preset threshold, it is determined that the bridge arm is not short-circuited, and the bridge arm is in a non-short-circuit state. The short-circuit detection module 12 generates a second signal. When the main control module 10 receives the second signal, it controls the generation of a test signal and transmits it to the bridge arm so that the bridge arm receives the test signal. This allows the main control module 10 to determine whether the first transistor T1 and the second transistor T2 in the bridge arm have failed based on the target output signal and the output signal.
[0051] In this embodiment, when the power board 2 is being tested, the short circuit detection module 12 is used to detect short circuits in the power board 2 in real time. When the main control module 10 determines that a bridge arm has a short circuit, it controls the test signal corresponding to that bridge arm to stop being generated and directly generates an alarm signal for that bridge arm. Other bridge arms that have not been short-circuited can continue to receive test signals for testing.
[0052] Continue to refer to Figure 3 Optionally, the short-circuit detection module 12 includes a shunt 121 and a third comparator 122; The first end of the current shunt 121 is connected to the second terminal of the second transistor T2, and the second end of the current shunt 121 is connected to the second end of the voltage divider unit 111. The first input terminal of the third comparator 122 is connected to the first terminal of the shunt 121, the second input terminal of the third comparator 122 is connected to the third reference voltage VF3, and the output terminal of the third comparator 122 is connected to the main control module 10.
[0053] For each bridge arm, the corresponding first transistor T1, second transistor T2, and shunt 121 are connected in series between the first port connected to the first power supply voltage VCC1 and the second port connected to the second power supply voltage. Because the impedance of shunt 121 is very small, approximately in the μΩ range, while the impedance of voltage divider unit 111 is in the KΩ range, the ratio of the impedance of shunt 121 to the impedance between the first terminal and the voltage divider terminal U0 of voltage divider unit 111 is less than 10. -9 And / or, the ratio of the impedance of shunt 121 to the impedance between the second terminal and the voltage divider terminal U0 of voltage divider unit 111 is less than 10. -9Therefore, the resistance of the shunt can be ignored relative to the impedance of the voltage divider unit 111. When calculating the voltage at the voltage divider terminal U0, the effect of the resistance of the shunt 121 can be ignored.
[0054] The short-circuit detection module 12 also includes a sixth resistor R6 and a first capacitor C1. The first power supply terminal of the third comparator 122 is connected to the fifth power supply voltage VCC5, such as 5V, and the second power supply terminal is connected to the sixth power supply voltage, such as the first ground potential GND1. The sixth resistor R6 is connected between the first power supply terminal and the output terminal of the third comparator 122, and the first capacitor C1 is connected between the output terminal and the second power supply terminal of the third comparator 122. The first input terminal of the third comparator 122 is a non-inverting input terminal and the second input terminal is an inverting input terminal, or the first input terminal of the third comparator 122 is an inverting input terminal and the second input terminal is a non-inverting input terminal.
[0055] This embodiment uses the first input terminal of the third comparator 122 as an inverting input terminal and the second input terminal as a non-inverting input terminal as an example to illustrate the principle. When a short circuit occurs in the bridge arm, the current in the branch where the bridge arm is located surges, causing the potential at the first terminal of the shunt 121 to increase. That is, the voltage at the first input terminal of the third comparator 122 increases, making the voltage at the first input terminal of the third comparator 122 greater than the voltage at the second input terminal of the third comparator 122. The third comparator 122 outputs a high potential. When the main control module 10 detects that the output terminal of the third comparator 122 has jumped from a low potential to a high potential, it determines that a short circuit has occurred in the bridge arm and controls the test signal to stop generating.
[0056] For any of the above embodiments, refer to Figure 2 Optionally, the voltage divider unit 111 includes a first resistor R1 and a second resistor R2; The first end of the first resistor R1 is connected to the first power supply voltage VCC1. The second end of the first resistor R1 is connected to the first end of the second resistor R2, the second terminal of the first transistor T1, and the comparator unit 112. The second end of the second resistor R2 is connected to the second power supply voltage.
[0057] The detection module 11 also includes a third resistor R3, a fourth resistor R4 and a fifth resistor R5 connected in series between the third power supply terminal and the fourth power supply terminal. The common terminal of the third resistor R3 and the fourth resistor R4 is connected to the second input terminal of the first comparator 1121, and is used to output the first reference voltage VF1. The common terminal of the fourth resistor R4 and the fifth resistor R5 is connected to the first input terminal of the second comparator 1122, and is used to output the second reference voltage VF2.
[0058] The first terminal of the third resistor R3 is connected to the third power supply terminal, and the voltage connected to the third power supply terminal can be equal to the first power supply voltage, such as 24V. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4, and the second terminal of the third resistor R3 is used to output the first reference voltage VF1. The second terminal of the fourth resistor R5 is connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the fourth power supply terminal, which can be connected to the first ground potential GND1. The second terminal of the fourth resistor R4 is used to output the second reference voltage VF2.
[0059] The first resistor R1 can be set to the same value as the second resistor R2, both set to 1KΩ. The first power supply voltage VCC1 and the voltage connected to the third power supply terminal are both 24V. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 are all set to 1KΩ. Therefore, the first reference voltage VF1 is 16V, the second reference voltage is 8V, and the first potential is 12V. In other embodiments, the first power supply voltage, the voltage connected to the third power supply terminal, and the resistance values of each resistor can be set to other values; no specific limitation is imposed.
[0060] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A detection circuit for a power board, the power board comprising a bridge arm, the bridge arm comprising a first transistor and a second transistor; characterized in that, include: The main control module and the detection module, wherein the detection module includes: a voltage divider unit and a comparison unit; The first terminal of the first transistor and the first terminal of the voltage divider unit are both connected to a first power supply voltage. The second terminal of the first transistor is connected to the voltage divider terminal of the voltage divider unit and the first terminal of the second transistor. The second terminal of the second transistor and the second terminal of the voltage divider unit are both connected to a second power supply voltage. When the voltage divider unit is not connected to the bridge arm, the voltage divider terminal has the first voltage. The comparison unit is connected to the voltage divider terminal of the voltage divider unit and is connected to a first reference voltage and a second reference voltage. The comparison unit is used to generate an output signal based on the relationship between the voltage at the voltage divider terminal and the first reference voltage, and the relationship between the voltage at the voltage divider terminal and the second reference voltage. The first reference voltage is less than the first power supply voltage and greater than the first voltage, and the second reference voltage is less than the first voltage and greater than the second power supply voltage. The bridge arm is used to control the on / off state of the first transistor and the second transistor in response to a test signal; each test signal corresponds to a target output signal; The main control module is connected to the comparison unit, and the main control module is used to determine whether the bridge arm has failed based on whether the output signal and the target output signal are consistent.
2. The detection circuit of the power board according to claim 1, characterized in that, The comparison unit includes a first comparator and a second comparator; The first input terminal of the first comparator is connected to the voltage divider terminal, the second input terminal of the first comparator is connected to the first reference voltage, and the output terminal of the first comparator is connected to the main control module. The first input terminal of the second comparator is connected to the second reference voltage, the second phase input terminal of the second comparator is connected to the voltage divider terminal, and the output terminal of the second comparator is connected to the main control module.
3. The detection circuit of the power board according to claim 2, characterized in that, The detection module further includes a first digital input unit and a second digital input unit; The input terminal of the first digital input unit is connected to the output terminal of the first comparator, and the output terminal of the first digital input unit is connected to the main control module. The first digital input unit is used to electrically isolate and level-convert the signal output from the output terminal of the first comparator and then input it to the main control module. The input terminal of the second digital input unit is connected to the output terminal of the second comparator, and the output terminal of the second digital input unit is connected to the main control module. The second digital input unit is used to electrically isolate and level-convert the signal output from the output terminal of the second comparator and then input it to the main control module.
4. The detection circuit of the power board according to claim 2, characterized in that, The detection module also includes a third resistor, a fourth resistor, and a fifth resistor connected in series between the third power terminal and the fourth power terminal. The common terminal connecting the third resistor and the fourth resistor is connected to the second input terminal of the first comparator, and is used to output the first reference voltage. The common terminal of the fourth resistor and the fifth resistor is connected to the first input terminal of the second comparator, and is used to output the second reference voltage; The voltage divider unit includes a first resistor and a second resistor; The first end of the first resistor is connected to the first power supply voltage, the second end of the first resistor is connected to the first end of the second resistor, the second terminal of the first transistor and the comparator unit, and the second end of the second resistor is connected to the second power supply voltage.
5. The detection circuit of the power board according to any one of claims 1-4, characterized in that, The test signal includes a first control signal and a second control signal. The first control signal is configured to control the on / off state of the first transistor in three stages, and the second control signal is configured to control the on / off state of the second transistor in three stages, the three stages including a first stage, a second stage and a third stage. In the first stage, the first control signal has a first turn-off potential, and the second control signal has a second turn-off potential; the first turn-off potential is a potential for controlling the first transistor to turn off, and the second turn-off potential is a potential for controlling the second transistor to turn off. In the second stage, the first control signal has a first turn-on potential and the second control signal has a second turn-off potential; the first turn-on potential is the potential that controls the first transistor to turn on; In the third stage, the first control signal has the first turn-off potential and the second control signal has the second turn-on potential; the second turn-on potential is the potential that controls the second transistor to turn on.
6. The detection circuit of the power board according to claim 5, characterized in that, The pulse frequency of the first control signal is equal to the pulse frequency of the second control signal; The power board is used to transmit a first working signal to the control terminal of the first transistor and a second working signal to the control terminal of the second transistor when driving the load to work. The pulse frequency of the first working signal is equal to the pulse frequency of the second working signal, and the pulse frequency of the first control signal is less than the pulse frequency of the first working signal.
7. The detection circuit of the power board according to claim 1, characterized in that, The power board also includes a slave control module, and the master control module is connected to the slave control module. The master control module is used to transmit detection trigger signals to the slave control module. The slave control module is used to send a test signal to the bridge arm after receiving the detection trigger signal.
8. The detection circuit of the power board according to claim 1, characterized in that, The power board includes at least one bridge arm, and the detection module is configured in a one-to-one correspondence with the bridge arm.
9. The detection circuit of the power board according to claim 1, characterized in that, It also includes a short-circuit detection module corresponding to the bridge arm, the short-circuit detection module being connected to the bridge arm, the short-circuit detection module being used to generate a short-circuit detection signal based on the short-circuit state of the bridge arm; the short-circuit state includes a short-circuit state and a short-circuit state. The main control module is connected to the short circuit detection module. The main control module is used to control the generation of the test signal when it is determined that no short circuit has occurred in the bridge arm based on the short circuit detection signal.
10. The detection circuit of the power board according to claim 9, characterized in that, The short-circuit detection module includes: a shunt and a third comparator; The first end of the current shunt is connected to the second terminal of the second transistor, and the second end of the current shunt is connected to the second end of the voltage divider unit; The first input terminal of the third comparator is connected to the first terminal of the shunt, the second input terminal of the third comparator is connected to the third reference voltage, and the output terminal of the third comparator is connected to the main control module.