A pipeline flush recovery method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a pipeline flush recovery method and device, electronic equipment and storage medium. By distinguishing the recovery stage and the resource release stage in the pipeline flush recovery process, and setting an independent renaming record queue write control mechanism, the error path resource release and the new instruction execution after the flush can be performed in parallel, thereby avoiding the problem that in the prior art, the processor front end must wait for all the recovery to be completed before restarting, and thus the pause time caused by the pipeline flush can be effectively shortened, the performance loss can be reduced, and the execution efficiency and resource utilization of the high-performance out-of-order processor core can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of processor microarchitecture design technology, and more specifically, to a pipeline flushing recovery method, apparatus, electronic device, and storage medium. Background Technology

[0002] To enhance instruction-level parallelism, high-performance processors typically employ out-of-order execution architectures. In this architecture, the processor front-end fetches and decodes instructions sequentially, while the back-end combines mechanisms such as register renaming, out-of-order scheduling, speculative execution, and commit control to enable multiple instructions to proceed in parallel across different execution units, thereby improving overall throughput. The register renaming mechanism typically maintains renaming mappings to map architectural registers to physical registers, eliminating spurious dependencies and supporting out-of-order instruction execution. Furthermore, to enable state rollback in speculative scenarios such as branch prediction and exception handling, the processor also includes renaming record queues, recovery mapping tables, or similar state recording structures to store mapping changes during speculative execution.

[0003] During out-of-order processor operation, when branch prediction errors, exception triggers, or invalidated instructions on erroneous paths occur, the processor typically needs to perform a pipeline flush. Pipeline flushing refers to clearing instructions that have entered the pipeline but belong to erroneous execution paths and restoring the processor state to the historical state corresponding to the correct execution path. However, existing pipeline flush recovery mechanisms usually employ a conservative serial recovery approach, maintaining a processor pause throughout the recovery process until the speculative state rollback and all erroneous path resources are released before restarting front-end instruction fetching, renaming, and subsequent execution. While this approach is relatively straightforward, it prevents the front-end and back-end of the processor from working effectively in parallel during pipeline flush recovery, resulting in significant performance cavitation. This performance penalty is particularly pronounced in scenarios with frequent branch jumps, complex control flows, or high speculative depths. Summary of the Invention

[0004] This disclosure provides at least one method, apparatus, electronic device, and storage medium for pipeline flushing recovery. By distinguishing between the recovery phase and the resource release phase during the pipeline flushing recovery process, and by setting an independent rename record queue write control mechanism, the resource release of the erroneous path and the execution of new instructions after flushing can be carried out in parallel. This avoids the problem in the prior art that the processor front end must wait for all recovery to be completed before it can be restarted. As a result, the pause time caused by pipeline flushing can be effectively shortened, performance loss can be reduced, and the execution efficiency and resource utilization of high-performance out-of-order processor cores can be improved.

[0005] This disclosure provides a pipeline flushing recovery method applied to an out-of-order processor including a rename record queue, wherein the rename record queue is provided with a read pointer, a first write pointer, and a second write pointer, and the method includes:

[0006] When a pipeline flushing event is detected, the flushing recovery start point corresponding to the read pointer at the time of the event is recorded, and the read pointer is controlled to start reading the rename record information from the flushing recovery start point, and the speculative rename mapping table is restored according to the rename record information;

[0007] When the speculative renaming mapping table is restored, the branch prediction failure point corresponding to the current read pointer is recorded to indicate the end of the recovery phase and the start of the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the renaming record information corresponding to the new instruction.

[0008] During the resource release phase, the read pointer is controlled to continue reading the rename record information in the rename record queue, and the processor is controlled to end the pause and respond to new instructions based on the positional relationship between the second write pointer and the read pointer.

[0009] When the read pointer reaches the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer.

[0010] In one optional implementation, when a pipeline flushing event is detected, the flushing recovery starting point corresponding to the read pointer at the time of the event is recorded, and the read pointer is controlled to read renaming record information starting from the flushing recovery starting point. The speculative renaming mapping table is then restored based on the renaming record information. Specifically, this includes:

[0011] The position of the read pointer when pipeline flushing occurs is stored in the first register, which serves as the starting point for flushing recovery.

[0012] The rename record information in the rename record queue is read sequentially by the read pointer, and the speculative rename mapping table is rolled back and restored based on the read rename record information so that the processor can return to the correct execution path.

[0013] In one optional implementation, when the speculative renaming mapping table recovery is complete, the branch prediction failure point currently corresponding to the read pointer is recorded to indicate the end of the recovery phase and entry into the resource release phase. Upon entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the renaming record information corresponding to the new instruction. Specifically, this includes:

[0014] When the speculative renaming mapping table is restored, the position of the read pointer at the current moment is stored in the second register as the branch prediction failure point.

[0015] At the start of the resource release phase, based on the branch prediction failure point location information stored in the second register, the second write pointer is moved to the position corresponding to the branch prediction failure point, and the renaming mapping data of the new instruction is stored based on the second write pointer.

[0016] In one optional implementation, during the resource release phase, controlling the read pointer to continue reading rename record information in the rename record queue specifically includes:

[0017] During the resource release phase, the rename record information after the branch prediction failure point is read sequentially using the read pointer.

[0018] Modify the physical register file state machine according to the renaming record information to release physical register resources occupied by the faulty path instruction.

[0019] In one optional implementation, the processor is controlled to end the pause and respond to a new instruction based on the positional relationship between the second write pointer and the read pointer, specifically including:

[0020] During the recovery phase, the processor pause enable signal is unconditionally pulled high to prevent the processor from responding to new instructions;

[0021] When in the resource release phase, the processor pause enable signal is conditionally disabled based on the positional relationship between the second write pointer and the read pointer.

[0022] In one optional implementation, the processor pause enable signal is conditionally deactivated based on the positional relationship between the second write pointer and the read pointer, specifically including:

[0023] When the second write pointer is greater than or equal to the read pointer, it is determined that the current processor resources are insufficient, and the processor is kept in a standby state.

[0024] When the second write pointer is less than the read pointer, it is determined that the current processor resources meet the conditions for executing the new instruction, and the processor is controlled to end the pause to respond to the new instruction.

[0025] In one optional implementation, when the read pointer reaches the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer, specifically including:

[0026] When the read pointer reaches the position corresponding to the first write pointer, it is determined that both the recovery phase and the resource release phase have ended.

[0027] After the pipeline flushing recovery is completed, the position of the read pointer is restored by the flushing recovery start point information recorded in the first register.

[0028] Move the first write pointer to the position corresponding to the second write pointer to restore the position of the latest written data.

[0029] This disclosure also provides a pipeline flushing recovery device applied to an out-of-order processor including a rename record queue, wherein the rename record queue is provided with a read pointer, a first write pointer, and a second write pointer, and the device includes:

[0030] The event detection module is used to record the flush recovery start point corresponding to the read pointer when the flush event occurs, and control the read pointer to read the rename record information from the flush recovery start point, and restore the speculative rename mapping table according to the rename record information when the flush event is detected.

[0031] The rename record writing module is used to record the branch prediction failure point currently corresponding to the read pointer when the speculative rename mapping table is restored, so as to indicate the end of the recovery phase and the entry into the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the rename record information corresponding to the new instruction.

[0032] The pointer position detection module is used to control the read pointer to continue reading the rename record information in the rename record queue during the resource release phase, and to control whether the processor ends the pause and responds to new instructions according to the positional relationship between the second write pointer and the read pointer.

[0033] The pointer position update module is used to determine that the pipeline flushing recovery is complete when the read pointer reads the position corresponding to the first write pointer, and update the first write pointer to the position corresponding to the second write pointer.

[0034] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the above-described pipeline flushing recovery method, or any possible implementation of the above-described pipeline flushing recovery method, are performed.

[0035] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described pipeline flushing recovery method, or any possible implementation of the above-described pipeline flushing recovery method.

[0036] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implements the above-described pipeline flushing recovery method, or the steps in any possible implementation of the above-described pipeline flushing recovery method.

[0037] This disclosure provides a pipeline flushing recovery method, apparatus, electronic device, and storage medium. By distinguishing between the recovery phase and the resource release phase during the pipeline flushing recovery process, and by setting an independent rename record queue write control mechanism, the resource release of the erroneous path and the execution of new instructions after flushing can be carried out in parallel. This avoids the problem in the prior art that the processor front end must wait for the entire recovery to be completed before it can be restarted. As a result, it can effectively shorten the pause time caused by pipeline flushing, reduce performance loss, and improve the execution efficiency and resource utilization of high-performance out-of-order processor cores.

[0038] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a method for restoring the scouring of a production line according to an embodiment of this disclosure is shown;

[0041] Figure 2 A schematic diagram of a process for restoring a production line flushing system, provided in an embodiment of this disclosure, is shown.

[0042] Figure 3 This diagram illustrates a pause enable signal for a pipeline flushing process processor provided in an embodiment of the present disclosure.

[0043] Figure 4A schematic diagram of a recovery device for automated flushing provided in an embodiment of this disclosure is shown;

[0044] Figure 5 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0046] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0047] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0048] Research has revealed that existing pipeline flush recovery mechanisms typically employ a conservative, serial recovery approach. This involves maintaining a processor pause throughout the recovery process, waiting for the speculative state to roll back and all erroneous path resources to be released before restarting the front-end instruction fetching, renaming, and subsequent execution flows. While this approach is relatively straightforward, it prevents the processor's front-end and back-end from working effectively in parallel during pipeline flush recovery, resulting in significant performance cavitation. This performance loss caused by pipeline flushing is particularly pronounced in scenarios with frequent branch jumps, complex control flows, or high speculative depths.

[0049] Based on the above research, this disclosure provides a pipeline flushing recovery method, apparatus, electronic device, and storage medium. By distinguishing between the recovery phase and the resource release phase during the pipeline flushing recovery process, and by setting an independent rename record queue write control mechanism, the resource release of the erroneous path and the execution of new instructions after flushing can be carried out in parallel. This avoids the problem in the prior art that the processor front end must wait for the entire recovery to be completed before it can be restarted. As a result, the pause time caused by pipeline flushing can be effectively shortened, performance loss can be reduced, and the execution efficiency and resource utilization of high-performance out-of-order processor cores can be improved.

[0050] To facilitate understanding of this embodiment, a pipeline flushing recovery method disclosed in this disclosure will first be described in detail. The execution entity of the pipeline flushing recovery method provided in this disclosure is generally a computer device with certain computing capabilities. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, the pipeline flushing recovery method can be implemented by a processor calling computer-readable instructions stored in memory.

[0051] In practical implementation, the recovery method for high-performance out-of-order processor cores after pipeline flushing provided in this embodiment is applied to out-of-order processors including a rename record queue. The out-of-order processor can be a high-performance processor core that supports register renaming, out-of-order scheduling, speculative execution, and sequential commit. During operation, this out-of-order processor can process instructions in parallel through front-end fetch, decode, rename, issue, execute, and commit processes to improve instruction-level parallelism and overall processing performance. In this type of processor, to support the recording of mapping relationships during register renaming and to restore the execution state in case of branch prediction errors, exception triggering, or faulty path instruction failure, a rename record queue is typically set up to store relevant record information generated during the instruction renaming phase.

[0052] In this embodiment, the rename record queue is equipped with a read pointer, a first write pointer, and a second write pointer. The read pointer is used to read historical rename record information in the rename record queue during pipeline flush recovery to perform speculative state recovery or release of resources on faulty paths. The first write pointer is used to characterize the current write position in the rename record queue under normal instruction execution flow to support the writing of rename records for newly entered instructions under normal circumstances. The second write pointer is an additional write position control pointer set in the pipeline flush recovery scenario. It is used to allocate new rename record write positions for newly entered instructions after flushing during flush recovery, so that the historical record reading process for faulty paths and the new record writing process for correct paths can be performed in parallel in the rename record queue.

[0053] It is understood that the read pointer, the first write pointer, and the second write pointer all correspond to position identifier information in the rename record queue. The position identifier information can be implemented using a queue index, address offset, entry number, or other methods that can characterize the queue access position; this embodiment does not limit this. The rename record queue can be a first-in, first-out queue, or other record structures with sequential recording and position-based access capabilities. As long as it can meet the storage, reading, and recovery control requirements of the rename record information, it is applicable to the technical solution of this application.

[0054] It should be noted that the read pointer position corresponds to the commit point of the previous clock cycle, which is also the pipeline flushing start point.

[0055] Here, under normal instruction execution, the first write pointer can be used to indicate the write position of the rename record corresponding to the new instruction, and the read pointer can be used to read the historical record when needed in conjunction with the processor's internal recovery control logic. When the processor detects a pipeline flush event, the second write pointer participates in the flush recovery control, enabling the processor to provide an independent record write position for new instructions on the correct path after the flush while performing error path recovery and resource release.

[0056] In some embodiments, the out-of-order processor may further include functional modules such as a speculative rename mapping table, a physical register file status management unit, a branch prediction unit, a commit control unit, and a pipeline pause control unit. The speculative rename mapping table records the register mapping relationships in the current speculative execution state; the physical register file status management unit identifies the allocation, occupancy, and release states of each physical register; and the pipeline pause control unit controls whether the processor allows new instructions to continue entering the processing flow during pipeline flush recovery. The rename record queue, along with the read pointer, the first write pointer, and the second write pointer, works in conjunction with the aforementioned functional modules to complete the recovery control after pipeline flushing.

[0057] It should be noted that the technical solution of this embodiment is not limited to the specific microarchitecture of the out-of-order processor. For example, the out-of-order processor can be a high-performance core in a general-purpose central processing unit, or it can be an out-of-order execution processor core designed for dedicated computing scenarios; it can be applied to single-issue, multi-issue, superscalar, or deep pipelined processor architectures. As long as the processor internally adopts a renaming information recording and recovery mechanism based on a renaming record queue, and there are state recovery and resource release requirements in pipeline flushing scenarios, the technical solution described in this application can be adopted.

[0058] See Figures 1-2 As shown, Figure 1 This is a flowchart illustrating a method for restoring the erosion performance of a production line, as provided in an embodiment of this disclosure. Figure 2 This diagram illustrates a process flow chart for restoring line flushing according to an embodiment of the present disclosure, the method comprising steps S101 to S104:

[0059] S101. When a pipeline flushing event is detected, the flushing recovery starting point corresponding to the read pointer at the time of the event is recorded, and the read pointer is controlled to start reading the renaming record information from the flushing recovery starting point, and the speculative renaming mapping table is restored according to the renaming record information.

[0060] In practical implementation, when the out-of-order processor detects a pipeline flushing event, it first records the queue position corresponding to the read pointer at the time of the event, which serves as the starting point for the pipeline flushing recovery process. The pipeline flushing event can be a branch prediction failure event, an exception triggering event, an interrupt-induced control flow redirection event, or other events that cause the current speculative execution path to fail and require a rollback of the processor state. This embodiment does not limit this; as long as the event triggers the clearing of erroneous path instructions and the recovery of the processor's speculative state, the technical solution of this application is applicable.

[0061] Specifically, when a pipeline flush event occurs, the processor's internal recovery control logic can latch the current read pointer position to save the historical record read start position corresponding to the moment the flush occurred. The recorded flush recovery start point can be understood as the starting boundary where the read pointer begins to execute backtracking reads during this recovery process, used to identify the range of renamed records that need to participate in this speculative state recovery.

[0062] Furthermore, after recording the flush recovery start point, the control read pointer reads the rename record information in the rename record queue starting from the flush recovery start point. The rename record information may include mapping change information generated by the instruction during the register renaming stage, old physical register identification information, new physical register allocation information, target architecture register identification information, and other record content that can characterize changes in renaming relationships.

[0063] It should be noted that this embodiment does not limit the specific field organization of the renamed record information, as long as it can support the restoration of the mapping relationship in the pipeline flushing scenario.

[0064] Here, during the reading process, the read pointer can read the rename record information in the corresponding table entry one by one according to the preset queue access direction, and send the read record information to the recovery control logic. The recovery control logic restores the speculative rename mapping table based on the rename record information.

[0065] Specifically, during the normal execution of an out-of-order processor, the speculative rename mapping table is continuously updated as new instructions enter the renaming stage, recording the mapping relationships between architectural registers and physical registers under the current speculative path. When a pipeline flush event occurs, this speculative rename mapping table may already contain the mapping results corresponding to the erroneous execution path. If it is not restored, the register addressing and data dependencies of subsequent correct path instructions will be incorrect. Therefore, it is necessary to perform a rollback restoration of the speculative rename mapping table based on the historical rename record information stored in the rename record queue.

[0066] In some implementations, the process of restoring the speculative rename mapping table can be manifested as follows: for each rename record currently read by the read pointer, determine the target architecture register corresponding to the record and the historical physical register mapping relationship of the target architecture register before the mapping change, and use the historical physical register mapping relationship to rewrite the corresponding item in the current speculative rename mapping table, thereby gradually undoing the mapping update on the erroneous execution path.

[0067] As the read pointer continuously reads the relevant records in the rename record queue, the speculative rename mapping table gradually reverts from the speculative mapping state under the wrong path to the correct path starting state corresponding to the flush event.

[0068] Furthermore, the process of reading rename record information based on the read pointer and restoring the speculative rename mapping table can be uniformly scheduled by a dedicated recovery state machine under recovery control. Upon detecting a pipeline flushing event, the recovery state machine can output a read control signal to the read pointer and an entry recovery control signal to the speculative rename mapping table to coordinate the record reading and mapping rollback operations.

[0069] This allows for a stable timing coordination between rename record queue access and speculative rename mapping table recovery, improving the reliability and feasibility of the recovery process.

[0070] S102. When the speculative renaming mapping table is restored, the branch prediction failure point corresponding to the current read pointer is recorded to indicate the end of the restoration phase and the start of the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the renaming record information corresponding to the new instruction.

[0071] In practice, the read pointer sequentially reads the rename record information in the rename record queue from the flush recovery starting point, and performs a rollback recovery of the speculative rename mapping table based on the rename record information. When the speculative rename mapping table recovery is complete, the queue position corresponding to the read pointer at the current moment is recorded as the branch prediction failure point. The branch prediction failure point is used to characterize the end position of the recovery phase in this pipeline flush recovery process, and also serves as the boundary reference position for the subsequent resource release phase and the rewriting of the new instruction rename record.

[0072] Understandably, the recovery phase is primarily used to undo the mapping updates caused by the erroneous execution path to the speculative renaming table, restoring the processor's register renaming state to the state corresponding to the correct execution path. When the read pointer reaches the position where the speculative renaming table recovery is complete, it indicates that the recovery task related to the register mapping rollback has been completed, and the processor now has the basic conditions to re-establish the correct path instruction renaming relationship. However, at this moment, the physical register resources, record queue entries, or other speculative resources occupied by the erroneous execution path may not have been completely released, so a subsequent resource release phase is still needed to continue cleaning up the erroneous path resources.

[0073] In some implementations, branch prediction failure points can be stored in dedicated registers. For example, when the recovery control logic detects that the speculative rename mapping table has been fully restored, it can latch the current position of the read pointer into a second register to form the branch prediction failure point location information. Subsequent resource release control logic and new instruction rename write control logic can determine their respective operation boundaries based on this branch prediction failure point location information.

[0074] Furthermore, after recording the branch prediction failure point, the characterization recovery phase ends and the resource release phase begins. The resource release phase is mainly used to continue processing the resource occupancy issues left over from the erroneous execution path.

[0075] Specifically, in this stage, the read pointer no longer needs to undertake the rollback and recovery task of the speculative rename mapping table. Instead, it continues to read subsequent related records along the rename record queue to cooperate with modules such as physical register state management logic and resource reclamation logic to release the processor resources occupied by the erroneous path instructions.

[0076] Therefore, this embodiment divides the post-flushing processing into two distinct phases: a recovery phase and a resource release phase. The recovery phase focuses on restoring the renamed state, while the resource release phase focuses on cleaning up resources along erroneous paths. This phased control approach facilitates parallel coordination between the recovery process and the new instruction entry process.

[0077] Furthermore, upon entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the rename record information corresponding to the new instruction. In other words, this embodiment does not continue to directly use the first write pointer in the normal execution state as the write control position for the new instruction after flushing, but introduces an independent second write pointer in the pipeline flushing recovery scenario, and makes the second write pointer use the branch prediction failure point as the new starting write position.

[0078] The reason for this setting is that the position corresponding to the branch prediction failure point can be regarded as the starting point for the new rename record to be re-established after the correct execution path is recovered. After the second write pointer is moved to this position, the new instructions on the subsequent correct path can be rewritten from this position to the corresponding rename record information, thus distinguishing it from the subsequent reading and release process of the error path history.

[0079] In a specific implementation, when the processor front end allows some or all new instructions to re-enter the renaming process again during the resource release phase, the renaming unit can write the mapping change information generated by these new instructions during the renaming process into the renaming record queue entry indicated by the second write pointer, and push the second write pointer forward to update after each write is completed.

[0080] Correspondingly, the read pointer can continue to read the historical rename records corresponding to the erroneous execution path along the original recovery path to perform resource release operations. Thus, in the same rename record queue, the old record read-release path controlled by the read pointer and the new record rewrite path controlled by the second write pointer can coexist in parallel, thereby providing a basis for the parallel execution of erroneous path resource cleanup and correct path new instruction entry during pipeline flushing and recovery.

[0081] It should be noted that moving the second write pointer to the position corresponding to the branch prediction failure point does not mean that all historical records corresponding to the erroneous path have been immediately overwritten at that moment. Rather, it means that logically, this position is determined as the starting write boundary for the new record of the correct path after flushing. Whether the processor is allowed to respond to the new instruction immediately and how fast the new record is written can be further determined by combining the positional relationship between the second write pointer and the read pointer to avoid conflicts between the newly written record and the old record that has not yet been read and released.

[0082] S103. During the resource release phase, the read pointer is controlled to continue reading the rename record information in the rename record queue, and the processor is controlled to end the pause and respond to new instructions based on the positional relationship between the second write pointer and the read pointer.

[0083] In practice, after entering the resource release phase, the control read pointer continues to read the rename record information in the rename record queue to continue the release operation of the resources corresponding to the instructions on the erroneous path. At this time, unlike the aforementioned recovery phase, the main purpose of the read pointer continuing to read the rename record information is no longer to restore the speculative rename mapping table, but to gradually reclaim the processor resources occupied by the erroneous path based on the record content formed by each instruction on the erroneous execution path during the rename phase.

[0084] Specifically, during speculative execution in an out-of-order processor, although instructions on the erroneous path are not ultimately committed, they typically consume some internal processor resources when entering pipeline stages such as renaming, scheduling, and execution. These resources include physical register resources, rename record queue entries, and other auxiliary control resources related to the speculative state. After pipeline flushing and restoration of the speculative rename mapping table, these erroneous path resources are not automatically released. Instead, they need to be cleared item by item by the resource release control logic based on the historical rename record information stored in the rename record queue.

[0085] In some implementations, during the resource release phase, the read pointer can continue reading rename record information sequentially in a predetermined direction after the branch prediction failure point. For each rename record currently read by the read pointer, the processor's internal resource state management logic can determine whether the corresponding resource belongs to the wrong path based on the target architecture register identifier, old physical register identifier, new physical register identifier, or other resource allocation flags contained in the record. When it is confirmed that the resource is no longer dependent on the correct path, the corresponding resource state is modified to a releaseable state or an idle state.

[0086] Taking physical register resources as an example, the resource release control logic can update the physical register file state machine according to the renaming record information to cancel the occupation mark of the corresponding physical register by the erroneous path instruction, so that the released physical register can re-participate in the register allocation of subsequent correct path instructions.

[0087] Meanwhile, in this embodiment, whether the processor ends the pause and responds to new instructions during the resource release phase is not fixed and waits for all erroneous path resources to be released before starting uniformly, but is dynamically controlled according to the positional relationship between the second write pointer and the read pointer.

[0088] In other words, this embodiment determines whether there is enough safe writable space in the current rename record queue by comparing the relative relationship between the new instruction write advance position and the old error path record release advance position, and further decides whether to allow the processor to resume responding to the new instruction.

[0089] Specifically, the second write pointer represents the current write position of the rename record information corresponding to the new instruction during the resource release phase, while the read pointer represents the current read and release position of the historical rename record of the error path. Since the new write process indicated by the second write pointer and the old record release process corresponding to the read pointer proceed in parallel within the same rename record queue, the positional relationship between the two can directly reflect the current resource occupancy and release status of the queue.

[0090] Here, when the second write pointer continues to advance while the read pointer's release speed is insufficient, it indicates that the newly entered instruction may be approaching an old record area that has not yet been released. If the processor continues to unconditionally accept new instructions at this time, it may lead to access conflicts between old and new records, queue space overwrite errors, or disordered recovery states. Conversely, when the read pointer has released enough space to keep the second write pointer within the safe write range, it indicates that the current processor resources are sufficient to support some or all of the new instructions re-entering the processing flow.

[0091] In some implementations, see Figure 3The diagram illustrates a processor pause enable signal for a pipeline flushing process according to an embodiment of this disclosure. The pause state of the processor can be controlled based on the relationship between the second write pointer and the read pointer. When the second write pointer is greater than or equal to the read pointer, it can be determined that the current new record write advance position has caught up with or is close to the old record release position, indicating that the current processor resources are still insufficient. At this time, the processor is controlled to remain in a pause state, prohibiting new instructions from continuing to enter the renaming process. When the second write pointer is less than the read pointer, it can be determined that the current read pointer has released enough space in the queue, indicating that the current processor resources meet the conditions for the new instruction to continue execution. At this time, the processor can be controlled to end the pause and allow new instructions to re-enter the front-end fetch, decode, and renaming processing flow.

[0092] It is understandable that the control method based on the positional relationship between the second write pointer and the read pointer essentially transforms the resource release progress directly into the processor pause release condition, so that the pause control no longer depends on a fixed duration or waiting for the entire recovery process to be completely finished, but can be dynamically adjusted according to the actual progress of resource release.

[0093] In this way, as soon as the error path resources are released enough space to support the writing and execution of some new instructions, the processor can resume responding to the new instructions in advance, without having to wait for all error path records to be processed. As a result, the processor front-end's processing of new instructions on the correct path and the back-end's release of error path history records can be carried out in parallel within the limits of available resources, thereby significantly reducing the overall downtime caused by pipeline flushing.

[0094] Furthermore, in the specific circuit implementation, the aforementioned positional relationship determination can be jointly accomplished by the pause control unit, the recovery state machine, or the queue management logic. The comparison logic can receive the current positions of the second write pointer and the read pointer in real time and output the corresponding pause control signal. When the comparison result meets the preset pause release condition, the pause control signal becomes invalid, and the processor front end restarts new instruction input; when the comparison result does not meet the pause release condition, the pause control signal remains valid, and the processor continues to maintain the paused state. In this way, the safety of error path release can be ensured while improving the processor recovery efficiency after pipeline flushing.

[0095] In this way, during the resource release phase, the read pointer continues to read the rename record information in the rename record queue, and the processor ends the pause and responds to new instructions based on the positional relationship between the second write pointer and the read pointer. This allows the resource release process of the erroneous path and the new instruction entry process of the correct path to proceed in a coordinated manner under a unified queue control framework. This not only ensures the correctness of pipeline flushing recovery, but also reduces the long pauses caused by traditional serial recovery methods, thereby effectively improving the execution efficiency and resource utilization of out-of-order processors in pipeline flushing scenarios.

[0096] S104. When the read pointer reads to the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer.

[0097] In practice, when the read pointer continuously reads the rename record information in the rename record queue during the resource release phase and finally reads to the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete.

[0098] Here, the first write pointer represents the latest write boundary of the rename record queue in normal execution before the pipeline flush occurs. Therefore, when the read pointer advances to this position, it means that all historical rename records written to the rename record queue before this pipeline flush, and which fall within the scope of error execution path processing, have been read and processed. In other words, reaching the position corresponding to the first write pointer means that all old records that need to be processed in this recovery process have been accessed, and the corresponding speculative state recovery and error path resource release tasks are also completed.

[0099] Understandably, in this embodiment, the read pointer advances from the flush recovery starting point, successively experiencing a recovery phase and a resource release phase. During the recovery phase, the rename records read by the read pointer are primarily used to restore the speculative rename mapping table; during the resource release phase, the read pointer continues to read subsequent rename records, mainly used to release physical registers and other processor resources occupied by erroneous path instructions. Therefore, when the read pointer finally catches up to the old write boundary indicated by the first write pointer, it can be considered that all old path records related to this pipeline flush have been processed, and the historical content of the rename record queue belonging to the erroneous path before the flush no longer needs to participate in the recovery control.

[0100] In some implementations, the processor's internal recovery state machine or queue management control logic can compare the positions of the read pointer and the first write pointer in real time. When the read pointer is detected to have reached the position corresponding to the first write pointer, a recovery completion flag signal is output. This recovery completion flag signal can be used to trigger subsequent state cleanup operations, such as ending the current recovery control state, canceling dedicated control signals related to this flush recovery, restoring the normal queue read / write management mode, and performing write pointer merging operations.

[0101] Furthermore, after confirming that the pipeline flush recovery is complete, the first write pointer is updated to the position corresponding to the second write pointer. Specifically, the second write pointer is used to represent the actual write progress position of the rename record corresponding to the new instruction after flushing during the pipeline flush recovery process, while the first write pointer is the write control pointer used to represent the current write boundary of the rename record queue in the normal execution state.

[0102] Here, during the pipeline flush recovery, because the second write pointer in this embodiment takes on the task of writing new instructions, the first write pointer does not directly reflect the latest new record write boundary during this period. Only after the entire pipeline flush recovery is completed does it need to be switched from the first write pointer to the position currently corresponding to the second write pointer, so that the renamed record queue returns to the normal single write boundary management mode.

[0103] Furthermore, updating the first write pointer to the position corresponding to the second write pointer can be understood as formally confirming the new write result maintained by the second write pointer during the pipeline flush recovery process as the latest valid write boundary of the current rename record queue. In this way, after the recovery is completed, subsequent new instructions entering the processor can continue to write rename records based on the updated first write pointer, without needing to distinguish whether it is in a flush recovery scenario.

[0104] It should be noted that after the first write pointer is updated to the corresponding position of the second write pointer, the second write pointer can exit the current recovery control flow or be retained as a backup write pointer to participate in control again when the next pipeline flush event is triggered. Its specific reset method, retention method, or reuse method can be set according to the specific hardware implementation of the processor, and this embodiment does not limit this. As long as the first write pointer accurately reflects the latest valid write position after recovery and ensures that the subsequent rename record write process proceeds normally, it falls within the protection scope of this application's technical solution.

[0105] In this way, when the read pointer reaches the position corresponding to the first write pointer, it is determined that the pipeline flush recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer. The timing of the recovery end can be accurately determined based on the completion of the processing of old records in the queue. At the same time, the write boundaries of new records formed during the recovery period are uniformly merged into the normal write control path, thereby ensuring that the pipeline flush recovery process has clear termination conditions and a stable state convergence process, further improving the control reliability and execution continuity of the out-of-order processor in the flush recovery scenario.

[0106] This disclosure provides a pipeline flushing recovery method that distinguishes between the recovery phase and the resource release phase during the pipeline flushing recovery process. By setting an independent rename record queue write control mechanism, the resource release of the erroneous path and the execution of new instructions after flushing can be carried out in parallel. This avoids the problem in the prior art that the processor front end must wait for the entire recovery to be completed before it can be restarted. As a result, it can effectively shorten the pause time caused by pipeline flushing, reduce performance loss, and improve the execution efficiency and resource utilization of high-performance out-of-order processor cores.

[0107] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0108] Based on the same inventive concept, this disclosure also provides a device for restoring the flushing of a production line, which corresponds to the method for restoring the flushing of a production line. Since the principle of the device in this disclosure is similar to the above-mentioned method for restoring the flushing of a production line, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0109] Please see Figure 4 , Figure 4 This is a schematic diagram of a recovery device for automated flushing provided in an embodiment of this disclosure. Figure 4 As shown in the illustration, the pipeline flushing recovery device 400 provided in this embodiment is applied to an out-of-order processor including a rename record queue, wherein the rename record queue is provided with a read pointer, a first write pointer, and a second write pointer, and includes:

[0110] The event detection module 410 is used to record the flush recovery start point corresponding to the event when the flow line flushing event is detected, and to control the read pointer to read the renaming record information from the flush recovery start point, and to restore the speculative renaming mapping table according to the renaming record information.

[0111] The rename record writing module 420 is used to record the branch prediction failure point currently corresponding to the read pointer when the speculative rename mapping table is restored, so as to indicate the end of the recovery phase and the entry into the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the rename record information corresponding to the new instruction.

[0112] The pointer position detection module 430 is used to control the read pointer to continue reading the rename record information in the rename record queue during the resource release phase, and to control whether the processor ends the pause and responds to new instructions according to the positional relationship between the second write pointer and the read pointer.

[0113] The pointer position update module 440 is used to determine that the pipeline flushing recovery is complete when the read pointer reads the position corresponding to the first write pointer, and update the first write pointer to the position corresponding to the second write pointer.

[0114] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0115] This disclosure provides a pipeline flushing recovery device that distinguishes between the recovery phase and the resource release phase during the pipeline flushing recovery process. By setting an independent rename record queue write control mechanism, it enables the release of erroneous path resources and the execution of new instructions after flushing to proceed in parallel. This avoids the problem in the prior art where the processor front end must wait for all recovery to be completed before it can be restarted. As a result, it can effectively shorten the pause time caused by pipeline flushing, reduce performance loss, and improve the execution efficiency and resource utilization of high-performance out-of-order processor cores.

[0116] Corresponding to Figure 1 In addition to the method for restoring the erosion caused by the assembly line flushing, this disclosure also provides an electronic device 500, such as... Figure 5 The diagram shown is a structural schematic of an electronic device 500 provided in an embodiment of this disclosure, including:

[0117] Processor 51, memory 52, and bus 53; memory 52 is used to store execution instructions, including main memory 521 and external memory 522; the main memory 521, also called internal memory, is used to temporarily store the computational data in processor 51, as well as the data exchanged with external memory 522 such as hard disk. Processor 51 exchanges data with external memory 522 through main memory 521. When the electronic device 500 is running, processor 51 and memory 52 communicate through bus 53, enabling processor 51 to execute... Figure 1 The steps of the recovery method for the flushing of the production line.

[0118] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the pipeline flushing recovery method described in the above-described method embodiments. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0119] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the pipeline flushing recovery method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0120] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0121] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0122] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0124] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0125] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for restoring the condition of a production line after flushing, characterized in that, A method applied to an out-of-order processor including a rename record queue, wherein the rename record queue is configured with a read pointer, a first write pointer, and a second write pointer, the method comprising: When a pipeline flushing event is detected, the flushing recovery start point corresponding to the read pointer at the time of the event is recorded, and the read pointer is controlled to start reading the rename record information from the flushing recovery start point, and the speculative rename mapping table is restored according to the rename record information; When the speculative renaming mapping table is restored, the branch prediction failure point corresponding to the current read pointer is recorded to indicate the end of the recovery phase and the start of the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the renaming record information corresponding to the new instruction. During the resource release phase, the read pointer is controlled to continue reading the rename record information in the rename record queue, and the processor is controlled to end the pause and respond to new instructions based on the positional relationship between the second write pointer and the read pointer. When the read pointer reads to the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer. The first write pointer is used to characterize the latest write boundary of the rename record queue in normal execution state before the pipeline flushing occurs. Based on the positional relationship between the second write pointer and the read pointer, control whether the processor ends the pause and responds to new instructions, specifically including: During the recovery phase, the processor pause enable signal is unconditionally pulled high to prevent the processor from responding to new instructions; When in the resource release phase, the processor pause enable signal is conditionally disabled based on the positional relationship between the second write pointer and the read pointer. Based on the positional relationship between the second write pointer and the read pointer, the processor pause enable signal is conditionally deactivated, specifically including: When the second write pointer is greater than or equal to the read pointer, it is determined that the current processor resources are insufficient, and the processor is kept in a standby state. When the second write pointer is less than the read pointer, it is determined that the current processor resources meet the conditions for executing the new instruction, and the processor is controlled to end the pause to respond to the new instruction.

2. The method according to claim 1, characterized in that, When a pipeline flushing event is detected, the flushing recovery starting point corresponding to the read pointer at the time of the event is recorded, and the read pointer is controlled to start reading renaming record information from the flushing recovery starting point. The speculative renaming mapping table is then restored based on the renaming record information, specifically including: The position of the read pointer when pipeline flushing occurs is stored in the first register, which serves as the starting point for flushing recovery. The rename record information in the rename record queue is read sequentially by the read pointer, and the speculative rename mapping table is rolled back and restored based on the read rename record information so that the processor can return to the correct execution path.

3. The method according to claim 1, characterized in that, When the speculative renaming mapping table recovery is complete, the branch prediction failure point corresponding to the current read pointer is recorded to indicate the end of the recovery phase and the start of the resource release phase. Upon entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the renaming record information corresponding to the new instruction, specifically including: When the speculative renaming mapping table is restored, the position of the read pointer at the current moment is stored in the second register as the branch prediction failure point. At the start of the resource release phase, based on the branch prediction failure point location information stored in the second register, the second write pointer is moved to the position corresponding to the branch prediction failure point, and the renaming mapping data of the new instruction is stored based on the second write pointer.

4. The method according to claim 1, characterized in that, During the resource release phase, controlling the read pointer to continue reading rename record information in the rename record queue specifically includes: During the resource release phase, the rename record information after the branch prediction failure point is read sequentially using the read pointer. Modify the physical register file state machine according to the renaming record information to release physical register resources occupied by the faulty path instruction.

5. The method according to claim 1, characterized in that, When the read pointer reaches the position corresponding to the first write pointer, it is determined that the pipeline flushing recovery is complete, and the first write pointer is updated to the position corresponding to the second write pointer, specifically including: When the read pointer reaches the position corresponding to the first write pointer, it is determined that both the recovery phase and the resource release phase have ended. After the pipeline flushing recovery is completed, the position of the read pointer is restored by the flushing recovery start point information recorded in the first register. Move the first write pointer to the position corresponding to the second write pointer to restore the position of the latest written data.

6. A recovery device for automated production line flushing, characterized in that, An out-of-order processor including a rename record queue, wherein the rename record queue is provided with a read pointer, a first write pointer, and a second write pointer, the device comprising: The event detection module is used to record the flush recovery start point corresponding to the read pointer when the flush event occurs, and control the read pointer to read the rename record information from the flush recovery start point, and restore the speculative rename mapping table according to the rename record information when the flush event is detected. The rename record writing module is used to record the branch prediction failure point currently corresponding to the read pointer when the speculative rename mapping table is restored, so as to indicate the end of the recovery phase and the entry into the resource release phase. When entering the resource release phase, the second write pointer is moved to the position corresponding to the branch prediction failure point to write the rename record information corresponding to the new instruction. The pointer position detection module is used to control the read pointer to continue reading the rename record information in the rename record queue during the resource release phase, and to control whether the processor ends the pause and responds to new instructions according to the positional relationship between the second write pointer and the read pointer. The pointer position update module is used to determine that pipeline flushing recovery is complete when the read pointer reads to the position corresponding to the first write pointer, and update the first write pointer to the position corresponding to the second write pointer. The first write pointer is used to characterize the latest write boundary of the rename record queue in normal execution state before the pipeline flushing occurs. Specifically, the control over whether the processor ends the pause and responds to new instructions is based on the positional relationship between the second write pointer and the read pointer, including: During the recovery phase, the processor pause enable signal is unconditionally pulled high to prevent the processor from responding to new instructions; When in the resource release phase, the processor pause enable signal is conditionally disabled based on the positional relationship between the second write pointer and the read pointer. Based on the positional relationship between the second write pointer and the read pointer, the processor pause enable signal is conditionally deactivated, specifically including: When the second write pointer is greater than or equal to the read pointer, it is determined that the current processor resources are insufficient, and the processor is kept in a standby state. When the second write pointer is less than the read pointer, it is determined that the current processor resources meet the conditions for executing the new instruction, and the processor is controlled to end the pause to respond to the new instruction.

7. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is in operation, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the pipeline flushing recovery method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the pipeline flushing recovery method as described in any one of claims 1 to 5.

Images