Delay circuit of chip pin output enable signal, chip and delay adjustment method

Abstract

This application discloses a delay circuit, chip, and delay adjustment method for chip pin output enable signals, belonging to the field of integrated circuit technology. The delay circuit for chip pin output enable signals includes: a delay chain circuit and an AND gate; the input terminal of the delay chain circuit and the first input terminal of the AND gate are used to receive output enable signals from the chip's input / output pins; the output terminal of the delay chain circuit is connected to the second input terminal of the AND gate; the delay chain circuit is used to delay the output enable signal based on the enable signal of the delay chain circuit. The delay circuit, chip, and delay adjustment method for chip pin output enable signals disclosed in this application can reduce or even eliminate the difference between the turn-on and turn-off delays of chip pins, achieving timing convergence of the I / O interface, making it easier to meet the timing requirements of the input / output interface, and enabling the memory interface to achieve higher read / write speeds.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a delay circuit, chip, and delay adjustment method for chip pin output enable signal. Background Technology

[0002] In related technologies, in order to flexibly expand storage capacity according to application needs, most current IoT communication chips adopt system-in-package (SiP) and other encapsulation methods to integrate memory by encapsulating synchronous dynamic random access memory (SDRAM), pseudo-static random access memory (PSRAM), and 6-wire serial peripheral interface (Quad SPI Flash or QSPI Flash).

[0003] To ensure high efficiency in executing programs and data within the encapsulated memory, the maximum clock frequency of the input / output (I / O) interfaces of the memory chips is typically above 100MHz. However, such high clock frequencies can easily lead to timing issues with the I / O interfaces, posing significant challenges to the design of the I / O pins and controllers.

[0004] To ensure the timing of the I / O interface is met even when the clock frequency is high, one existing approach is to design the controller and reserve a certain timing margin for the I / O interface. However, in many cases, even after designing the controller using this method, the timing of the I / O interface still has the problem of being difficult to converge. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a delay circuit, chip, and delay adjustment method for chip pin output enable signals, which can reduce or even eliminate the difference between the turn-on delay and turn-off delay of chip pins, thereby achieving timing convergence of the I / O interface.

[0006] In a first aspect, this application provides a delay circuit for outputting an enable signal from a chip pin, the delay circuit comprising: The input terminal of the delay chain circuit and the first input terminal of the AND gate are used to receive the output enable signal of the chip's input / output pins; The output terminal of the delay chain circuit is connected to the second input terminal of the AND gate; The delay chain circuit is used to delay the output enable signal.

[0007] According to the chip pin output enable signal delay circuit of this application, by delaying the output enable signal OEN through a delay chain circuit and then performing a logical AND operation with the output enable signal OEN, the signal obtained is used as the actual output enable signal of the chip input / output pin. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, realize the timing convergence of the IO interface, and more easily meet the timing of the input / output interface, enabling the storage interface to achieve higher read / write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing convergence difficulties and limited read / write speeds of the storage interface caused by the output delay difference of the chip pin can be solved more effectively. Moreover, it can be implemented in a fully digital manner, making it simpler.

[0008] According to one embodiment of this application, the delay chain circuit includes: a plurality of cascaded delay units; the control terminal of the delay unit is used to receive an enable signal of the delay unit; In two adjacent delay units, the first output terminal of the previous delay unit is connected to the first input terminal of the next delay unit, and the second output terminal of the next delay unit is connected to the second input terminal of the previous delay unit.

[0009] According to one embodiment of this application, the delay unit includes: a multiplexer and at least two delay buffers; The first input terminal of the multiplexer is connected to the first input terminal of the delay unit; the output terminal of the multiplexer is connected to the second output terminal of the delay unit; the control terminal of the multiplexer is connected to the control terminal of the delay unit. At least one delay buffer is provided between the first input terminal and the first output terminal of the delay unit; At least one delay buffer is provided between the second input terminal of the delay unit and the second input terminal of the multiplexer.

[0010] According to one embodiment of this application, the number of delay buffers disposed between the first input terminal and the first output terminal of the delay unit is equal to the number of delay buffers disposed between the second input terminal of the delay unit and the second input terminal of the multiplexer.

[0011] According to one embodiment of this application, when at least two delay buffers are provided between the first input terminal and the first output terminal of the delay unit, the at least two delay buffers are cascaded.

[0012] According to one embodiment of this application, when at least two delay buffers are provided between the second input terminal of the delay unit and the second input terminal of the multiplexer, the at least two delay buffers are cascaded.

[0013] According to one embodiment of this application, when the enable signal input to the control terminal of the delay unit is in a first state, the output terminal of the multiplexer outputs the signal input to the first input terminal of the multiplexer; and when the enable signal input to the control terminal of the delay unit is in a second state, the output terminal of the multiplexer outputs the signal input to the second input terminal of the multiplexer.

[0014] Secondly, this application provides a memory chip, which includes: at least one memory chip and at least one delay circuit for outputting an enable signal from a chip pin as described above.

[0015] According to the memory chip of this application, a higher read / write rate can be achieved by using the aforementioned delay circuit for outputting enable signals from the chip pins.

[0016] According to one embodiment of this application, the memory chip includes at least two memory chips; the delay circuit is connected to the data bus of the at least two memory chips; the timing of the output enable signals of the input / output pins of the chips corresponding to the memory chips connected to the data bus and the delay circuit is the same.

[0017] Thirdly, this application provides a delay adjustment method for a delay circuit of a chip pin output enable signal, the method comprising: With the clock frequency of the chip's input / output interface and the operating parameters of the controller set according to the highest operating frequency, and with not all of the delay unit's enable signals in the second state, the enable signal of the first delay unit that is not in the second state is set to the second state according to the connection order. The corresponding first target data is written to the multiple target storage areas of the chip in sequence, and the data stored in each target storage area is read out. The corresponding second target data is written to the multiple target storage areas in sequence, and the data stored in each target storage area is read out, until all of the delay unit's enable signals are in the second state. By comparing the data read from the target storage area each time with the expected data, the target interval corresponding to the enable signal of each delay unit is determined; Based on the target interval, the state of the enable signal of each delay unit is determined in order to adjust the delay time of the delay circuit.

[0018] According to the delay adjustment method of the delay circuit for the chip pin output enable signal of this application, the delay adjustment range is determined by using a back-to-back "write-read-write" method, thereby adjusting the delay time of the delay circuit. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, achieve timing convergence of the IO interface, and more easily meet the timing requirements of the input and output interfaces. This enables the storage interface to achieve higher read and write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing convergence difficulties and limited read and write speeds of the storage interface caused by the output delay difference of the chip pin can be solved more effectively. Furthermore, it can be implemented in a fully digital manner, making it simpler to implement.

[0019] According to one embodiment of this application, determining the state of the enable signal of each delay unit based on the target interval includes: The state corresponding to the minimum or intermediate value of the target interval is determined as the state of the enable signal of each delay unit.

[0020] Fourthly, this application provides a delay adjustment device for a delay circuit of a chip pin output enable signal, the device comprising: The read / write module is used to, when the clock frequency of the chip's input / output interface and the operating parameters of the controller are set according to the highest operating frequency, and when the enable signals of the delay units are not all in the second state, set the enable signal of the first delay unit that is not in the second state to the second state according to the connection order, sequentially write the corresponding first target data to multiple target storage areas of the chip, and read out the data stored in each target storage area, sequentially write the corresponding second target data to the multiple target storage areas, and read out the data stored in each target storage area, until the enable signals of all delay units are in the second state; The comparison module is used to determine the target interval corresponding to the enable signal of each delay unit by comparing the data read from the target storage area each time with the expected data. A determining module is used to determine the state of the enable signal of each delay unit based on the target interval, so as to adjust the delay time of the delay circuit.

[0021] The delay adjustment device for the delay circuit of the chip pin output enable signal according to this application determines the delay adjustment range by adopting a back-to-back "write-read-write" method, thereby adjusting the delay time of the delay circuit. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, achieve timing convergence of the IO interface, more easily meet the timing of the input and output interfaces, and enable the storage interface to achieve higher read and write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing difficulty in convergence and limited read and write speed of storage interface caused by the output delay difference of chip pins can be solved more effectively. Moreover, it can be implemented in a fully digital manner, making it simpler.

[0022] Fifthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the delay adjustment method of the delay circuit for the chip pin output enable signal as described in the first aspect above.

[0023] In a sixth aspect, this application provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a delay adjustment method for a delay circuit that outputs an enable signal from a chip pin as described in the first aspect above.

[0024] In a seventh aspect, this application provides a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the delay adjustment method of the delay circuit for chip pin output enable signal as described in the first aspect.

[0025] Eighthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements a delay adjustment method for a delay circuit that outputs an enable signal from a chip pin as described in the first aspect above.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the input / output pin structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the delay circuit for the chip pin output enable signal provided in the embodiments of this application; Figure 3 This is a schematic diagram of the output delay of the input / output pins provided in the embodiments of this application; Figure 4 This is a schematic diagram of the delay chain circuit in the delay circuit for the chip pin output enable signal provided in the embodiments of this application; Figure 5 This is a schematic diagram of the delay unit in the delay circuit for the chip pin output enable signal provided in the embodiments of this application; Figure 6 This is one of the structural schematic diagrams of the memory chip provided in the embodiments of this application; Figure 7 This is a second schematic diagram of the structure of the memory chip provided in the embodiments of this application; Figure 8 This is a flowchart illustrating the delay adjustment method of the delay circuit for the chip pin output enable signal provided in the embodiments of this application. Figure 9 This is a schematic diagram of the delay adjustment device for the delay circuit of the chip pin output enable signal provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] In related technologies, in order to meet the timing requirements of the IO interface when the clock frequency of the IO interface is high, there are two main methods: one is to use high-speed input / output pins (IO PADs) or increase the drive capability or slew rate (SR, i.e., "voltage conversion rate") of the IO interface; the other is to reserve a certain timing margin for the IO interface from the perspective of controller design.

[0031] Using high-speed input / output (IO) pads or increasing the drive capability or slew rate of the IO interface can lead to several problems. High-speed IO pads typically require custom design and have a larger area, while increasing the drive capability or slew rate of the IO interface results in a significant increase in the peak current of the IO pads. In summary, this approach results in high power consumption and noise in the IO pads and IO interface, which can easily interfere with IoT communication chips.

[0032] While optimizing I / O interface timing from a controller design perspective can reduce the requirements for I / O pads, the intellectual property (IP) of general-purpose controllers is typically designed for ideal I / O pad models. In integrated circuit (IC) design, IP refers to reusable IC design modules with proprietary functions. These IC design modules are characterized by high performance, low power consumption, high technology density, and concentrated intellectual property, allowing them to be integrated into IC design chips to shorten development time. Because general-purpose controller IP is often designed for ideal I / O pad models, although the I / O interface timing may be ideal during the pre-simulation stage, the actual latency of I / O pads provided by different IC foundries varies significantly. This leads to substantial timing differences in the general-purpose controller IP for I / O pads provided by different foundries during the post-simulation stage, potentially resulting in I / O interface timing not fully meeting requirements and necessitating frequency reduction.

[0033] refer to Figure 1 A general IO PAD structure can be like this Figure 1As shown. By evaluating the pin (PAD) delay models provided by different foundries, it can be found that there is a significant difference in output delay between the effective low-level output enable (OEN) signal and the pin (PAD) signal. This significant difference in output delay refers to the large difference between the turn-on delay and the turn-off delay, typically the former being several nanoseconds longer than the latter. The turn-on delay refers to the delay between the OEN signal changing from high to low and the effective PAD signal output, affecting setup time. The turn-off delay refers to the delay between the OEN signal changing from low to high and the absence of a PAD signal output, affecting hold time. The turn-on and turn-off delays are interdependent, and it is difficult to simultaneously satisfy both conditions using backend tools alone during timing convergence. This can easily lead to suboptimal timing at the memory chip level when OEN changes (especially when OEN changes from low to high).

[0034] The following description, in conjunction with the accompanying drawings, details the delay circuit for chip pin output enable signals, the memory chip, the delay adjustment method for the delay circuit for chip pin output enable signals, the delay adjustment device for the delay circuit for chip pin output enable signals, the electronic device, and the readable storage medium provided in this application, through specific embodiments and application scenarios.

[0035] refer to Figure 2 In some embodiments of this application, a delay circuit for outputting an enable signal from a chip pin includes: a delay chain circuit 210 and an AND gate 220.

[0036] In actual implementation, a delay circuit for outputting an enable signal from a chip pin may include a delay chain circuit 210 and an AND gate 220, among other components.

[0037] The input terminal of the delay chain circuit 210 and the first input terminal of the AND gate 220 are used to receive the output enable signal OEN from the input / output pin of the chip; the output terminal of the delay chain circuit 210 and the second input terminal of the AND gate 220 are connected; the delay chain circuit 210 is used to delay the output enable signal OEN.

[0038] In actual implementation, the output enable signal OEN of the chip's input / output pins can be directly input to the first input terminal of AND gate 220. After being delayed by delay chain circuit 210, the output enable signal OEN is then input to the second input terminal of AND gate 220. AND gate 220 performs a logical AND operation on these two signals and outputs the result of the logical AND operation.

[0039] It is understood that the delay circuit for the chip pin output enable signal provided in the embodiments of this application can be set as follows: Figure 1The OEN interface in the illustrated IO PAD structure is connected to the CMOS (Complementary Metal Oxide Semiconductor). Because the output enable signal OEN of the chip's input / output pins is not directly input to the CMOS, but rather a logical AND operation is performed between the OEN signal itself and the delayed OEN signal before inputting it to the CMOS, the difference between the turn-on and turn-off delays of the chip's input / output pins (IO PADs) (which can be denoted as "PAD signals") can be reduced, making them nearly identical or even equal. This allows for timing convergence of the IO interface, unaffected by different foundries.

[0040] In some embodiments, the actual delay of the delay chain circuit 210 can be adjusted, that is, a delay within a certain range can be achieved.

[0041] In some embodiments, for an IO PAD that uses a delay circuit to output an enable signal from a chip pin, the maximum delay of the delay chain circuit 210 in the delay circuit to output the enable signal from the chip pin can be greater than or equal to the difference between the turn-on delay and the turn-off delay of the IO PAD.

[0042] refer to Figure 3 , Figure 3 Various cases of output delay for the IO PAD are shown. Figure 3 The waveforms of the core input signal I, the output enable signal OEN of the IO PAD, the ideal output signal PAD of the IO PAD (referring to the output signal PAD under zero delay), the actual output signal PAD of the IO PAD (referring to the output signal PAD without using the delay circuit of the chip pin output enable signal in related technologies), and the actual output signal PAD of the improved IO PAD (referring to the output signal PAD with the delay circuit of the chip pin output enable signal) are shown. By comparing the above waveforms, it can be seen that in related technologies, the turn-on delay t1 of the actual output delay of the IO PAD is much larger than the turn-off delay t2. However, by using the delay circuit of the chip pin output enable signal, the turn-on delay t3 of the actual output delay of the improved IO PAD can be made approximately equal to the turn-off delay t4.

[0043] It should be noted that the reference Figure 2 The signals involved in the IO PAD can also include the output signal C to the core and the pull-up / pull-down register enable signal IE. The aforementioned signals OEN, I, C, PAD, and IE can be input to or output from the IO PAD through their respective interfaces (which can be referred to as OEN interface, I interface, C interface, PAD interface, and IE interface, respectively).

[0044] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, the output enable signal OEN is delayed by a delay chain circuit, and then the signal obtained by performing a logical AND operation with the output enable signal OEN is used as the actual output enable signal of the chip input / output pin. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, realize the timing convergence of the IO interface, and more easily meet the timing of the input / output interface, enabling the storage interface to achieve higher read / write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing difficulty in convergence and limited read / write speed of the storage interface caused by the output delay difference of the chip pin can be solved more effectively. Moreover, it can be implemented in a fully digital manner, making it simpler.

[0045] refer to Figure 4 In some embodiments of this application, the delay chain circuit 210 includes: a plurality of cascaded delay units 410; the control terminal of the delay unit 410 is used to receive the enable signal of the delay unit.

[0046] In actual implementation, the delay chain circuit 210 can be composed of a series of delay cells 410 connected in series. The number of delay cells 410 can be at least two. Each delay cell 410 can be controlled by an externally input enable signal to its control terminal.

[0047] It should be noted that by adjusting the state of the enable signal of each delay unit 410, the actual delay generated by the delay chain circuit 210 can be adjusted.

[0048] In some embodiments, the enable signal for each delay unit 410 can be 1 bit.

[0049] In two adjacent delay units 410, the first output terminal of the previous delay unit 410 is connected to the first input terminal of the next delay unit 410, and the second output terminal of the next delay unit 410 is connected to the second input terminal of the previous delay unit 410.

[0050] In actual implementation, each delay unit 410 may include two input terminals (including a first input terminal and a second input terminal) and two output terminals (including a first output terminal and a second output terminal).

[0051] The aforementioned multiple delay units 410 can be cascaded or connected in series as follows: In two adjacent delay units 410, the first output terminal of the previous delay unit 410 is connected to the first input terminal of the next delay unit 410, and the second output terminal of the next delay unit 410 is connected to the second input terminal of the previous delay unit 410. That is, for each delay unit 410 except for the first-stage delay unit 410 and the last-stage delay unit 410, the first input terminal of the delay unit 410 is connected to the first output terminal of the previous delay unit 410, the second input terminal of the delay unit 410 is connected to the second output terminal of the next delay unit 410, the first output terminal of the delay unit 410 is connected to the first input terminal of the next delay unit 410, and the second output terminal of the delay unit 410 is connected to the second input terminal of the previous delay unit 410.

[0052] Understandably, for the first-stage delay unit 410, the first input terminal of the delay unit 410 is connected to the input terminal of the delay chain circuit 210, and is used to receive the output enable signal OEN from the input / output pin of the chip; the second input terminal of the delay unit 410 is connected to the second output terminal of the second-stage delay unit 410; the first output terminal of the delay unit 410 is connected to the first input terminal of the second-stage delay unit 410; and the second output terminal of the delay unit 410 is connected to the output terminal of the delay chain circuit 210, and is used to output the output enable signal OEN after being delayed by the delay chain circuit 210.

[0053] It should be noted that for the last stage delay unit 410, the first input terminal of the delay unit 410 is connected to the first output terminal of the previous stage delay unit 410, the second input terminal of the delay unit 410 is connected to the first output terminal of the delay unit 410, and the second output terminal of the delay unit 410 is connected to the second input terminal of the previous stage delay unit 410.

[0054] It should be noted that the reference Figure 4 According to the connection order between the delay units 410, the first-stage delay unit 410 to the last-stage delay unit 410 can be sequentially referred to as delay unit (0), delay unit (1), delay unit (2), ..., delay unit (n). Correspondingly, the enable signals of each delay unit 410 can be referred to as En (0), En (1), En (2), ..., En (n). Wherein, (n+1) is the number of delay units 410 included in the delay chain circuit 210.

[0055] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, a delay chain circuit is formed by multiple cascaded delay units. By adjusting the state of the enable signal of each delay unit, the actual delay generated by the delay chain circuit is adjusted so that the delay chain circuit matches the chip pin of the chip pin that uses the delay circuit for the chip pin output enable signal. This enables the output enable signal OEN to be delayed by the delay chain circuit and then the signal obtained by performing a logical AND operation with the output enable signal OEN is used as the actual output enable signal of the chip input / output pin. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, realize the timing convergence of the IO interface, and more easily meet the timing of the input / output interface, enabling the storage interface to achieve higher read / write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing difficulties caused by the output delay difference of the chip pin and the limited read / write speed of the storage interface can be solved more effectively. Moreover, it can be implemented in a fully digital manner, making it simpler.

[0056] refer to Figure 5 In some embodiments of this application, the delay unit 410 includes: a multiplexer 510 and at least two delay buffers 520.

[0057] In actual execution, the structures of each delay unit 410 may be the same or different.

[0058] In some embodiments, each delay unit 410 may consist of a delay buffer (buf) 520 and a multiplexer (Mux) 510.

[0059] In some embodiments, both the multiplexer 510 and the delay buffer 520 can be implemented using basic gate circuits from a standard cell library provided by a foundry.

[0060] The first input terminal of the multiplexer 510 is connected to the first input terminal of the delay unit 410; the output terminal of the multiplexer 510 is connected to the second output terminal of the delay unit 410; and the control terminal of the multiplexer 510 is connected to the control terminal of the delay unit 410.

[0061] In actual implementation, the multiplexer 510 may include two input terminals (including a first input terminal and a second input terminal) and one output terminal. The multiplexer 510 can select one signal from the signal input from its first input terminal and the signal input from its second input terminal, and output it from its output terminal.

[0062] In some embodiments, the first input terminal of the multiplexer 510 can be connected to the first input terminal of the delay unit 410, the second input terminal of the multiplexer 510 can be connected to the second input terminal of the delay unit 410, and the output terminal of the multiplexer 510 can be connected to the second output terminal of the delay unit 410.

[0063] At least one delay buffer 520 is provided between the first input terminal and the first output terminal of the delay unit 410; at least one delay buffer 520 is provided between the second input terminal of the delay unit 410 and the second input terminal of the multiplexer 510.

[0064] In actual execution, the transmission path between the first input terminal and the first output terminal of the delay unit 410 can be a forward path, and the transmission path between the second input terminal and the second output terminal can be a return path. For any delay unit 410, at least one delay buffer 520 can be set on both the forward path and the return path.

[0065] It should be noted that the multiplexer 510 can be considered as being set on the return path, and the delay buffer 520 set on the return path is located between the second input terminal of the delay unit 410 and the second input terminal of the multiplexer 510.

[0066] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, at least one delay buffer can be set on both the forward path and the return path of the delay unit. The multiplexer selects the forward path or the return path as the output of the delay unit based on the enable signal, and can adjust its own implemented delay. Thus, through the cooperation of multiple delay units, the delay of the chip pin output enable signal delay circuit can be adjusted.

[0067] In some embodiments of this application, the number of delay buffers 520 disposed between the first input terminal and the first output terminal of the delay unit 410 is equal to the number of delay buffers 520 disposed between the second input terminal of the delay unit 410 and the second input terminal of the multiplexer 510.

[0068] In actual execution, the delay buffers 520 in each delay unit 410 can be set in pairs, with at least two delay buffers 520. Paired setting means that the number of delay buffers 520 set on the forward path and the return path in the delay unit 410 are equal and correspond one-to-one.

[0069] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, by setting delay buffers in pairs on the forward and return paths of the delay unit, the delay of the chip pin output enable signal delay circuit can be adjusted more conveniently.

[0070] In some embodiments of this application, when at least two delay buffers 520 are provided between the first input terminal and the first output terminal of the delay unit 410, the at least two delay buffers 520 are cascaded.

[0071] In actual execution, if at least two delay buffers 520 are set in the forward path of the delay unit 410, the delay buffers 520 set in the forward path can be cascaded in series.

[0072] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, a greater delay can be achieved by cascading at least two delay buffers on the forward path of the delay unit.

[0073] In some embodiments of this application, when at least two delay buffers 520 are provided between the second input terminal of delay unit 410 and the second input terminal of multiplexer 510, the at least two delay buffers 520 are cascaded.

[0074] In actual execution, if at least two delay buffers 520 are set in the return path of the delay unit 410, the delay buffers 520 set in the above return path can be cascaded in series.

[0075] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, a greater delay can be achieved by cascading at least two delay buffers on the return path of the delay unit.

[0076] In some embodiments of this application, when the enable signal input to the control terminal of the delay unit 410 is in a first state, the output terminal of the multiplexer 510 outputs the signal input to the first input terminal of the multiplexer 510, and when the enable signal input to the control terminal of the delay unit 410 is in a second state, the output terminal of the multiplexer 510 outputs the signal input to the second input terminal of the multiplexer 510.

[0077] In actual execution, when the enable signal input to the control terminal of delay unit 410 is in the first state, multiplexer 510 can directly return the signal output from the first output terminal of the previous delay unit 410 to the second input terminal of the previous delay unit 410; when the enable signal input to the control terminal of delay unit 410 is in the second state, the signal output from the second output terminal of the next delay unit 410 can return to the second input terminal of the previous delay unit 410 after passing through delay buffer 520 and multiplexer 510 on the return path.

[0078] In some embodiments, the first state and the second state can be low level and high level, respectively, corresponding to digital signals 0 and 1; or, the first state and the second state can be high level and low level, respectively, corresponding to digital signals 1 and 0.

[0079] In some embodiments, static timing analysis can be used to determine whether the timing of the delay chain circuit 210 and the IO PAD meets the requirements, i.e. whether the difference between the turn-on delay and turn-off delay of the chip pins is reduced or even eliminated.

[0080] In some embodiments, the output delay of the IO PAD can be checked in the following two cases to determine whether the timing of the delay chain circuit 210 and the IO PAD meets the requirements.

[0081] The first method is to set all bits in the enable signal EN[n:0] of each delay unit of the delay chain circuit 210 to 0 (taking the first state as low level, i.e. digital signal 0 as an example), and check the setup time related to the OEN interface to the PAD interface during static timing analysis, ignoring the hold time check.

[0082] The second method is to set all bits of the enable signal EN[n-1:0] of each delay unit of the delay chain circuit 210 to 1 (taking the second state as high level, i.e. digital signal 1 as an example, the highest bit EN[n] is set to 0). During static timing analysis, the hold time related to the OEN interface to the PAD interface is checked, and the setup time is ignored.

[0083] In some embodiments, if the timing check for the hold time is not met in the second case, the number of stages of the delay chain circuit 210 (referring to the number of delay units 410 included in the delay chain circuit 210) and / or the number of pairs of delay buffers 520 in the delay units 410 can be increased before performing a static timing check.

[0084] It should be noted that the delay buffers 520 used in each delay unit 410 can be the same. By increasing the number of pairs of delay buffers 520 in the delay unit 410, the maximum delay of the delay unit 410 can be increased, thereby increasing the maximum delay of the delay chain circuit 210. The maximum delay of the delay chain circuit 210 can also be increased by increasing the number of stages in the delay chain circuit 210.

[0085] According to the chip pin output enable signal delay circuit provided in the embodiments of this application, when the enable signal input to the control terminal of the delay unit is in a first state, the output terminal of the multiplexer outputs the signal input to the first input terminal of the multiplexer, and when the enable signal input to the control terminal of the delay unit is in a second state, the output terminal of the multiplexer outputs the signal input to the second input terminal of the multiplexer. This enables the delay of the delay unit to be adjustable, and the delay of the delay circuit is made adjustable through the cooperation of each delay unit, thereby enabling different degrees of delay for the output enable signal OEN.

[0086] This application also provides a memory chip. (See reference...) Figure 6 The memory chip 600 may include at least one memory chip 610 and at least one delay circuit 620 for outputting enable signals from chip pins.

[0087] In actual implementation, the memory chip 600 can use the delay circuit 620 for chip pin output enable signal provided in any of the foregoing embodiments of this application. After the output enable signal OEN is processed by the delay circuit 620, it is input to IOPAD, thereby reducing the delay of the PAD signal output by the IOP PAD, optimizing the timing of the IOP interface, and enabling the memory chip to achieve a higher read and write speed.

[0088] According to the memory chip provided in the embodiments of this application, a higher read and write rate can be achieved by using the delay circuit of the chip pin output enable signal provided in any of the foregoing embodiments of this application.

[0089] In some embodiments of this application, the memory chip 600 includes at least two memory chips 610; the delay circuit 620 is connected to the data bus of the at least two memory chips 610; the timing of the output enable signals of the input and output pins of the chips corresponding to the memory chips 610 connected to the data bus and the delay circuit is the same.

[0090] In actual implementation, for memory chips 610 with the same timing of output enable signal OEN, the data buses of the aforementioned memory chips 610 can share a delay circuit 620.

[0091] In some embodiments, the data bus of the memory chip 610 is typically in groups of 8 bits (or 4 bits, such as QSPI, etc.), and the timing of its OEN signal is the same. Therefore, the data buses of the multiple memory chips 610 can share a delay circuit 620.

[0092] According to the memory chip provided in the embodiments of this application, by sharing the delay circuit of the chip pin output enable signal through the data bus of memory chips with the same timing of output enable signal, the number of components of the memory chip can be reduced, the workload of memory chip design and manufacturing can be reduced, and the efficiency of memory chip design and manufacturing can be improved.

[0093] One method for adjusting the delay of a delay circuit that outputs an enable signal from a chip pin can be applied to a terminal, and can be executed by the hardware or software in the terminal.

[0094] This application provides a delay adjustment method for a delay circuit of a chip pin output enable signal. The execution subject of this delay adjustment method can be an electronic device or a functional module or entity in an electronic device that can implement the delay adjustment method of the chip pin output enable signal delay circuit. The electronic devices mentioned in this application include, but are not limited to, mobile phones, tablets, computers, cameras, and wearable devices. The delay adjustment method of the chip pin output enable signal delay circuit provided in this application will be described below using an electronic device as the execution subject.

[0095] like Figure 8 As shown, the delay adjustment method of the delay circuit for the chip pin output enable signal includes steps 810, 820 and 830.

[0096] In practice, this delay adjustment method can be applied to the delay circuit of the enable signal output by any of the aforementioned chip pins.

[0097] The delay adjustment method uses a back-to-back "write-read" method to search for the range of the enable signal of the corresponding delay unit 420 that can be read and written correctly. The minimum or center value of the range can be selected as the initial delay adjustment.

[0098] It should be noted that for memory chips such as SDRAM, PSRAM, or QSPI, read and write operations typically involve several stages. A read operation generally includes the following stages: "IDLE + Send command + Send address + Read data + IDLE"; a write operation generally includes the following stages: "IDLE + Send command + Send address + Write data + IDLE".

[0099] During the read operation, the OEN signal will change from low to high level between "send address" and "read data". At this time, it is important to pay attention to whether the read data is correct.

[0100] During the write operation, the OEN signal will change from low to high level between "write data" and "IDLE". At this time, it is important to pay attention to whether the data is correctly written to the memory.

[0101] During the chip development phase, in the post-simulation process, the delay adjustment range can be determined using a back-to-back "write-read" method, either at the Fast Process Corner or at room temperature (during the sample verification phase). The Fast Process Corner includes the use of a fast process, the lowest temperature, and the highest voltage.

[0102] Step 810: With the clock frequency of the chip's input / output interface and the operating parameters of the controller set according to the highest operating frequency, and with not all the enable signals of the delay units in the second state, according to the connection order, set the enable signal of the first delay unit that is not in the second state to the second state, write the corresponding first target data to the multiple target storage areas of the chip in sequence, and read out the data stored in each target storage area, write the corresponding second target data to the multiple target storage areas in sequence, and read out the data stored in each target storage area, until all the enable signals of each delay unit are in the second state.

[0103] In actual implementation, the clock frequency of the IO interface and the corresponding controller operating parameters can be set according to the highest operating frequency.

[0104] After making the above settings, the enable signals En of each delay unit 410 in the delay chain circuit 210 can be set to 1 sequentially in ascending order of bit position (i.e., the order in which the delay units 410 are cascaded, from 0 to n) (taking the second state as high level, i.e., digital signal 1 as an example). That is, the enable signal EN[n:0] is set sequentially to 0x0, 0x1, 0x3, 0x7, 0xf, ..., 0xffffffff. Here, n is 31 as an example, but n can also be other values.

[0105] In four specific regions of the storage particle, specific test data pattern0(0x5a5aa5a5,0xa5a55a5a, 0x5aa5a55a, 0xa55a5aa5) is written sequentially and then read out.

[0106] Then, write specific test data pattern1 (0xa5a55a5a, 0x5a5a5a5, 0xa55a5a5, 0x5aa5a5) into the four specific regions mentioned above, and then read it out.

[0107] It should be noted that the four specific regions of the storage particle are the multiple target storage regions of the chip, that is, the multiple target storage regions of the chip can be multiple regions in a single storage particle of the chip.

[0108] It should be noted that specific test data pattern0 is the first target data, and specific test data pattern1 is the second target data. The specific contents of the aforementioned specific test data pattern0 and pattern1 are merely illustrative examples and are not limited to these.

[0109] Step 820: By comparing the data read from the target storage area each time with the expected data, determine the target interval corresponding to the enable signal of each delay unit.

[0110] In actual execution, the data read out multiple times (eight times in the example above) can be compared with the expected value of the read data (i.e., "expected data", usually the data written). The interval of EN[n:0] through which the written data and the read data are compared is recorded as the target interval corresponding to the enable signal of each delay unit.

[0111] It is understandable that the comparison between the written data and the read data passes, meaning that the written data and the read data are the same, the data was written correctly, and there was no inconsistency between the written data and the read data due to the delay of the OEN signal.

[0112] Step 830: Based on the target interval, determine the state of the enable signal of each delay unit in order to adjust the delay time of the delay circuit.

[0113] In actual execution, after determining the target range corresponding to the enable signal of each delay unit, a value in the target range can be determined as the state of the enable signal of each delay unit, which is used to control the operation of the delay circuit 620, thereby adjusting the delay time of the delay circuit 620.

[0114] According to the delay adjustment method of the delay circuit for the chip pin output enable signal provided in the embodiments of this application, the delay adjustment range is determined by using a back-to-back "write-read-write" method, thereby adjusting the delay time of the delay circuit. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, achieve timing convergence of the IO interface, and more easily meet the timing requirements of the input / output interface. This enables the storage interface to achieve higher read and write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing convergence difficulties and limited read and write speeds of the storage interface caused by the output delay difference of the chip pin can be solved more effectively. Furthermore, it can be implemented in a fully digital manner, making it simpler to implement.

[0115] In some embodiments of this application, determining the state of the enable signal of each delay unit based on the target interval includes: determining the state corresponding to the minimum or intermediate value of the target interval as the state of the enable signal of each delay unit.

[0116] In actual execution, after determining the target interval corresponding to the enable signal of each delay unit, the minimum or intermediate value of the target interval (referring to the center or center point of the target interval) can be selected as the initial delay adjustment.

[0117] In some embodiments, during the chip development stage, the delay value corresponding to the minimum value of EN[n:0] in the target interval can be selected as the initial delay value; during the sample verification stage, the delay value corresponding to the middle value or the center point of EN[n:0] in the target interval can be selected as the initial delay value; in actual chip applications, the maximum value of the above two can be selected as the initial delay value.

[0118] It should be noted that the delay value corresponding to a value of EN[n:0] in the target interval refers to the delay that the delay chain circuit 210 can achieve when it operates under the control of the enable signal represented by that value, and the delay circuit that outputs the enable signal from the chip pin.

[0119] According to the delay adjustment method of the delay circuit for chip pin output enable signal provided in the embodiments of this application, by determining the state corresponding to the minimum or intermediate value of the target interval as the state of the enable signal of each delay unit, the delay of the delay circuit for chip pin output enable signal can be adjusted.

[0120] The delay adjustment method for the delay circuit of the chip pin output enable signal provided in this application embodiment can be executed by a delay adjustment device for the delay circuit of the chip pin output enable signal. This application embodiment uses the execution of the delay adjustment method for the delay circuit of the chip pin output enable signal by the delay adjustment device as an example to illustrate the delay adjustment device for the delay circuit of the chip pin output enable signal provided in this application embodiment.

[0121] This application also provides a delay adjustment device for a delay circuit that outputs an enable signal from a chip pin. For example... Figure 9 As shown, the delay adjustment device of the delay circuit for the chip pin output enable signal includes: a read / write module 910, a comparison module 920, and a determination module 930.

[0122] The read / write module 910 is used to, when the clock frequency of the chip's input / output interface and the operating parameters of the controller are set according to the highest operating frequency, and when the enable signals of the delay units are not all in the second state, set the enable signal of the first delay unit that is not in the second state to the second state according to the connection order, sequentially write the corresponding first target data to multiple target storage areas of the chip, and read out the data stored in each target storage area, sequentially write the corresponding second target data to multiple target storage areas, and read out the data stored in each target storage area, until the enable signals of all delay units are in the second state; The comparison module 920 is used to determine the target interval corresponding to the enable signal of each delay unit by comparing the data read from the target storage area each time with the expected data. The determination module 930 is used to determine the state of the enable signal of each delay unit based on the target interval, so as to adjust the delay time of the delay circuit.

[0123] The delay adjustment device for the delay circuit of the chip pin output enable signal provided in the embodiments of this application determines the delay adjustment range by adopting a back-to-back "write-read-write" method, thereby adjusting the delay time of the delay circuit. This can reduce or even eliminate the difference between the turn-on delay and turn-off delay of the chip pin, achieve timing convergence of the IO interface, and more easily meet the timing requirements of the input / output interface. This enables the storage interface to achieve higher read / write speeds. By adding an adjustable delay circuit to the general-purpose controller and ordinary IO PAD, the problems of timing convergence difficulties and limited read / write speeds of the storage interface caused by the output delay difference of the chip pin can be solved more effectively. Furthermore, it can be implemented in a fully digital manner, making it simpler to implement.

[0124] In some embodiments, the determining module 930 may be specifically used to determine the state corresponding to the minimum or intermediate value of the target interval, as the state of the enable signal of each delay unit.

[0125] The delay adjustment device of the delay circuit for the chip pin output enable signal in this embodiment can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This embodiment does not specifically limit the specific type of device.

[0126] The delay adjustment device of the delay circuit for the chip pin output enable signal in this embodiment can be a device with an operating system. This operating system can be Microsoft Windows, Android, iOS, or other possible operating systems; this embodiment does not specifically limit it.

[0127] The delay adjustment device for the delay circuit of the chip pin output enable signal provided in this application embodiment can achieve... Figure 8 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0128] In some embodiments, such as Figure 10 As shown, this application embodiment also provides an electronic device 1000, including a processor 1001, a memory 1002, and a computer program stored in the memory 1002 and executable on the processor 1001. When the computer program is executed by the processor 1001, it implements the various processes of the delay adjustment method embodiment of the delay circuit for the chip pin output enable signal, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0129] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0130] This application also provides a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the delay adjustment method embodiment for the delay circuit of the chip pin output enable signal, and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0131] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0132] This application also provides a computer program product, including a computer program that, when executed by a processor, implements a delay adjustment method for the delay circuit of the chip pin output enable signal.

[0133] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0134] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the delay adjustment method embodiment of the delay circuit for the chip pin output enable signal, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0135] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0138] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0139] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0140] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A delay circuit for outputting an enable signal from a chip pin, characterized in that, include: Delay chain circuits and AND gates; The input terminal of the delay chain circuit and the first input terminal of the AND gate are used to receive the output enable signal of the chip's input / output pins; The output terminal of the delay chain circuit is connected to the second input terminal of the AND gate; The delay chain circuit is used to delay the output enable signal.

2. The delay circuit for outputting the enable signal from the chip pin according to claim 1, characterized in that, The delay chain circuit includes: multiple cascaded delay units; the control terminal of each delay unit is used to receive the enable signal of the delay unit; In two adjacent delay units, the first output terminal of the previous delay unit is connected to the first input terminal of the next delay unit, and the second output terminal of the next delay unit is connected to the second input terminal of the previous delay unit.

3. The delay circuit for outputting the enable signal from the chip pin according to claim 2, characterized in that, The delay unit includes: a multiplexer and at least two delay buffers; The first input terminal of the multiplexer is connected to the first input terminal of the delay unit; the output terminal of the multiplexer is connected to the second output terminal of the delay unit; the control terminal of the multiplexer is connected to the control terminal of the delay unit. At least one delay buffer is provided between the first input terminal and the first output terminal of the delay unit; At least one delay buffer is provided between the second input terminal of the delay unit and the second input terminal of the multiplexer.

4. The delay circuit for outputting the enable signal from the chip pin according to claim 3, characterized in that, The number of delay buffers disposed between the first input terminal and the first output terminal of the delay unit is equal to the number of delay buffers disposed between the second input terminal of the delay unit and the second input terminal of the multiplexer.

5. The delay circuit for outputting the enable signal from the chip pin according to claim 3, characterized in that, When at least two delay buffers are provided between the first input terminal and the first output terminal of the delay unit, the at least two delay buffers are cascaded.

6. The delay circuit for outputting the enable signal from the chip pin according to claim 3, characterized in that, When at least two delay buffers are provided between the second input terminal of the delay unit and the second input terminal of the multiplexer, the at least two delay buffers are cascaded.

7. The delay circuit for outputting enable signals from chip pins according to any one of claims 3 to 6, characterized in that, When the enable signal input to the control terminal of the delay unit is in the first state, the output terminal of the multiplexer outputs the signal input to the first input terminal of the multiplexer; and when the enable signal input to the control terminal of the delay unit is in the second state, the output terminal of the multiplexer outputs the signal input to the second input terminal of the multiplexer.

8. A memory chip, characterized in that, It includes at least one memory chip and at least one delay circuit for outputting a chip pin enable signal as described in any one of claims 1 to 7.

9. The memory chip according to claim 8, characterized in that, It includes at least two memory chips; the delay circuit is connected to the data bus of at least two memory chips; the timing of the output enable signals of the input and output pins of the chips corresponding to the memory chips connected to the data bus and the delay circuit is the same.

10. A method for adjusting the delay of a delay circuit for a chip pin output enable signal, characterized in that, include: With the clock frequency of the chip's input / output interface and the operating parameters of the controller set according to the highest operating frequency, and with not all of the delay unit's enable signals in the second state, the enable signal of the first delay unit that is not in the second state is set to the second state according to the connection order. The corresponding first target data is written to the multiple target storage areas of the chip in sequence, and the data stored in each target storage area is read out. The corresponding second target data is written to the multiple target storage areas in sequence, and the data stored in each target storage area is read out, until all of the delay unit's enable signals are in the second state. By comparing the data read from the target storage area each time with the expected data, the target interval corresponding to the enable signal of each delay unit is determined; Based on the target interval, the state of the enable signal of each delay unit is determined in order to adjust the delay time of the delay circuit.

11. The delay adjustment method according to claim 10, characterized in that, Determining the state of the enable signal for each delay unit based on the target interval includes: The state corresponding to the minimum or intermediate value of the target interval is determined as the state of the enable signal of each delay unit.

12. A delay adjustment device for a delay circuit that outputs an enable signal from a chip pin, characterized in that, include: The read / write module is used to, when the clock frequency of the chip's input / output interface and the controller's operating parameters are set to the highest operating frequency, and when not all the enable signals of the delay units are in the second state, set the enable signal of the first delay unit that is not in the second state to the second state according to the connection order, sequentially write the corresponding first target data to multiple target storage areas of the chip, and read out the data stored in each target storage area, sequentially write the corresponding second target data to the multiple target storage areas, and read out the data stored in each target storage area, until all the enable signals of the delay units are in the second state; The comparison module is used to determine the target interval corresponding to the enable signal of each delay unit by comparing the data read from the target storage area each time with the expected data. A determining module is used to determine the state of the enable signal of each delay unit based on the target interval, so as to adjust the delay time of the delay circuit.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the delay adjustment method as described in claim 10 or 11.

14. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the delay adjustment method as described in claim 10 or 11.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the delay adjustment method as described in claim 10 or 11.

Images