An ARM+CPLD-based high-performance distributed IO communication method

Abstract

The application relates to the field of intelligent inspection and state monitoring of a transformer substation, and discloses a high-performance distributed IO communication method based on ARM+CPLD; the method is applied to a distributed IO network composed of an ARM coupler and a plurality of CPLD slot modules, and a communication bus comprises a downlink communication bus, an uplink communication bus, a synchronization line, a sending enable line and a receiving enable line. The ARM coupler establishes a downlink sending queue, encapsulates IO control instructions into downlink data frames containing a frame header, a receiving end serial number, a module ID, data content and a verification field, and continuously sends the downlink data frames; after downlink sending is completed, the synchronization line is switched to trigger synchronous output and synchronous acquisition of each slot module. Each slot module determines a slot serial number according to a receiving enable line pulse and executes instructions in a directional manner, encapsulates acquisition data into uplink data frames, returns the uplink data frames in a slot serial number sequence, and triggers the next module to send through the sending enable line. After the ARM coupler performs CRC verification on the uplink data frames, the uplink data frames are uploaded to an upper network.

Description

Technical Field

[0001] This invention relates to the field of electrical communication technology, and specifically to a high-performance distributed I / O communication method based on ARM+CPLD. Background Technology

[0002] Distributed I / O systems are widely used in industrial automation, motion control, and process control scenarios. They typically require I / O output control and I / O acquisition and feedback to be completed between multiple remote slot modules, and periodic interaction with a host network. As the scale of equipment increases and the number of signal points grows, the real-time performance, synchronization, and reliability of the communication link have an increasingly significant impact on the system's control accuracy and operational stability.

[0003] Existing distributed I / O communication often employs a master-slave polling mechanism to distribute downlink commands and transmit uplink data. Common implementations rely on a single communication channel or a broadcast-address matching mechanism, with software scheduling controlling the timing of multi-module transmissions. Some solutions use fixed address configuration or DIP switches to determine module identifiers, and use frame headers, address fields, and checksum fields for data parsing and error detection.

[0004] When multiple modules operate in parallel and the communication cycle requirement is short, polling scheduling is prone to time discrepancies between instruction issuance and data acquisition and transmission, making it difficult to ensure the synchronization and consistency between the I / O output actions of multiple modules and the data acquisition actions. At the same time, during the uplink transmission phase, bus idle waiting or conflict retransmission caused by multiple modules competing to send data can easily occur, resulting in communication cycle jitter and decreased bandwidth utilization. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a high-performance distributed I / O communication method based on ARM+CPLD. This method solves the technical problems in existing technologies, such as the difficulty in stably aligning and registering multi-source perception data in time and space, the inability to maintain the corresponding position of geometric structures, visible light textures, and thermal imaging temperature information in VR 3D scenes, and the difficulty in achieving low-latency incremental updates and continuous reconstruction rendering for regions of interest under conditions of limited bandwidth and continuously changing viewpoints.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: A high-performance distributed I / O communication method based on ARM+CPLD includes the following steps: It is applied to a distributed I / O network consisting of ARM couplers and multiple CPLD slot modules. The ARM coupler is connected to each CPLD slot module via a communication bus, which includes a downlink communication bus, an uplink communication bus, a synchronization line, a transmit enable line, and a receive enable line. The method is characterized by the following steps: S1: The ARM coupler establishes a downlink transmission queue, receives IO control commands from the host network, encapsulates the IO control commands into downlink data frames according to the preset frame structure, and writes them into the downlink transmission queue. Downlink data frames include a frame header field, a receiver sequence number field, a module ID field, a data content field, and a checksum field; S2: When each communication cycle is triggered, the ARM coupler controls the synchronization line to be at the first level and continuously sends multiple downlink data frames in the downlink transmission queue via the downlink communication bus; S3: After the downlink data frame is sent, the ARM coupler controls the synchronization line to switch to the second level to trigger each CPLD slot module to synchronously execute the corresponding IO output action and synchronously start the IO acquisition action; S4: Each CPLD slot module determines its own slot number by detecting the valid pulse parameters of the receive enable line, and parses the receiver sequence number field when receiving downlink data frames. When the receiver sequence number matches its own slot number, it receives the data content field of the downlink data frame and executes the corresponding IO control command. S5: Each CPLD slot module encapsulates the collected data into uplink data frames. The uplink data frame includes a frame header field, a sender sequence number field, a module ID field, a data content field, and a check field. After detecting the preset edge trigger signal of the receive enable line, each CPLD slot module sequentially sends uplink data frames via the uplink communication bus in ascending order of slot number; the slot number is... After the CPLD slot module completes its uplink data frame transmission, the control transmit enable line output is used to trigger the slot with the sequence number [slot number missing]. The CPLD slot module sends a trigger pulse to increase the slot number by 1. The CPLD slot module with slot 1 incremented begins sending its uplink data frames, thus forming a sequential backhaul process; S6: The ARM coupler receives each uplink data frame and performs the corresponding verification processing for the verification field. After the verification is successful, the data content field is extracted and uploaded to the host network.

[0007] Preferably, step S1 includes: The ARM coupler initializes the buffer for storing downlink data frames and the receive buffer for storing uplink data frames, and initializes the timer to generate a communication cycle trigger signal, so that downlink transmission and uplink reception are executed at fixed cycles; The ARM coupler will send a pulse signal configured to periodically output the enable line for timing coordination during the slot module sending process.

[0008] Preferably, steps S2 to S3 satisfy the following timing rules: The ARM coupler keeps the synchronization line low during the continuous transmission of multiple downlink data frames, and switches the synchronization line high after the last downlink data frame is transmitted and holds it for a preset time. Each CPLD slot module synchronously executes IO output and synchronously starts IO acquisition after detecting the rising edge of the synchronization line.

[0009] Preferably, the data content fields of the downlink data frame and the uplink data frame include: The command type subfield is used to indicate whether the data frame is a control command frame, a configuration parameter frame, or a status query frame; The data length subfield is used to characterize the length of the payload in bytes; The payload subfield is used to carry IO output parameters, IO acquisition data, or slot module status parameters; The data length configuration range is from 1 byte to 256 bytes.

[0010] Preferably, determining the slot number in step S4 includes: The CPLD slot module uses clock counting to measure the effective level duration of the receive enable line, based on a preset basic pulse width. As a counting unit, when the effective level duration is Multiply At that time, the slot number is determined as ,in It is a positive integer.

[0011] Preferably, step S4 includes: When the sequence number of the receiving end matches the sequence number of its own slot, the IO control command corresponding to the downlink data frame is executed; When the sequence number of the receiving end is inconsistent with its own slot sequence number, the downlink data frame is discarded and the current IO output state remains unchanged.

[0012] Preferably, step S5 includes: The CPLD slot module initiates uplink data frame transmission after detecting a falling edge that switches the receive enable line from high to low. After the CPLD slot module completes its transmission, it outputs a trigger pulse. The trigger pulse is a high-level pulse on the transmit enable line. The duration of the high-level trigger pulse is set incrementally according to the slot number of this module, serving as the start signal for the next slot module's transmission.

[0013] Preferably, during the sequential backhaul process: The receive enable line is used to indicate the start time of uplink transmission from the slot module; The transmit enable line is used to indicate the end time of the slot module's uplink transmission; Once a slot module finishes sending, the next slot module is triggered to start sending. The bus remains continuously occupied during the sequential return of multiple slot modules, avoiding bus idle waiting and bus preemption conflicts caused by multiple slot modules sending at the same time.

[0014] Preferably, the method further includes: The ARM coupler counts the number of received uplink data frames within a preset time window and establishes an online module table based on the sender sequence number field and module ID field in the uplink data frames. When the number of uplink data frames received within a preset time window changes, the online module table is updated to identify the disconnection or hot-plugging status of the slot module.

[0015] Preferably, the verification field is a cyclic redundancy check code, and the ARM coupler and CPLD slot module perform consistency verification on the cyclic redundancy check code after receiving the data frame. When the verification passes, the data content fields are extracted and used for interaction with the higher-level network. When a verification fails, the corresponding data frame is discarded and the verification failure count is recorded. When the verification failure count reaches a preset threshold, the corresponding slot module is marked as an abnormal node for online module table updates.

[0016] In summary, the present invention has the following main beneficial effects: This application establishes a downlink communication bus, an uplink communication bus, a synchronization line, a transmit enable line, and a receive enable line between an ARM coupler and multiple CPLD slot modules. Within each communication cycle, it employs a combination of downlink queued continuous transmission and synchronization line triggering. This allows the ARM coupler to continuously transmit multiple downlink data frames when the synchronization line is at the first level. After downlink transmission is completed, it controls the synchronization line to switch to the second level, triggering each CPLD slot module to synchronously execute IO output actions and synchronously start IO acquisition actions. This achieves the effects of improving action consistency and acquisition time alignment in multi-slot module parallel control and acquisition scenarios, reducing time dispersion and acquisition deviation caused by polling control, and improving data comparability and control stability.

[0017] This application determines and latches the slot number by receiving the valid pulse parameters of the enable line, and sets the receiver number field and module ID field in the downlink data frame. This enables each CPLD slot module to receive and execute only downlink data frames that match its own slot number, discarding mismatched data frames and keeping the current IO output state unchanged. This achieves the effects of avoiding the risk of mis-execution caused by broadcast reception, improving the accuracy of instruction distribution and the reliability of module control, reducing the deployment complexity caused by address configuration or DIP switch maintenance, and improving the convenience of module replacement and maintenance.

[0018] This application employs a sequential backhaul mechanism that combines receive enable line triggering and transmit enable line cascading triggering during the uplink phase. This mechanism enables each CPLD slot module to send uplink data frames sequentially from smallest to largest slot number. After the CPLD slot module with slot number n finishes sending, a trigger pulse is output to trigger the CPLD slot module with slot number n+1 to send. This ensures that the uplink communication bus remains continuously occupied during the sequential backhaul of multiple slot modules and avoids bus idle waiting and concurrent preemption conflicts. At the same time, the consistency verification of the verification field and the online module table update realize the identification of abnormal nodes and hot-plug status. This achieves the effects of improving uplink bandwidth utilization and communication cycle determinism, reducing bus conflicts and cycle jitter, improving communication reliability, and enhancing the system's online diagnostic and maintenance capabilities. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the distributed I / O network structure of the present invention; Figure 2 This is a flowchart of the method of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1 refer to Figure 1 A high-performance distributed I / O communication method based on ARM+CPLD includes the following steps: It is applied to a distributed I / O network consisting of ARM couplers and multiple CPLD slot modules. The ARM coupler is connected to each CPLD slot module via a communication bus, which includes a downlink communication bus, an uplink communication bus, a synchronization line, a transmit enable line, and a receive enable line. The method is characterized by the following steps: S1: The ARM coupler establishes a downlink transmission queue, receives IO control commands from the host network, encapsulates the IO control commands into downlink data frames according to the preset frame structure, and writes them into the downlink transmission queue. Downlink data frames include a frame header field, a receiver sequence number field, a module ID field, a data content field, and a checksum field; S2: When each communication cycle is triggered, the ARM coupler controls the synchronization line to be at the first level and continuously sends multiple downlink data frames in the downlink transmission queue via the downlink communication bus; S3: After the downlink data frame is sent, the ARM coupler controls the synchronization line to switch to the second level to trigger each CPLD slot module to synchronously execute the corresponding IO output action and synchronously start the IO acquisition action; S4: Each CPLD slot module determines its own slot number by detecting the valid pulse parameters of the received enable line. When receiving downlink data frames, the receiver sequence number field is parsed. When the receiver sequence number matches its own slot sequence number, the data content field of the downlink data frame is received and the corresponding IO control instructions are executed. S5: Each CPLD slot module encapsulates the acquired data into uplink data frames. The uplink data frame includes a frame header field, a sender sequence number field, a module ID field, a data content field, and a checksum field. After detecting the preset edge trigger signal of the receive enable line, each CPLD slot module sequentially sends uplink data frames via the uplink communication bus in ascending order of slot number. The slot number is After the CPLD slot module completes its uplink data frame transmission, the control transmit enable line output is used to trigger the slot with the sequence number [slot number missing]. The trigger pulse sent by the CPLD slot module with +1 Make the slot number as The CPLD slot module with slot 1 incremented begins sending its uplink data frames, thus forming a sequential backhaul process; S6: The ARM coupler receives each uplink data frame and performs the corresponding verification processing for the verification field. After the verification is successful, the data content field is extracted and uploaded to the host network.

[0022] The downlink communication bus is used by the ARM coupler to send downlink data frames to each CPLD slot module, and the uplink communication bus is used by each CPLD slot module to send uplink data frames back to the ARM coupler. The synchronization line is used to trigger each CPLD slot module to synchronously execute IO output actions and synchronously start IO acquisition actions. The receive enable line is used to provide the valid pulse parameters required to determine the slot number and to indicate the start trigger conditions of the uplink phase. The transmit enable line is used to pass the transmit start flag from the previous slot module to the next slot module in the uplink phase to form a sequential backlink link according to the slot number.

[0023] The first level of the synchronization line is low, and the second level is high. The rising edge that switches the synchronization line from low to high is defined as the synchronization trigger edge. Through this synchronization trigger edge, each CPLD slot module can synchronously execute IO output actions and synchronously start IO acquisition actions at the same time, thereby avoiding the problem of inconsistent acquisition windows caused by the dispersed action time of slave devices in traditional polling schemes.

[0024] This embodiment divides a communication cycle into a downlink phase, a synchronization phase, and an uplink phase. The three phases are executed sequentially in time, forming a closed-loop communication process of downlink configuration, synchronization action, and uplink backhaul within a communication cycle.

[0025] 1) Downlink phase: The ARM coupler continuously sends multiple downlink data frames, and the synchronization line remains low during this phase; 2) Synchronization phase: After the ARM coupler completes the transmission of the downlink data frame, it switches the synchronization line to a high level and holds it for a preset time, so that each CPLD slot module can synchronously execute control actions and synchronously start the acquisition action; 3) Uplink phase: After detecting the preset edge trigger signal of the receive enable line, each CPLD slot module transmits uplink data frames in ascending order of slot number. After the previous slot module completes its transmission, it outputs a transmit enable line trigger pulse as the start identifier of the next slot module, thus forming a sequential transmission process.

[0026] To avoid bus preemption conflicts caused by multiple slot modules transmitting simultaneously during the uplink phase, this embodiment employs a bus occupancy coordination mechanism: the receive enable line indicates the start time of uplink transmission by the slot module, and the transmit enable line indicates the end time of uplink transmission by the slot module. The ARM coupler defines the uplink phase as the effective window corresponding to the receive enable line. Each slot module only performs sequential backhaul within this effective window, ensuring continuous occupancy of the uplink communication bus during the sequential backhaul of multiple slot modules, thus avoiding bus idle waiting and concurrent transmission conflicts.

[0027] An ARM coupler includes at least a processor, a downlink transmit buffer, an uplink receive buffer, a timer, a downlink communication interface, and an uplink communication interface. The ARM coupler is used to execute downlink transmission, synchronization triggering, and uplink receive verification and upload processes.

[0028] During the system power-on initialization phase, the ARM coupler outputs a valid pulse on the receive enable line for slot number identification. Each CPLD slot module measures the duration of the valid level on the receive enable line within the initialization window and latches it as its own slot number. After the slot number is latched, it is used in subsequent communication cycles to parse the receive end sequence number field and generate the send end sequence number field, thereby ensuring the consistency of the slot identifier.

[0029] The ARM coupler initializes the buffer for storing downlink data frames and the receive buffer for storing uplink data frames, and initializes the timer to generate a communication cycle trigger signal, so that downlink transmission and uplink reception are executed at fixed cycles.

[0030] The ARM coupler establishes a downlink transmit queue, receives IO control commands from the host network, encapsulates the IO control commands into downlink data frames according to a preset frame structure, and writes them into the downlink transmit queue. The downlink transmit queue can be implemented using a circular queue structure or a double-buffered structure. The queue elements are complete downlink data frames. The ARM coupler writes data into the queue according to the slot number or the order in which the commands arrive, so as to continuously transmit control data for multiple slot modules within one communication cycle.

[0031] In this embodiment, the downlink data frame includes at least a frame header field, a receiver sequence number field, a module ID field, a data content field, and a checksum field: The frame header field is used to identify the start of a frame and is used for fast synchronization at the receiving end; The receiver sequence number field is used to indicate which CPLD slot module with which slot number should receive and execute the downlink data frame; The Module ID field is used to identify the module type and module model of the target slot module, so as to support the mixed networking of different types of slot modules; The data content field is used to carry I / O control commands and their parameters; The verification field is used to detect transmission errors.

[0032] Furthermore, to facilitate instruction expansion and parsing, the data content field may include a command type subfield, a data length subfield, and a payload subfield: the command type subfield indicates whether the data frame is a control instruction frame, a configuration parameter frame, or a status query frame; the data length subfield characterizes the byte length of the payload; and the payload subfield carries IO output parameters, IO acquisition data, or slot module status parameters. The data length configuration range is from 1 byte to 256 bytes, and the data length subfield can occupy 1 byte or 2 bytes. The receiving end determines the boundaries of the payload subfield and completes parsing based on the data length subfield.

[0033] When each communication cycle is triggered, the ARM coupler controls the synchronization line to the first level and continuously transmits multiple downlink data frames in the downlink transmission queue via the downlink communication bus.

[0034] The continuous transmission refers to the ARM coupler sending multiple downlink data frames in the same communication cycle according to the queue order. Except for meeting the minimum inter-frame interval required for physical layer transceiver switching, no extra idle waiting is inserted, thereby reducing the downlink phase occupation time and improving the bus effective utilization rate.

[0035] After the last downlink data frame is sent, the ARM coupler controls the synchronization line to switch to the second level, triggering each CPLD slot module to synchronously execute the corresponding IO output action and synchronously start the IO acquisition action. The rising edge of the synchronization line switching to the second level serves as the synchronization trigger edge. The ARM coupler can maintain the synchronization line at the second level for a preset holding time. The preset holding time can be set according to the minimum response time required for the slot module to execute the control action and start the acquisition, so as to ensure that the synchronization trigger signal covers the effective response range of each module.

[0036] During the uplink phase, the ARM coupler receives uplink data frames from each CPLD slot module and performs verification processing corresponding to the verification fields. After successful verification, the data content fields are extracted and uploaded to the host network. To facilitate maintenance and fault location, the ARM coupler can upload the transmitter sequence number field and the module ID field together for slot location and module type identification on the host network side.

[0037] The host network can be an industrial Ethernet, a serial communication network, or other host computer communication links. The ARM coupler encapsulates the IO acquisition data and status information obtained by parsing the verified uplink data frames according to the host network protocol and sends them to the host device to realize the host device's monitoring and control of the distributed IO network.

[0038] Each CPLD slot module includes at least: CPLD control logic, downlink receive parsing logic, IO output control logic, IO acquisition logic, uplink transmit logic, and timing and triggering logic related to the transmit enable line and receive enable line. The CPLD slot module is used to perform slot number determination, downlink directed receive execution, synchronous acquisition, and uplink sequential return processes.

[0039] Each CPLD slot module determines its slot number by detecting the effective pulse parameters of the receive enable line. Specifically, the CPLD slot module uses a clock counting method to measure the duration of the effective level of the receive enable line, with a preset basic pulse width. As a counting unit, when the effective level duration is When multiplied by T0, the slot number is determined as follows. ,in The value is a positive integer. The effective level can be high or low, depending on the system convention.

[0040] To ensure the repeatability of slot number calculation, this embodiment uses the following calculation formula: ; in, Indicates the slot number; Indicates the duration of the active level of the receive enable line; Indicates the basic pulse width; This indicates the integer division operation.

[0041] When receiving downlink data frames, the CPLD slot module parses the receiver sequence number field. When the receiver sequence number field matches its own slot sequence number, it receives the data content field of the downlink data frame and executes the corresponding IO control instructions. When the receiver sequence number field does not match its own slot sequence number, it discards the downlink data frame and keeps the current IO output state unchanged.

[0042] Maintaining the current IO output state unchanged includes maintaining the IO output state latched after the synchronization trigger of the previous communication cycle, so as to avoid output jitter caused by misreception or frame loss.

[0043] When the CPLD slot module detects the synchronization trigger edge of the synchronization line, it immediately applies the received IO control command to the IO output control logic and synchronously starts the IO acquisition logic. Synchronous start can adopt the acquisition trigger latch method, that is, when the synchronization trigger edge arrives, the acquisition start flag is latched, so that the acquisition window is aligned between each CPLD slot module, thereby improving the time consistency of the acquired data.

[0044] Each CPLD slot module encapsulates the acquired data into uplink data frames. The uplink data frame includes a frame header field, a sender sequence number field, a module ID field, a data content field, and a checksum field. The frame header field is used to identify the start of an uplink data frame; The sender sequence number field is used to identify which slot sequence number the uplink data frame comes from; The module ID field is used to identify the module type and model of the sending end; The data content field is used to carry IO acquisition data and slot module status information; The verification field is used to detect transmission errors.

[0045] Furthermore, the data content field of the uplink data frame can also include a command type subfield, a data length subfield, and a payload subfield. The command type subfield is used to indicate whether the uplink data frame is a data acquisition frame or a status reporting frame. The data length subfield is used to characterize the payload length. The payload subfield is used to carry specific IO acquisition data or status parameters. The data length configuration range is 1 byte to 256 bytes.

[0046] After detecting the preset edge trigger signal on the receive enable line, each CPLD slot module sequentially transmits uplink data frames via the uplink communication bus in ascending order of slot number. In this embodiment, the preset edge trigger signal is the falling edge of the receive enable line switching from high to low. Upon detecting this falling edge, the slot module initiates its own uplink data frame transmission. After completing its transmission, the module controls the transmit enable line to output a trigger pulse to trigger the next slot module (with a slot number one greater than its own) to transmit its uplink data frame, thus forming a sequential backhaul process.

[0047] To ensure the triggering rules are clear and feasible, this embodiment adopts the following trigger pulse generation formula: ; in, Indicates the slot number is The duration of the high level on the transmit enable line output by the slot module; Indicates the basic pulse width; This is the slot number for this module.

[0048] Slot number is When a slot module receives a high-level trigger pulse on the transmit enable line during the uplink phase, it determines whether the trigger pulse is a transmit start flag for its own slot number. If the determination is successful, uplink data frame transmission is initiated. Thus, the incrementing rule of the transmit enable line trigger pulse and the slot number determination mechanism form a closed loop, ensuring that the sequential return process can be stably implemented by hardware timing.

[0049] To ensure stable execution of the sequential backhaul process, each CPLD slot module is equipped with an uplink transmission state machine. This state machine includes at least three states: a wait-to-trigger state, a transmitting state, and a transmission-complete state. In the wait-to-trigger state, the slot module monitors the preset edge trigger signal of the receive enable line; upon detecting the trigger signal, it enters the transmitting state and transmits its own uplink data frame; after transmission is complete, it enters the transmission-complete state and outputs a trigger pulse to the transmit enable line, then returns to the wait-to-trigger state. Through this state machine, the slot module only occupies the uplink communication bus when triggered during the entire uplink phase, thus avoiding concurrent transmissions.

[0050] During the effective window of the uplink phase, except for the slot module that is triggered to start sending, other slot modules remain in a waiting state and do not actively occupy the uplink communication bus, so as to further reduce the probability of concurrent conflicts.

[0051] The transmit enable line is driven by different nodes at different stages: At the start of system initialization or the uplink phase, the ARM coupler outputs a preset transmit enable pulse to trigger the CPLD slot module with slot number 1 to start transmitting; during sequential return, each CPLD slot module drives the transmit enable line to output a trigger pulse after completing its own transmission to trigger the next slot module to transmit. To avoid multi-source drive conflicts, the transmit enable line's drive port adopts a tri-state output mode, with non-current drive nodes maintaining a high-impedance state, ensuring that the transmit enable line is effectively driven by only one drive source at any given time.

[0052] In this embodiment, the verification field is a cyclic redundancy check code. The ARM coupler and CPLD slot module perform consistency verification on the cyclic redundancy check code after receiving the data frame.

[0053] CRC is generated using a generator polynomial. Modulo-2 division. Let the message polynomial corresponding to the bit sequence to be verified be... The length of the check bit is The polynomial corresponding to the CRC checksum is: ; in, This is the message polynomial obtained by concatenating the frame header field and the data content field; The length of the check bit; Generate a predefined polynomial; This is a CRC checksum.

[0054] The sending end will Write the check field. The receiving end performs the same modulo-2 operation on the corresponding bit sequence of the received frame. If the remainder is zero or matches the received check field, the check is considered successful.

[0055] When the verification passes, the ARM coupler extracts the data content field and uploads it to the host network. When the verification fails, the ARM coupler discards the corresponding data frame and records the verification failure count. When the verification failure count reaches a preset threshold, the corresponding slot module is marked as an abnormal node for online module table updates. The preset threshold can be configured according to the link bit error rate and system reliability requirements to avoid misjudgments caused by occasional bit errors.

[0056] The ARM coupler counts the number of received uplink data frames within a preset time window and establishes an online module table based on the sender sequence number field and module ID field in the uplink data frames. The online module table records at least the slot sequence number, module ID, last valid reception time, and check failure count.

[0057] The preset time window can consist of multiple consecutive communication cycles, and the window length is a configurable parameter. When the number of received uplink data frames changes within the preset time window, the ARM coupler updates the online module table to identify the offline or hot-plugged status of the slot module. If uplink data frames corresponding to a certain slot number are continuously missing for multiple consecutive communication cycles, it can be determined that the slot module is offline or the link is abnormal; when the slot number resumes uplink transmission and the verification passes, it can be determined that it has been inserted or restored to online status.

[0058] In this embodiment, the downlink and uplink communication buses can be implemented using independent bus transceiver channels. The synchronization line can be implemented using the general-purpose I / O port output of the ARM coupler. The transmit enable line and receive enable line can be implemented using the timer output and input capture resources of the ARM coupler. The slot number counting, frame parsing, trigger control, and transmit state machine in the CPLD slot module can all be implemented using synthesizable logic. Based on the description of this embodiment, those skilled in the art can complete the implementation through conventional hardware design and firmware programming.

[0059] This invention utilizes an ARM coupler and multiple CPLD slot modules to form a distributed I / O network. The ARM coupler and each CPLD slot module are connected via a communication bus, which includes a downlink communication bus, an uplink communication bus, a synchronization line, a transmit enable line, and a receive enable line. This invention uses the communication cycle as the basic scheduling unit, sequentially completing downlink control command distribution, synchronous execution and acquisition, and uplink sequential transmission and verification transmission within each communication cycle, thereby achieving highly real-time and highly consistent distributed I / O communication.

[0060] During system power-up or initialization, the ARM coupler outputs a valid pulse for sequence number identification on the receive enable line. Each CPLD slot module measures the duration of the valid level on the receive enable line and determines the slot number n using a preset basic pulse width T0 as the counting unit. Each slot module latches the slot number for parsing the receiver sequence number field and filling in the transmitter sequence number field in subsequent communication cycles. This ensures that each slot module in the network has a unique and stable logical identifier, avoiding the maintenance complexity caused by relying on DIP switches or software-written addresses.

[0061] After receiving I / O control commands from the host network, the ARM coupler establishes a downlink transmission queue and encapsulates the I / O control commands into downlink data frames according to a preset frame structure, writing them into the downlink transmission queue. The downlink data frame includes a frame header field, a receiver sequence number field, a module ID field, a data content field, and a checksum field.

[0062] The receiver sequence number field indicates the target slot module, the module ID field identifies the type or model of the target module, the data content field carries control command parameters, and the checksum field is used for transmission error detection. By carrying the receiver sequence number field in the downlink data frame, each CPLD slot module only receives and executes data frames with the same slot sequence number as its own when receiving downlink data frames. Other data frames are discarded, and the current IO output state remains unchanged. This achieves targeted distribution of downlink control commands and avoids the risk of misexecution caused by broadcast reception.

[0063] When each communication cycle is triggered, the ARM coupler controls the synchronization line to be at the first level and continuously sends multiple downlink data frames in the downlink transmission queue through the downlink communication bus, so that each slot module can complete the reception and buffering of control data within the same communication cycle.

[0064] After the downlink data frame is transmitted, the ARM coupler controls the synchronization line to switch to the second level. The level switching edge of the synchronization line serves as a synchronization trigger signal. Upon detecting the synchronization trigger signal, each CPLD slot module synchronously executes its corresponding IO output action and simultaneously initiates IO acquisition. Since synchronous triggering does not rely on per-module polling or per-module triggering, it can significantly reduce the time dispersion between multi-module output actions and acquisition actions, ensure acquisition window alignment, and improve the time consistency and comparability of acquired data.

[0065] After synchronous acquisition is completed, each CPLD slot module encapsulates the acquired data into uplink data frames. The uplink data frame includes a frame header field, a sender sequence number field, a module ID field, a data content field, and a checksum field. The sender sequence number field identifies the slot number from which this frame originates, the module ID field identifies the type or model of the sending module, and the data content field carries the acquired data or status parameters.

[0066] Upon entering the uplink phase, each CPLD slot module initiates uplink backhaul after detecting the preset edge trigger signal on the receive enable line, and sequentially transmits uplink data frames via the uplink communication bus in ascending order of slot number. To ensure a strictly sequential backhaul process, after completing its uplink data frame transmission, the CPLD slot module with slot number n controls the transmit enable line to output a trigger pulse to trigger the transmission of the CPLD slot module with slot number n+1, causing the CPLD slot module with slot number n+1 to begin transmitting its uplink data frame, thus forming a cascaded triggered sequential backhaul process.

[0067] During this sequential backhaul, the receive enable line indicates the start time of uplink transmission, and the transmit enable line transmits the transmission start flag between adjacent slot modules. Since only the triggered slot module is allowed to occupy the uplink communication bus at any given time, the bus remains continuously occupied during the sequential backhaul of multiple slot modules, avoiding bus idle waiting and bus preemption conflicts caused by multiple slot modules transmitting simultaneously. This improves uplink bandwidth utilization and reduces communication cycle jitter.

[0068] During the uplink phase, the ARM coupler receives uplink data frames from each slot module and performs verification processing based on the verification field. When the verification passes, the ARM coupler extracts the data content field and uploads it to the host network, realizing a closed-loop monitoring and control system for the distributed I / O network by the host device. When the verification fails, the ARM coupler discards the corresponding data frame and records the verification failure count to prevent erroneous data from participating in host business decisions.

[0069] To achieve self-monitoring of network operation status, the ARM coupler counts the number of received uplink data frames within a preset time window and establishes an online module table based on the sender sequence number and module ID fields in the uplink data frames. The online module table records information such as slot sequence number, module ID, last valid reception time, and verification failure count. When the number of received uplink data frames changes within the preset time window, the ARM coupler updates the online module table to identify the disconnection or hot-plugging status of the slot module, and can provide alarm prompts or adjust operating strategies on the host network side.

[0070] This embodiment achieves synchronous triggering through a synchronization line, determines the slot number by receiving valid pulse parameters from the enable line, and achieves sequential backhaul through cascading triggering of the enable line. During the uplink phase, it maintains continuous occupation of the uplink communication bus, avoiding bus preemption conflicts caused by concurrent transmissions from multiple nodes. The aforementioned synchronous triggering mechanism, slot number determination mechanism, and sequential backhaul cascading triggering mechanism work together within the same communication cycle to form a closed-loop communication process of continuous downlink transmission, unified synchronous triggering action, and sequential uplink backhaul with continuous bus occupation. This results in a stable improvement in real-time performance and bus utilization.

[0071] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-performance distributed I / O communication method based on ARM+CPLD, applied to a distributed I / O network consisting of an ARM coupler and multiple CPLD slot modules. The ARM coupler is connected to each CPLD slot module via a communication bus, which includes a downlink communication bus, an uplink communication bus, a synchronization line, a transmit enable line, and a receive enable line. Its distinguishing feature is that... The method includes the following steps: S1: The ARM coupler establishes a downlink transmission queue, receives IO control commands from the host network, encapsulates the IO control commands into downlink data frames according to the preset frame structure, and writes them into the downlink transmission queue. Downlink data frames include a frame header field, a receiver sequence number field, a module ID field, a data content field, and a checksum field; S2: When each communication cycle is triggered, the ARM coupler controls the synchronization line to be at the first level and continuously sends multiple downlink data frames in the downlink transmission queue via the downlink communication bus; S3: After the downlink data frame is sent, the ARM coupler controls the synchronization line to switch to the second level to trigger each CPLD slot module to synchronously execute the corresponding IO output action and synchronously start the IO acquisition action; S4: Each CPLD slot module determines its own slot number by detecting the valid pulse parameters of the receive enable line, and parses the receiver sequence number field when receiving downlink data frames. When the receiver sequence number matches its own slot number, it receives the data content field of the downlink data frame and executes the corresponding IO control command. Determining the slot number in step S4 includes: The CPLD slot module uses clock counting to measure the effective level duration of the receive enable line, based on a preset basic pulse width. As a counting unit, when the effective level duration is Multiply At that time, the slot number is determined as ,in It is a positive integer; S5: Each CPLD slot module encapsulates the collected data into uplink data frames. The uplink data frame includes a frame header field, a sender sequence number field, a module ID field, a data content field, and a check field. After detecting the preset edge trigger signal of the receive enable line, each CPLD slot module sequentially sends uplink data frames via the uplink communication bus in ascending order of slot number; the slot number is... After the CPLD slot module completes its uplink data frame transmission, the control transmit enable line output is used to trigger the slot with the sequence number [slot number missing]. The CPLD slot module sends a trigger pulse to increase the slot number by 1. The CPLD slot module with slot 1 incremented begins sending its uplink data frames, thus forming a sequential backhaul process; S6: The ARM coupler receives each uplink data frame and performs the corresponding verification processing for the verification field. After the verification is successful, the data content field is extracted and uploaded to the host network.

2. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 1, characterized in that, Step S1 includes: The ARM coupler initializes the buffer for storing downlink data frames and the receive buffer for storing uplink data frames, and initializes the timer to generate a communication cycle trigger signal, so that downlink transmission and uplink reception are executed at fixed cycles; The ARM coupler will send a pulse signal configured to periodically output the enable line for timing coordination during the slot module sending process.

3. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 2, characterized in that, Steps S2 to S3 satisfy the following timing rules: The ARM coupler keeps the synchronization line low during the continuous transmission of multiple downlink data frames, and switches the synchronization line high after the last downlink data frame is transmitted and holds it for a preset time. Each CPLD slot module synchronously executes IO output and synchronously starts IO acquisition after detecting the rising edge of the synchronization line.

4. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 3, characterized in that, The data content fields of the downlink and uplink data frames include: The command type subfield is used to indicate whether the data frame is a control command frame, a configuration parameter frame, or a status query frame; The data length subfield is used to characterize the length of the payload in bytes; The payload subfield is used to carry IO output parameters, IO acquisition data, or slot module status parameters; The data length configuration range is from 1 byte to 256 bytes.

5. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 4, characterized in that, Step S4 includes: When the sequence number of the receiving end matches the sequence number of its own slot, the IO control command corresponding to the downlink data frame is executed; When the sequence number of the receiving end is inconsistent with its own slot sequence number, the downlink data frame is discarded and the current IO output state remains unchanged.

6. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 5, characterized in that, Step S5 includes: The CPLD slot module initiates uplink data frame transmission after detecting a falling edge that switches the receive enable line from high to low. After the CPLD slot module completes its transmission, it outputs a trigger pulse. The trigger pulse is a high-level pulse on the transmit enable line. The duration of the high-level trigger pulse is set incrementally according to the slot number of this module, serving as the transmit start indicator for the next slot module.

7. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 6, characterized in that, During the sequential backhaul process: The receive enable line is used to indicate the start time of uplink transmission from the slot module; The transmit enable line is used to indicate the end time of the slot module's uplink transmission; Once a slot module finishes sending, the next slot module is triggered to start sending. The bus remains continuously occupied during the sequential return of multiple slot modules, avoiding bus idle waiting and bus preemption conflicts caused by multiple slot modules sending at the same time.

8. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 7, characterized in that, The method further includes: The ARM coupler counts the number of received uplink data frames within a preset time window and establishes an online module table based on the sender sequence number field and module ID field in the uplink data frames. When the number of uplink data frames received within a preset time window changes, the online module table is updated to identify the disconnection or hot-plugging status of the slot module.

9. The high-performance distributed I / O communication method based on ARM+CPLD according to claim 8, characterized in that, The verification field is a cyclic redundancy check code. The ARM coupler and CPLD slot module perform consistency verification on the cyclic redundancy check code after receiving the data frame. When the verification passes, the data content fields are extracted and used for interaction with the higher-level network. When a verification fails, the corresponding data frame is discarded and the verification failure count is recorded. When the verification failure count reaches a preset threshold, the corresponding slot module is marked as an abnormal node for online module table updates.

Images